% problem-set/circuits/design_or.ver1.clauses % created : 08/28/86 % revised : 07/11/88 % description: % % This run designs an OR gate, using NAND gates. % representation: % % This input file came with no explanation of % the representation. -Tab(x1,x2,x3,x4) | -Tab(y1,y2,y3,y4) | Tab(nand(x1,y1),nand(x2,y2),nand(x3,y3),nand(x4,y4)). -Tab(0,1,1,1). Tab(0,0,1,1). Tab(0,1,0,1). Equal(nand(x,y),not(and(x,y))). Equal(and(x,0),0). Equal(and(x,1),x). Equal(not(0),1). Equal(not(1),0).