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00009 #ifndef PXA_H
00010 # define PXA_H "pxa.h"
00011
00012
00013 # define PXA2XX_PIC_SSP3 0
00014 # define PXA2XX_PIC_USBH2 2
00015 # define PXA2XX_PIC_USBH1 3
00016 # define PXA2XX_PIC_KEYPAD 4
00017 # define PXA2XX_PIC_PWRI2C 6
00018 # define PXA25X_PIC_HWUART 7
00019 # define PXA27X_PIC_OST_4_11 7
00020 # define PXA2XX_PIC_GPIO_0 8
00021 # define PXA2XX_PIC_GPIO_1 9
00022 # define PXA2XX_PIC_GPIO_X 10
00023 # define PXA2XX_PIC_I2S 13
00024 # define PXA26X_PIC_ASSP 15
00025 # define PXA25X_PIC_NSSP 16
00026 # define PXA27X_PIC_SSP2 16
00027 # define PXA2XX_PIC_LCD 17
00028 # define PXA2XX_PIC_I2C 18
00029 # define PXA2XX_PIC_ICP 19
00030 # define PXA2XX_PIC_STUART 20
00031 # define PXA2XX_PIC_BTUART 21
00032 # define PXA2XX_PIC_FFUART 22
00033 # define PXA2XX_PIC_MMC 23
00034 # define PXA2XX_PIC_SSP 24
00035 # define PXA2XX_PIC_DMA 25
00036 # define PXA2XX_PIC_OST_0 26
00037 # define PXA2XX_PIC_RTC1HZ 30
00038 # define PXA2XX_PIC_RTCALARM 31
00039
00040
00041 # define PXA2XX_RX_RQ_I2S 2
00042 # define PXA2XX_TX_RQ_I2S 3
00043 # define PXA2XX_RX_RQ_BTUART 4
00044 # define PXA2XX_TX_RQ_BTUART 5
00045 # define PXA2XX_RX_RQ_FFUART 6
00046 # define PXA2XX_TX_RQ_FFUART 7
00047 # define PXA2XX_RX_RQ_SSP1 13
00048 # define PXA2XX_TX_RQ_SSP1 14
00049 # define PXA2XX_RX_RQ_SSP2 15
00050 # define PXA2XX_TX_RQ_SSP2 16
00051 # define PXA2XX_RX_RQ_ICP 17
00052 # define PXA2XX_TX_RQ_ICP 18
00053 # define PXA2XX_RX_RQ_STUART 19
00054 # define PXA2XX_TX_RQ_STUART 20
00055 # define PXA2XX_RX_RQ_MMCI 21
00056 # define PXA2XX_TX_RQ_MMCI 22
00057 # define PXA2XX_USB_RQ(x) ((x) + 24)
00058 # define PXA2XX_RX_RQ_SSP3 66
00059 # define PXA2XX_TX_RQ_SSP3 67
00060
00061 # define PXA2XX_SDRAM_BASE 0xa0000000
00062 # define PXA2XX_INTERNAL_BASE 0x5c000000
00063 # define PXA2XX_INTERNAL_SIZE 0x40000
00064
00065
00066 qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
00067
00068
00069 void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
00070 void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
00071
00072
00073 struct pxa2xx_gpio_info_s;
00074 struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
00075 CPUState *env, qemu_irq *pic, int lines);
00076 qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s);
00077 void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s,
00078 int line, qemu_irq handler);
00079 void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler);
00080
00081
00082 struct pxa2xx_dma_state_s;
00083 struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
00084 qemu_irq irq);
00085 struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
00086 qemu_irq irq);
00087 void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on);
00088
00089
00090 struct pxa2xx_lcdc_s;
00091 struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
00092 qemu_irq irq);
00093 void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler);
00094 void pxa2xx_lcdc_oritentation(void *opaque, int angle);
00095
00096
00097 struct pxa2xx_mmci_s;
00098 struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
00099 BlockDriverState *bd, qemu_irq irq, void *dma);
00100 void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly,
00101 qemu_irq coverswitch);
00102
00103
00104 struct pxa2xx_pcmcia_s;
00105 struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base);
00106 int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card);
00107 int pxa2xx_pcmcia_dettach(void *opaque);
00108 void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
00109
00110
00111 struct keymap {
00112 int column;
00113 int row;
00114 };
00115 struct pxa2xx_keypad_s;
00116 struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base,
00117 qemu_irq irq);
00118 void pxa27x_register_keypad(struct pxa2xx_keypad_s *kp, struct keymap *map,
00119 int size);
00120
00121
00122 struct pxa2xx_ssp_s;
00123 void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
00124 uint32_t (*readfn)(void *opaque),
00125 void (*writefn)(void *opaque, uint32_t value), void *opaque);
00126
00127 struct pxa2xx_i2c_s;
00128 struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
00129 qemu_irq irq, uint32_t page_size);
00130 i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s);
00131
00132 struct pxa2xx_i2s_s;
00133 struct pxa2xx_fir_s;
00134
00135 struct pxa2xx_state_s {
00136 CPUState *env;
00137 qemu_irq *pic;
00138 qemu_irq reset;
00139 struct pxa2xx_dma_state_s *dma;
00140 struct pxa2xx_gpio_info_s *gpio;
00141 struct pxa2xx_lcdc_s *lcd;
00142 struct pxa2xx_ssp_s **ssp;
00143 struct pxa2xx_i2c_s *i2c[2];
00144 struct pxa2xx_mmci_s *mmc;
00145 struct pxa2xx_pcmcia_s *pcmcia[2];
00146 struct pxa2xx_i2s_s *i2s;
00147 struct pxa2xx_fir_s *fir;
00148 struct pxa2xx_keypad_s *kp;
00149
00150
00151 target_phys_addr_t pm_base;
00152 uint32_t pm_regs[0x40];
00153
00154
00155 target_phys_addr_t cm_base;
00156 uint32_t cm_regs[4];
00157 uint32_t clkcfg;
00158
00159
00160 target_phys_addr_t mm_base;
00161 uint32_t mm_regs[0x1a];
00162
00163
00164 uint32_t pmnc;
00165
00166
00167 target_phys_addr_t rtc_base;
00168 uint32_t rttr;
00169 uint32_t rtsr;
00170 uint32_t rtar;
00171 uint32_t rdar1;
00172 uint32_t rdar2;
00173 uint32_t ryar1;
00174 uint32_t ryar2;
00175 uint32_t swar1;
00176 uint32_t swar2;
00177 uint32_t piar;
00178 uint32_t last_rcnr;
00179 uint32_t last_rdcr;
00180 uint32_t last_rycr;
00181 uint32_t last_swcr;
00182 uint32_t last_rtcpicr;
00183 int64_t last_hz;
00184 int64_t last_sw;
00185 int64_t last_pi;
00186 QEMUTimer *rtc_hz;
00187 QEMUTimer *rtc_rdal1;
00188 QEMUTimer *rtc_rdal2;
00189 QEMUTimer *rtc_swal1;
00190 QEMUTimer *rtc_swal2;
00191 QEMUTimer *rtc_pi;
00192 };
00193
00194 struct pxa2xx_i2s_s {
00195 qemu_irq irq;
00196 struct pxa2xx_dma_state_s *dma;
00197 void (*data_req)(void *, int, int);
00198
00199 uint32_t control[2];
00200 uint32_t status;
00201 uint32_t mask;
00202 uint32_t clk;
00203
00204 int enable;
00205 int rx_len;
00206 int tx_len;
00207 void (*codec_out)(void *, uint32_t);
00208 uint32_t (*codec_in)(void *);
00209 void *opaque;
00210
00211 int fifo_len;
00212 uint32_t fifo[16];
00213 };
00214
00215 # define PA_FMT "0x%08lx"
00216 # define REG_FMT "0x" TARGET_FMT_plx
00217
00218 struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision);
00219 struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size);
00220
00221
00222 void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
00223 qemu_irq irq);
00224
00225 #endif