00001 #ifndef QEMU_SH_H
00002 #define QEMU_SH_H
00003
00004
00005 #include "sh_intc.h"
00006
00007 #define A7ADDR(x) ((x) & 0x1fffffff)
00008 #define P4ADDR(x) ((x) | 0xe0000000)
00009
00010
00011 struct SH7750State;
00012
00013 struct SH7750State *sh7750_init(CPUState * cpu);
00014
00015 typedef struct {
00016
00017 uint16_t portamask_trigger;
00018 uint16_t portbmask_trigger;
00019
00020 int (*port_change_cb) (uint16_t porta, uint16_t portb,
00021 uint16_t * periph_pdtra,
00022 uint16_t * periph_portdira,
00023 uint16_t * periph_pdtrb,
00024 uint16_t * periph_portdirb);
00025 } sh7750_io_device;
00026
00027 int sh7750_register_io_device(struct SH7750State *s,
00028 sh7750_io_device * device);
00029
00030 #define TMU012_FEAT_TOCR (1 << 0)
00031 #define TMU012_FEAT_3CHAN (1 << 1)
00032 #define TMU012_FEAT_EXTCLK (1 << 2)
00033 void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
00034 qemu_irq ch0_irq, qemu_irq ch1_irq,
00035 qemu_irq ch2_irq0, qemu_irq ch2_irq1);
00036
00037
00038
00039 #define SH_SERIAL_FEAT_SCIF (1 << 0)
00040 void sh_serial_init (target_phys_addr_t base, int feat,
00041 uint32_t freq, CharDriverState *chr,
00042 qemu_irq eri_source,
00043 qemu_irq rxi_source,
00044 qemu_irq txi_source,
00045 qemu_irq tei_source,
00046 qemu_irq bri_source);
00047
00048
00049 qemu_irq sh7750_irl(struct SH7750State *s);
00050
00051
00052 int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2);
00053
00054
00055 void mmio_ide_init(target_phys_addr_t membase, target_phys_addr_t membase2,
00056 qemu_irq irq, int shift,
00057 BlockDriverState *hd0, BlockDriverState *hd1);
00058 #endif