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sst/elements/genericProc/ssBackEnd/ssb_machine.h

00001 #ifndef SSB_MACHINE_H
00002 #define SSB_MACHINE_H
00003 
00004 /* * powerpc.h - PowerPC definitions
00005  *
00006  * This file is a part of the SimpleScalar tool suite written by
00007  * Todd M. Austin as a part of the Multiscalar Research Project.
00008  *  
00009  * The tool suite is currently maintained by Doug Burger and Todd M. Austin.
00010  * 
00011  * Copyright (C) 1994, 1995, 1996, 1997, 1998 by Todd M. Austin
00012  *
00013  * This source file is distributed "as is" in the hope that it will be
00014  * useful.  The tool set comes with no warranty, and no author or
00015  * distributor accepts any responsibility for the consequences of its
00016  * use. 
00017  * 
00018  * Everyone is granted permission to copy, modify and redistribute
00019  * this tool set under the following conditions:
00020  * 
00021  *    This source code is distributed for non-commercial use only. 
00022  *    Please contact the maintainer for restrictions applying to 
00023  *    commercial use.
00024  *
00025  *    Permission is granted to anyone to make or distribute copies
00026  *    of this source code, either as received or modified, in any
00027  *    medium, provided that all copyright notices, permission and
00028  *    nonwarranty notices are preserved, and that the distributor
00029  *    grants the recipient permission for further redistribution as
00030  *    permitted by this document.
00031  *
00032  *    Permission is granted to distribute this file in compiled
00033  *    or executable form under the same conditions that apply for
00034  *    source code, provided that either:
00035  *
00036  *    A. it is accompanied by the corresponding machine-readable
00037  *       source code,
00038  *    B. it is accompanied by a written offer, with no time limit,
00039  *       to give anyone a machine-readable copy of the corresponding
00040  *       source code in return for reimbursement of the cost of
00041  *       distribution.  This written offer must permit verbatim
00042  *       duplication by anyone, or
00043  *    C. it is distributed by someone who received only the
00044  *       executable form, and is accompanied by a copy of the
00045  *       written offer of source code that they received concurrently.
00046  *
00047  * In other words, you are welcome to use, share and improve this
00048  * source file.  You are forbidden to forbid anyone else to use, share
00049  * and improve what you give them.
00050  *
00051  * INTERNET: dburger@cs.wisc.edu
00052  * US Mail:  1210 W. Dayton Street, Madison, WI 53706
00053  *
00054  *
00055  *
00056  */
00057 
00058 #include "fuClasses.h"
00059 #include "global.h"
00060 
00061 #include <stdio.h>
00062 
00063 #include "ssb_host.h"
00064 #include "ssb_misc.h"
00065 
00066 /*
00067  * This file contains various definitions needed to decode, disassemble, and
00068  * execute PowerPC instructions.
00069  */
00070 
00071 /* build for PowerPC target */
00072 #define TARGET_PPC 
00073 
00074 /* not applicable/available, usable in most definition contexts */
00075 #define NA              0
00076 
00077 /*
00078  * target-dependent type definitions
00079  */
00080 
00081 /* define MD_QWORD_ADDRS if the target requires 64-bit (quadword) addresses */
00082 #undef MD_QWORD_ADDRS
00083 
00084 /* address type definition */
00085 typedef simAddress md_addr_t;
00086 
00087 typedef unsigned long long SS_TIME_TYPE;
00088 
00089 /* inst tag type, used to tag an operation instance in the RUU */
00090 typedef unsigned int INST_TAG_TYPE;
00091 
00092 /* inst sequence type, used to order instructions in the ready list, if
00093    this rolls over the ready list order temporarily will get messed up,
00094    but execution will continue and complete correctly */
00095 typedef unsigned int INST_SEQ_TYPE;
00096 
00097 
00098 /*
00099  * target-dependent memory module configuration
00100  */
00101 
00102 /* physical memory page size (must be a power-of-two) */
00103 #define MD_PAGE_SIZE            4096
00104 /*Base 2 Logarithm of the physical memory page size*/
00105 #define MD_LOG_PAGE_SIZE        12
00106 
00107 
00108 /*
00109  * target-dependent instruction faults
00110  */
00111 
00112 enum md_fault_type {
00113   md_fault_none = 0,            /* no fault */
00114   md_fault_access,              /* storage access fault */
00115   md_fault_alignment,           /* storage alignment fault */
00116   md_fault_overflow,            /* signed arithmetic overflow fault */
00117   md_fault_div0,                /* division by zero fault */
00118   md_fault_break,               /* BREAK instruction fault */
00119   md_fault_unimpl,              /* unimplemented instruction fault */
00120   md_fault_invalidinstruction,  /* PowerPC has an invalid instruction fault */
00121   md_fault_internal             /* internal S/W fault */
00122 };
00123 
00124 
00125 /*
00126  * target-dependent register file definitions, used by regs.[hc]
00127  */
00128 
00129 /* number of integer registers */
00130 #define MD_NUM_IREGS            32
00131 #define MD_NUM_LREGS            1
00132 #define MD_NUM_CTRREGS  1
00133 
00134 /* number of floating point registers */
00135 #define MD_NUM_FREGS            32
00136 
00137 /* number of control registers */
00138 #define MD_NUM_CREGS            3
00139 
00140 /* total number of registers, excluding PC and NPC */
00141 #define MD_TOTAL_REGS                                                   \
00142   (/*int*/32 + /*fp*/32 + /*condition*/1 + /*fpscr*/1 + /*xer*/1 + /*lr*/1+/*ctr*/1)
00143 
00144 /* general purpose (integer) register file entry type */
00145 typedef sword_t md_gpr_t[MD_NUM_IREGS];
00146 
00147 /* floating point register file entry type */
00148 
00149 /*IMP:This structure is different from the PISA/Alpha because PowerPC has 64 bit FP registers*/
00150 
00151 typedef struct {
00152   dfloat_t d[MD_NUM_FREGS];     /* floating point view */
00153 } md_fpr_t;
00154 
00155 /* control register file contents */
00156 typedef struct {
00157   word_t cr, xer;               /* control register and XER register */
00158   word_t fpscr;                 /* floating point status and condition regsiter */
00159 } md_ctrl_t;
00160 
00161 
00162 typedef word_t md_link_t;      /* link regsiter */
00163 typedef word_t md_ctr_t;       /* counter register */
00164 
00165 
00166 /*
00167  * To see the system call conventions on Linux for PPC see
00168  * http://lxr.linux.no/source/include/asm-ppc/unistd.h
00169  *
00170  */
00171 
00172 
00173 /*
00174  * target-dependent instruction format definition
00175  */
00176 /*PowerPc has a 32 bit instruction*/
00177 /* instruction formats */
00178 typedef word_t md_inst_t;
00179 
00180 /* preferred nop instruction definition */
00181 extern md_inst_t MD_NOP_INST;
00182 
00183 
00184 /*
00185  * target-dependent loader module configuration
00186  */
00187 /*For PowerPC other segments starting address is read from the file header by the
00188 loader. So no need to spefcify other segments*/
00189 
00190 /* virtual memory segment limits */
00191 
00192 #define MD_STACK_BASE   0x80000000
00193 
00194 /* maximum size of argc+argv+envp environment */
00195 #define MD_MAX_ENVIRON  131072 /* For PPC :- PAGE_SIZE*MAX_ARG_PAGES . To see this
00196 information, you will have to see the Linux source files as mentioned above*/ 
00197 
00198 
00199 /*
00200  * machine.def specific definitions
00201  */
00202 
00203 /* returns the opcode field value of PowerPC instruction INST */
00204 
00205 /* inst -> enum md_opcode mapping, use this macro to decode insts */
00206 #define MD_TOP_OP(INST)         (((INST) >> 26) & 0x3f)
00207 #define MD_SET_OPCODE(OP, INST)                                        \
00208  {      OP = md_mask2op[((INST>>26)&0x3f)];                            \
00209         while (md_opmask[OP][md_check_mask(INST)])                     \
00210           OP = md_mask2op[((INST) & md_opmask[OP][md_check_mask(INST)])\
00211                          + md_opoffset[OP]];   }
00212 
00213 
00214 
00215 
00216 /* global opcode names, these are returned by the decoder (MD_OP_ENUM()) */
00217 
00218 enum md_opcode {OP_NA=0, OP_MAX};
00219 
00220 #undef DEFINST 
00221 
00222 /* largest opcode field value */
00223 #define MD_MAX_MASK             8192
00224 
00225 
00226 
00227 /* inst -> enum md_opcode mapping, use this macro to decode insts */
00228 #define MD_OP_ENUM(MSK)         (md_mask2op[MSK])
00229 extern enum md_opcode md_mask2op[];
00230 
00231 /* enum md_opcode -> description string */
00232 #define MD_OP_NAME(OP)          (md_op2name[OP])
00233 extern char *md_op2name[];
00234 
00235 /* enum md_opcode -> opcode operand format, used by disassembler */
00236 #define MD_OP_FORMAT(OP)        (md_op2format[OP])
00237 extern char *md_op2format[];
00238 
00239 /* function unit classes, update md_fu2name if you update this definition */
00240 /* Note: the md_fu_class is now defined in fuClasses.h, not here. */
00241 
00242 /* enum md_opcode -> enum md_fu_class, used by performance simulators */
00243 #define MD_OP_FUCLASS(OP)       (md_op2fu[OP])
00244 extern enum md_fu_class md_op2fu[];
00245 
00246 /* enum md_fu_class -> description string */
00247 #define MD_FU_NAME(FU)          (md_fu2name[FU])
00248 extern char *md_fu2name[];
00249 
00250 /* instruction flags */
00251 /* Instruction flags are defined in fuClasses.h, not here. */
00252 
00253 /* enum md_opcode -> opcode flags, used by simulators */
00254 /*#define MD_OP_FLAGS(OP)               (md_op2flags[OP])
00255   extern unsigned int md_op2flags[];*/
00256 
00257 /* integer register specifiers */
00258 #undef  RS      /* defined in /usr/include/sys/syscall.h on HPUX boxes */
00259 
00260 #define RD              ((inst >> 21) & 0x1f)           /* reg dest */
00261 #define RA              ((inst >> 16) & 0x1f)
00262 #define RB              ((inst >> 11) & 0x1f)
00263 #define RC              ((inst >>  6) & 0x1f)
00264 #define RS              RD
00265 
00266 /* floating point register field synonyms */
00267 #define FS              RS
00268 #define FD              RD
00269 #define FB              RB
00270 #define FA              RA
00271 #define FC              RC
00272 
00273 /*Condition registers fields*/
00274 #define CRBD            RD
00275 #define CRBA            RA
00276 #define CRBB            RB
00277 
00278 #define CRFD            ((inst & 0x03800000)>>23)
00279 #define CRFS            ((inst & 0x001C0000)>>18)
00280 
00281 /* Used in decoding the PowerPC instructions*/
00282 #define MTFSFI_FM       ((inst>>17)&0xff)
00283 #define MTFSFI_IMM      ((inst>>12)&0xf)
00284 #define MB              ( (inst & 0x7C0) >> 6  ) 
00285 #define ME              ( (inst & 0x3E) >> 1 )
00286 #define SPR             ( (inst & 0x001FF800) >> 11 ) 
00287 #define SPRVAL          ( (SPR & 0x1F)+((SPR>>5) & 0x1F) )
00288 #define CRM             ( (inst >> 12) & 0xff ) 
00289 #define TO              RD
00290 #define BO              RD
00291 #define BI              RA
00292 #define BD              ( (inst>>2) & 0x3fff )
00293 #define SH              RB
00294 #define NB              RB
00295 #define LK              (inst & 0x1)
00296 
00297 
00298 #define POSZERODP       0x0000000000000000
00299 #define NEGZERODP       0x8000000000000000
00300 #define POSINFDP        0x7ff0000000000000
00301 #define NEGINFDP        0xfff0000000000000
00302 
00303 #define POSZEROSP       0x0000000000000000
00304 #define NEGZEROSP       0x8000000000000000
00305 #define POSINFSP        0x0ff0000000000000
00306 #define NEGINFSP        0x8ff0000000000000
00307 
00308 
00309 /* If this bit is set in certain instructions, they are invalid for the
00310 32 bit implementation*/
00311 #define ISSETL          ((inst & 0x00200000)>>21)
00312 
00313 /* returns 16-bit signed immediate field value */
00314 #define IMM             ((int)((/* signed */short)(inst & 0xffff)))
00315 
00316 /* returns 16-bit unsigned immediate field value */
00317 #define UIMM            (inst & 0xffff)
00318 
00319 /* load/store 16-bit signed offset field value, synonym for imm field */
00320 #define OFS             IMM             /* alias to IMM */
00321 
00322 /* Immediate field value for branch instruction*/
00323 #define LI              ((inst & 0x3fffffc))
00324 
00325 #define SEXT24(X)                                                       \
00326   (((X) & 0x800000) ? ((sword_t)(X) | 0xff000000):(sword_t)(X))
00327 
00328 #define SEXT8(X)                                                        \
00329   (((X) & 0x80) ? ((sword_t)(X) | 0xffffff00):(sword_t)(X))
00330 
00331 
00332 #define SEXT16(X)                                                        \
00333   (((X) & 0x8000) ? ((sword_t)(X) | 0xffff0000):(sword_t)(X))
00334 
00335 #define SEXT26(X)                                                        \
00336   (((X) & 0x2000000) ? ((sword_t)(X) | 0xfc000000):(sword_t)(X))
00337 
00338 /*These functions are used to support floating point computations*/
00339 
00340 int isdpNan(qword_t t);
00341 int isdpSNan(qword_t t);
00342 int isdpQNan(qword_t t);
00343 
00344 int isspNan(qword_t t);
00345 int isspSNan(qword_t t);
00346 int isspQNan(qword_t t);
00347 dfloat_t convertDWToDouble(qword_t q);
00348 
00349 /* largest signed integer */
00350 #define MAXINT_VAL      0x7fffffff
00351 
00352 /* check for overflow in X+Y, both signed */
00353 #define OVER(X,Y)                                                       \
00354   ((((X) > 0) && ((Y) > 0) && (MAXINT_VAL - (X) < (Y)))                 \
00355    || (((X) < 0) && ((Y) < 0) && (-MAXINT_VAL - (X) > (Y))))
00356 
00357 /* check for underflow in X-Y, both signed */
00358 #define UNDER(X,Y)                                                      \
00359   ((((X) > 0) && ((Y) < 0) && (MAXINT_VAL + (Y) < (X)))                 \
00360    || (((X) < 0) && ((Y) > 0) && (-MAXINT_VAL + (Y) > (X))))
00361 
00362 /*Check for the carry bit */
00363 
00364 int carrygenerated(sword_t a, sword_t b);
00365 
00366 /* default target PC handling */
00367 #ifndef SET_TPC
00368 #define SET_TPC(PC)     (void)0
00369 #endif /* SET_TPC */
00370 
00371 /*
00372  * various other helper macros/functions
00373  */
00374 
00375 
00376 /* returns non-zero if instruction is a function call */
00377 #define MD_IS_CALL() ((inst->specificOp() & (F_CTRL|F_CALL)) == (F_CTRL|F_CALL))
00378 
00379 /* returns non-zero if instruction is a function return */
00380 //#define MD_IS_RETURN(OP)              (((OP) == BCLR) && ((LK) == 0))
00381 
00382 /* returns non-zero if instruction is an indirect jump */
00383 //#define MD_IS_INDIR(OP)                       ( ((OP) == BCCTR) ||((OP) == BCCTRL)|| ((OP) == BCLR) ||((OP) == BCLRL) )
00384 #define MD_IS_INDIR(OP)                 (printf("fix MD_IS_INDIR\n"))
00385 
00386 /* addressing mode probe, enums and strings */
00387 enum md_amode_type {
00388   md_amode_imm,         /* immediate addressing mode */
00389   md_amode_gp,          /* global data access through global pointer */
00390   md_amode_sp,          /* stack access through stack pointer */
00391   md_amode_fp,          /* stack access through frame pointer */
00392   md_amode_disp,        /* (reg + const) addressing */
00393   md_amode_rr,          /* (reg + reg) addressing */
00394   md_amode_NUM
00395 };
00396 extern char *md_amode_str[md_amode_NUM];
00397 
00398 /* addressing mode pre-probe FSM, must see all instructions */
00399 /*
00400 #define MD_AMODE_PREPROBE(OP, FSM)                                      \
00401   { if ((OP) == LUI) (FSM) = (RT); }
00402 */
00403 
00404 #define MD_AMODE_PREPROBE(OP, FSM) 
00405 #define MD_AMODE_POSTPROBE(FSM) 
00406 
00407 /* compute addressing mode, only for loads/stores */
00408 /*#define MD_AMODE_PROBE(AM, OP, FSM)                                   \
00409   {                                                                     \
00410     if (MD_OP_FLAGS(OP) & F_DISP)                                       \
00411       {                                                                 \
00412         if ((RA) == MD_REG_SP)                                  \
00413           (AM) = md_amode_sp;                                           \
00414         else                                                            \
00415           (AM) = md_amode_disp;                                         \
00416       }                                                                 \
00417     else if (MD_OP_FLAGS(OP) & F_RR)                                    \
00418       (AM) = md_amode_rr;                                               \
00419     else                                                                \
00420       panic("cannot decode addressing mode");                           \
00421   }
00422 
00423 #define MD_AMODE_PROBE(AM, OP, FSM)                                     \
00424   {                                                                     \
00425     if (MD_OP_FLAGS(OP) & F_DISP)                                       \
00426       {                                                                 \
00427         if ((BS) == (FSM))                                              \
00428           (AM) = md_amode_imm;                                          \
00429         else if ((BS) == MD_REG_GP)                                     \
00430           (AM) = md_amode_gp;                                           \
00431         else if ((BS) == MD_REG_SP)                                     \
00432           (AM) = md_amode_sp;                                           \
00433         else if ((BS) == MD_REG_FP)                                     \
00434           (AM) = md_amode_fp;                                           \
00435         else                                                            \
00436           (AM) = md_amode_disp;                                         \
00437       }                                                                 \
00438     else if (MD_OP_FLAGS(OP) & F_RR)                                    \
00439       (AM) = md_amode_rr;                                               \
00440     else                                                                \
00441       panic("cannot decode addressing mode");                           \
00442   }
00443   */
00444 /* addressing mode pre-probe FSM, after all loads and stores */
00445 /*#define MD_AMODE_POSTPROBE(FSM)      { (FSM) = MD_REG_ZERO; }*/
00446 
00447 
00448 /*
00449  * EIO package configuration/macros
00450  */
00451 
00452 /* expected EIO file format */
00453 #define MD_EIO_FILE_FORMAT              EIO_POWERPC_FORMAT
00454 
00455 #define MD_MISC_REGS_TO_EXO(REGS)                                       \
00456   exo_new(ec_list,                                                      \
00457           /*icnt*/exo_new(ec_integer, (exo_integer_t)sim_num_insn),     \
00458           /*PC*/exo_new(ec_address, (exo_integer_t)(REGS)->regs_PC),    \
00459           /*NPC*/exo_new(ec_address, (exo_integer_t)(REGS)->regs_NPC),  \
00460           /*CR*/exo_new(ec_integer, (exo_integer_t)(REGS)->regs_C.cr),  \
00461           /*XER*/exo_new(ec_integer, (exo_integer_t)(REGS)->regs_C.xer),\
00462           /*FPSCR*/exo_new(ec_integer, (exo_integer_t)(REGS)->regs_C.fpscr),\
00463           NULL)
00464 
00465 #define MD_IREG_TO_EXO(REGS, IDX)                                       \
00466   exo_new(ec_address, (exo_integer_t)(REGS)->regs_R[IDX])
00467 
00468 /*FixMe : Needs to be fixed for PowerPC since PowerPC has 64 bit FP registers*/
00469 
00470 #define MD_FREG_TO_EXO(REGS, IDX)                                       \
00471   exo_new(ec_address, (exo_integer_t)(REGS)->regs_F.d[IDX])
00472 
00473 
00474 
00475 
00476 #define MD_EXO_TO_MISC_REGS(EXO, ICNT, REGS)                            \
00477   /* check EXO format for errors... */                                  \
00478   if (!exo                                                              \
00479       || exo->ec != ec_list                                             \
00480       || !exo->as_list.head                                             \
00481       || exo->as_list.head->ec != ec_integer                            \
00482       || !exo->as_list.head->next                                       \
00483       || exo->as_list.head->next->ec != ec_address                      \
00484       || !exo->as_list.head->next->next                                 \
00485       || exo->as_list.head->next->next->ec != ec_address                \
00486       || !exo->as_list.head->next->next->next                           \
00487       || exo->as_list.head->next->next->next->ec != ec_integer          \
00488       || !exo->as_list.head->next->next->next->next                     \
00489       || exo->as_list.head->next->next->next->next->ec != ec_integer    \
00490       || !exo->as_list.head->next->next->next->next->next               \
00491       || exo->as_list.head->next->next->next->next->next->ec != ec_integer\
00492       || exo->as_list.head->next->next->next->next->next->next != NULL) \
00493     fatal("could not read EIO misc regs");                              \
00494   (ICNT) = (counter_t)exo->as_list.head->as_integer.val;                \
00495   (REGS)->regs_PC = (md_addr_t)exo->as_list.head->next->as_integer.val; \
00496   (REGS)->regs_NPC =                                                    \
00497     (md_addr_t)exo->as_list.head->next->next->as_integer.val;           \
00498   (REGS)->regs_C.cr =                                                   \
00499     (word_t)exo->as_list.head->next->next->next->as_integer.val;        \
00500   (REGS)->regs_C.xer =                                                  \
00501     (word_t)exo->as_list.head->next->next->next->next->as_integer.val;  \
00502   (REGS)->regs_C.fpscr =                                                        \
00503     (int)exo->as_list.head->next->next->next->next->next->as_integer.val;
00504 
00505 #define MD_EXO_TO_IREG(EXO, REGS, IDX)                                  \
00506   ((REGS)->regs_R[IDX] = (word_t)(EXO)->as_integer.val)
00507 
00508 /*FixMe: The registers in PowerPC are double precision - 64 bit*/
00509 
00510 #define MD_EXO_TO_FREG(EXO, REGS, IDX)                                  \
00511   ((REGS)->regs_F.d[IDX] = (word_t)(EXO)->as_integer.val)
00512 
00513 #define MD_EXO_CMP_IREG(EXO, REGS, IDX)                                 \
00514   ((REGS)->regs_R[IDX] != (sword_t)(EXO)->as_integer.val)
00515 
00516 #define MD_FIRST_IN_REG                 0
00517 #define MD_LAST_IN_REG                  31
00518 
00519 #define MD_FIRST_OUT_REG                0
00520 #define MD_LAST_OUT_REG                 31
00521 
00522 
00523 /*
00524  * configure the EXO package
00525  */
00526 
00527 /* EXO pointer class */
00528 typedef word_t exo_address_t;
00529 
00530 /* EXO integer class, 64-bit encoding */
00531 typedef word_t exo_integer_t;
00532 
00533 /* EXO floating point class, 64-bit encoding */
00534 typedef double exo_float_t;
00535 
00536 
00537 /*
00538  * configure the stats package
00539  */
00540 
00541 /* counter stats */
00542 #ifdef HOST_HAS_QWORD
00543 #define stat_reg_counter                stat_reg_squad
00544 #define sc_counter                      sc_squad
00545 #define for_counter                     for_squad
00546 #else /* !HOST_HAS_QWORD */
00547 #define stat_reg_counter                stat_reg_double
00548 #define sc_counter                      sc_double
00549 #define for_counter                     for_double
00550 #endif /* HOST_HAS_QWORD */
00551 
00552 /* address stats */
00553 #define stat_reg_addr                   stat_reg_uint
00554 
00555 
00556 /*
00557  * configure the DLite! debugger
00558  */
00559 
00560 /* register bank specifier */
00561 enum md_reg_type {
00562         rt_lpr,               /* integer-precison floating point register */
00563         rt_fpr,               /* single-precision floating point register */
00564   rt_gpr,               /* general purpose register */
00565   rt_dpr,               /* double-precision floating pointer register */
00566   rt_link,              /* link register */
00567   rt_cntr,              /* counter register */
00568   rt_ctrl,              /* control register */
00569   rt_PC,                /* program counter */
00570   rt_NPC,               /* next program counter */
00571   rt_NUM
00572 };
00573 
00574 /* register name specifier */
00575 //!IGNORE:
00576 struct md_reg_names_t {
00577   char *str;                    /* register name */
00578   enum md_reg_type file;        /* register file */
00579   int reg;                      /* register index */
00580 };
00581 
00582 /* symbolic register names, parser is case-insensitive */
00583 extern md_reg_names_t md_reg_names[];
00584 
00585 /* returns a register name string */
00586 char *md_reg_name(enum md_reg_type rt, int reg);
00587 
00588 /* default register accessor object */
00589 struct eval_value_t;
00590 struct regs_t;
00591 char *                                          /* err str, NULL for no err */
00592 md_reg_obj(struct regs_t *regs,                 /* registers to access */
00593            int is_write,                        /* access type */
00594            enum md_reg_type rt,                 /* reg bank to probe */
00595            int reg,                             /* register number */
00596            struct eval_value_t *val);           /* input, output */
00597 
00598 /* print integer REG(S) to STREAM */
00599 void md_print_ireg(md_gpr_t regs, int reg, FILE *stream);
00600 void md_print_iregs(md_gpr_t regs, FILE *stream);
00601 
00602 /* print floating point REG(S) to STREAM */
00603 void md_print_fpreg(md_fpr_t regs, int reg, FILE *stream);
00604 void md_print_fpregs(md_fpr_t regs, FILE *stream);
00605 
00606 /* print control REG(S) to STREAM */
00607 void md_print_creg(md_ctrl_t regs, int reg, FILE *stream);
00608 void md_print_cregs(md_ctrl_t regs, FILE *stream);
00609 
00610 /* xor checksum registers */
00611 word_t md_xor_regs(struct regs_t *regs);
00612 
00613 
00614 /*
00615  * configure sim-outorder specifics
00616  */
00617 
00618 /* primitive operation used to compute addresses within pipeline */
00619 #define MD_AGEN_OP              ADD
00620 
00621 /* NOP operation when injected into the pipeline */
00622 #define MD_NOP_OP       0x18    
00623 
00624 /* non-zero for a valid address, used to determine if speculative accesses
00625    should access the DL1 data cache */
00626 /*#define MD_VALID_ADDR(ADDR)                                           \
00627   (((ADDR) >= ld_text_base && (ADDR) < (ld_text_base + ld_text_size))   \
00628   || ((ADDR) >= ld_data_base && (ADDR) < ld_stack_base))*/
00629 #define MD_VALID_ADDR(ADDR) (ADDR > 0x100)
00630 
00631 /* this is the address written by the loader for system calls that are imported.
00632 in the 2 word sequence for every sequences, the first word is this value
00633 and the second word is different for each system call. those values
00634 are defined in aixloader.h */
00635 /* in sim-fast we break on a bctr to PPC_SYSCALL_ADDRESS */
00636 #define PPC_SYSCALL_ADDRESS 0x0
00637 
00638 
00639 /*
00640  * configure branch predictors
00641  */
00642 
00643 /* shift used to ignore branch address least significant bits, usually
00644    log2(sizeof(md_inst_t)) */
00645 #define MD_BR_SHIFT             2       /* log2(4) */
00646 
00647 
00648 /*
00649  * target-dependent routines
00650  */
00651 
00652 /* intialize the inst decoder, this function builds the ISA decode tables */
00653 void md_init_decoder(void);
00654 
00655 /* disassemble an instruction */
00656 void
00657 md_print_insn(md_inst_t inst,           /* instruction to disassemble */
00658               md_addr_t pc,             /* addr of inst, used for PC-rels */
00659               FILE *stream);            /* output stream */
00660 
00661 /* defines ripped from semantics.c for the instruction implementations copied from there */
00662 
00663 #define CR_LT_BIT ((unsigned int )0x8)
00664 #define CR_GT_BIT ((unsigned int)0x4)
00665 #define CR_EQ_BIT ((unsigned int)0x2)
00666 #define GET_L(_x)       (((_x) >> 21) &  1)
00667 
00668 #define GET_AA(_x)      (((_x) >>  1) &  1)
00669 #define GET_BA(_x)      (((_x) >> 16) & 31)
00670 #define GET_BB(_x)      (((_x) >> 11) & 31)
00671 #define GET_BD(_x)      ((val) ((int16) ((_x) & -4)))
00672 #define GET_BF(_x)      (((_x) >> 23) &  7)
00673 
00674 #define GET_BO(_x)      (((_x) >> 21) & 31)
00675 #define GET_BI(_x)      (((_x) >> 16) & 31)
00676 #define GET_LK(_x)       ((_x)        &  1)
00677 
00678 #define DECREMENTS_CTR(_x) (0 == (GET_BO (_x) & 4))
00679 #define BR_IF_CTR_ZERO(_x) (GET_BO (_x) & 2)
00680 #define CONDITIONAL_BR(_x) (0 == (GET_BO (_x) & 16))
00681 #define BR_IF_TRUE(_x)     (GET_BO (_x) & 8)
00682 
00683 unsigned int sim_mask32(unsigned int start, unsigned int end);
00684 unsigned int sim_rotate_left_32(unsigned int source, unsigned int count);
00685 
00686 #endif 

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