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sst/core/techModels/libMcPAT/const.h

00001 /*****************************************************************************
00002  *                                McPAT
00003  *                      SOFTWARE LICENSE AGREEMENT
00004  *            Copyright 2009 Hewlett-Packard Development Company, L.P.
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00007  * Permission to use, copy, and modify this software and its documentation is
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00010  * of the software, derivative works or modified versions, and any portions
00011  * thereof, and both notices must appear in supporting documentation.
00012  *
00013  * Any User of the software ("User"), by accessing and using it, agrees to the
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00019  * software by User, including but not limited to those affording
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00048 #ifndef __CONST_H__
00049 #define __CONST_H__
00050 
00051 #include <sst_stdint.h>
00052 #include <stdlib.h>
00053 #include <string.h>
00054 #include <stdio.h>
00055 #include <math.h>
00056 
00057 /*  The following are things you might want to change
00058  *  when compiling
00059  */
00060 
00061 /*
00062  * Address bits in a word, and number of output bits from the cache
00063  */
00064 
00065 /*
00066 was: #define ADDRESS_BITS 32
00067 now: I'm using 42 bits as in the Power4,
00068 since that's bigger then the 36 bits on the Pentium 4
00069 and 40 bits on the Opteron
00070 */
00071 const int ADDRESS_BITS = 42;
00072 
00073 /*dt: In addition to the tag bits, the tags also include 1 valid bit, 1 dirty bit, 2 bits for a 4-state
00074   cache coherency protocoll (MESI), 1 bit for MRU (change this to log(ways) for full LRU).
00075   So in total we have 1 + 1 + 2 + 1 = 5 */
00076 const int EXTRA_TAG_BITS = 5;
00077 
00078 /* limits on the various N parameters */
00079 
00080 const unsigned int MAXDATAN     = 512;      // maximum for Ndwl and Ndbl
00081 const unsigned int MAXSUBARRAYS = 1048576;  // maximum subarrays for data and tag arrays
00082 const unsigned int MAXDATASPD   = 256;      // maximum for Nspd
00083 const unsigned int MAX_COL_MUX  = 256;
00084 
00085 const double Cpolywire = 0;
00086 
00087 
00088 /* Threshold voltages (as a proportion of Vdd)
00089    If you don't know them, set all values to 0.5 */
00090 #define VTHFA1         0.452
00091 #define VTHFA2         0.304
00092 #define VTHFA3         0.420
00093 #define VTHFA4         0.413
00094 #define VTHFA5         0.405
00095 #define VTHFA6         0.452
00096 #define VSINV          0.452
00097 #define VTHCOMPINV     0.437
00098 #define VTHMUXNAND     0.548  // TODO : this constant must be revisited
00099 #define VTHEVALINV     0.452
00100 #define VTHSENSEEXTDRV 0.438
00101 
00102 
00103 //WmuxdrvNANDn and WmuxdrvNANDp are no longer being used but it's part of the old
00104 //delay_comparator function which we are using exactly as it used to be, so just setting these to 0
00105 const double WmuxdrvNANDn = 0;
00106 const double WmuxdrvNANDp = 0;
00107 
00108 
00109 /*===================================================================*/
00110 /*
00111  * The following are things you probably wouldn't want to change.
00112  */
00113 
00114 #define BIGNUM 1e30
00115 #define INF 9999999
00116 #define MAX(a,b) (((a)>(b))?(a):(b))
00117 #define MIN(a,b) (((a)<(b))?(a):(b))
00118 
00119 /* Used to communicate with the horowitz model */
00120 #define RISE 1
00121 #define FALL 0
00122 #define NCH  1
00123 #define PCH  0
00124 
00125 
00126 #define EPSILON 0.5 //v4.1: This constant is being used in order to fix floating point -> integer
00127 //conversion problems that were occuring within CACTI. Typical problem that was occuring was
00128 //that with different compilers a floating point number like 3.0 would get represented as either
00129 //2.9999....or 3.00000001 and then the integer part of the floating point number (3.0) would
00130 //be computed differently depending on the compiler. What we are doing now is to replace
00131 //int (x) with (int) (x+EPSILON) where EPSILON is 0.5. This would fix such problems. Note that
00132 //this works only when x is an integer >= 0.
00133 
00134 #define EPSILON2 0.1
00135 #define EPSILON3 0.6
00136 
00137 
00138 #define MINSUBARRAYROWS 16 //For simplicity in modeling, for the row decoding structure, we assume
00139 //that each row predecode block is composed of at least one 2-4 decoder. When the outputs from the
00140 //row predecode blocks are combined this means that there are at least 4*4=16 row decode outputs
00141 #define MAXSUBARRAYROWS 262144 //Each row predecode block produces a max of 2^9 outputs. So
00142 //the maximum number of row decode outputs will be 2^9*2^9
00143 #define MINSUBARRAYCOLS 2
00144 #define MAXSUBARRAYCOLS 262144
00145 
00146 
00147 #define INV 0
00148 #define NOR 1
00149 #define NAND 2
00150 
00151 
00152 #define NUMBER_TECH_FLAVORS 4
00153 
00154 #define NUMBER_INTERCONNECT_PROJECTION_TYPES 2 //aggressive and conservative
00155 //0 = Aggressive projections, 1 = Conservative projections
00156 #define NUMBER_WIRE_TYPES 4 //local, semi-global and global
00157 //1 = 'Semi-global' wire type, 2 = 'Global' wire type
00158 
00159 
00160 const int dram_cell_tech_flavor = 3;
00161 
00162 
00163 #define VBITSENSEMIN 0.08 //minimum bitline sense voltage is fixed to be 80 mV.
00164 
00165 #define fopt 4.0
00166 
00167 #define INPUT_WIRE_TO_INPUT_GATE_CAP_RATIO 0
00168 #define BUFFER_SEPARATION_LENGTH_MULTIPLIER 1
00169 #define NUMBER_MATS_PER_REDUNDANT_MAT 8
00170 
00171 #define NUMBER_STACKED_DIE_LAYERS 1
00172 
00173 // this variable can be set to carry out solution optimization for
00174 // a maximum area allocation.
00175 #define STACKED_DIE_LAYER_ALLOTED_AREA_mm2 0 //6.24 //6.21//71.5
00176 
00177 // this variable can also be employed when solution optimization
00178 // with maximum area allocation is carried out.
00179 #define MAX_PERCENT_AWAY_FROM_ALLOTED_AREA 50
00180 
00181 // this variable can also be employed when solution optimization
00182 // with maximum area allocation is carried out.
00183 #define MIN_AREA_EFFICIENCY 20
00184 
00185 // this variable can be employed when solution with a desired
00186 // aspect ratio is required.
00187 #define STACKED_DIE_LAYER_ASPECT_RATIO 1
00188 
00189 // this variable can be employed when solution with a desired
00190 // aspect ratio is required.
00191 #define MAX_PERCENT_AWAY_FROM_ASPECT_RATIO 101
00192 
00193 // this variable can be employed to carry out solution optimization
00194 // for a certain target random cycle time.
00195 #define TARGET_CYCLE_TIME_ns 1000000000
00196 
00197 #define NUMBER_PIPELINE_STAGES 4
00198 
00199 /*
00200 // this can be used to model the length of interconnect
00201 // between a bank and a crossbar
00202 #define LENGTH_INTERCONNECT_FROM_BANK_TO_CROSSBAR 0 //3791 // 2880//micron
00203 
00204 #define IS_CROSSBAR 0
00205 #define NUMBER_INPUT_PORTS_CROSSBAR 8
00206 #define NUMBER_OUTPUT_PORTS_CROSSBAR 8
00207 #define NUMBER_SIGNALS_PER_PORT_CROSSBAR 256
00208 
00209 */
00210 #define MAT_LEAKAGE_REDUCTION_DUE_TO_SLEEP_TRANSISTORS_FACTOR 2
00211 #define LEAKAGE_REDUCTION_DUE_TO_LONG_CHANNEL_HP_TRANSISTORS_FACTOR 1
00212 
00213 #define PAGE_MODE 0
00214 
00215 #define MAIN_MEM_PER_CHIP_STANDBY_CURRENT_mA 60
00216 // We are actually not using this variable in the CACTI code. We just want to acknowledge that
00217 // this current should be multiplied by the DDR(n) system VDD value to compute the standby power
00218 // consumed during precharge.
00219 
00220 
00221 const double VDD_STORAGE_LOSS_FRACTION_WORST = 0.125;
00222 const double CU_RESISTIVITY = 0.022; //ohm-micron
00223 const double BULK_CU_RESISTIVITY = 0.018; //ohm-micron
00224 const double PERMITTIVITY_FREE_SPACE = 8.854e-18; //F/micron
00225 
00226 const static uint32_t sram_num_cells_wl_stitching_ = 16;
00227 const static uint32_t dram_num_cells_wl_stitching_ = 64;
00228 const static uint32_t comm_dram_num_cells_wl_stitching_ = 256;
00229 const static uint32_t num_bits_per_ecc_b_          = 8;
00230 const static bool     add_ecc_b_                   = true;
00231 
00232 const int    bit_to_byte  = 8;
00233 
00234 #define MAX_NUMBER_GATES_STAGE 20
00235 #define MAX_NUMBER_HTREE_NODES 20
00236 #define NAND2_LEAK_STACK_FACTOR 0.2
00237 #define NAND3_LEAK_STACK_FACTOR 0.2
00238 #define NOR2_LEAK_STACK_FACTOR 0.2
00239 #define INV_LEAK_STACK_FACTOR  0.5
00240 #define MAX_NUMBER_ARRAY_PARTITIONS 1000000
00241 
00242 
00243 // abbreviations used in this project
00244 // ----------------------------------
00245 //
00246 //  num  : number
00247 //  rw   : read/write
00248 //  rd   : read
00249 //  wr   : write
00250 //  se   : single-ended
00251 //  sz   : size
00252 //  F    : feature
00253 //  w    : width
00254 //  h    : height or horizontal
00255 //  v    : vertical or velocity
00256 
00257 
00258 enum ram_cell_tech_type_num
00259 {
00260   itrs_hp   = 0,
00261   itrs_lstp = 1,
00262   itrs_lop  = 2,
00263   lp_dram   = 3,
00264   comm_dram = 4
00265 };
00266 
00267 #endif

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