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00049 #ifndef __PARAMETER_H__
00050 #define __PARAMETER_H__
00051
00052 #include "area.h"
00053 #include "const.h"
00054 #include "cacti_interface.h"
00055 #include "io.h"
00056
00057
00058
00059 class TechnologyParameter
00060 {
00061 public:
00062 class DeviceType
00063 {
00064 public:
00065 double C_g_ideal;
00066 double C_fringe;
00067 double C_overlap;
00068 double C_junc;
00069 double C_junc_sidewall;
00070 double l_phy;
00071 double l_elec;
00072 double R_nch_on;
00073 double R_pch_on;
00074 double Vdd;
00075 double Vth;
00076 double I_on_n;
00077 double I_on_p;
00078 double I_off_n;
00079 double I_off_p;
00080 double I_g_on_n;
00081 double I_g_on_p;
00082 double C_ox;
00083 double t_ox;
00084 double n_to_p_eff_curr_drv_ratio;
00085
00086 DeviceType(): C_g_ideal(0), C_fringe(0), C_overlap(0), C_junc(0),
00087 C_junc_sidewall(0), l_phy(0), l_elec(0), R_nch_on(0), R_pch_on(0),
00088 Vdd(0), Vth(0),
00089 I_on_n(0), I_on_p(0), I_off_n(0), I_off_p(0),I_g_on_n(0),I_g_on_p(0),
00090 C_ox(0), t_ox(0), n_to_p_eff_curr_drv_ratio(0) { };
00091 void reset()
00092 {
00093 C_g_ideal = 0;
00094 C_fringe = 0;
00095 C_overlap = 0;
00096 C_junc = 0;
00097 l_phy = 0;
00098 l_elec = 0;
00099 R_nch_on = 0;
00100 R_pch_on = 0;
00101 Vdd = 0;
00102 Vth = 0;
00103 I_on_n = 0;
00104 I_on_p = 0;
00105 I_off_n = 0;
00106 I_off_p = 0;
00107 I_g_on_n = 0;
00108 I_g_on_p = 0;
00109 C_ox = 0;
00110 t_ox = 0;
00111 n_to_p_eff_curr_drv_ratio = 0;
00112 }
00113
00114 void display(uint32_t indent = 0);
00115 };
00116 class InterconnectType
00117 {
00118 public:
00119 double pitch;
00120 double R_per_um;
00121 double C_per_um;
00122
00123 InterconnectType(): pitch(0), R_per_um(0), C_per_um(0) { };
00124
00125 void reset()
00126 {
00127 pitch = 0;
00128 R_per_um = 0;
00129 C_per_um = 0;
00130 }
00131
00132 void display(uint32_t indent = 0);
00133 };
00134 class MemoryType
00135 {
00136 public:
00137 double b_w;
00138 double b_h;
00139 double cell_a_w;
00140 double cell_pmos_w;
00141 double cell_nmos_w;
00142 double Vbitpre;
00143
00144 void reset()
00145 {
00146 b_w = 0;
00147 b_h = 0;
00148 cell_a_w = 0;
00149 cell_pmos_w = 0;
00150 cell_nmos_w = 0;
00151 Vbitpre = 0;
00152 }
00153
00154 void display(uint32_t indent = 0);
00155 };
00156
00157 class ScalingFactor
00158 {
00159 public:
00160 double logic_scaling_co_eff;
00161 double core_tx_density;
00162
00163 ScalingFactor(): logic_scaling_co_eff(0), core_tx_density(0) { };
00164
00165 void reset()
00166 {
00167 logic_scaling_co_eff= 0;
00168 core_tx_density = 0;
00169 }
00170
00171 void display(uint32_t indent = 0);
00172 };
00173
00174 double ram_wl_stitching_overhead_;
00175 double min_w_nmos_;
00176 double max_w_nmos_;
00177 double max_w_nmos_dec;
00178 double unit_len_wire_del;
00179 double FO4;
00180 double kinv;
00181 double vpp;
00182 double w_sense_en;
00183 double w_sense_n;
00184 double w_sense_p;
00185 double sense_delay;
00186 double sense_dy_power;
00187 double w_iso;
00188 double w_poly_contact;
00189 double spacing_poly_to_poly;
00190 double spacing_poly_to_contact;
00191
00192 double w_comp_inv_p1;
00193 double w_comp_inv_p2;
00194 double w_comp_inv_p3;
00195 double w_comp_inv_n1;
00196 double w_comp_inv_n2;
00197 double w_comp_inv_n3;
00198 double w_eval_inv_p;
00199 double w_eval_inv_n;
00200 double w_comp_n;
00201 double w_comp_p;
00202
00203 double dram_cell_I_on;
00204 double dram_cell_Vdd;
00205 double dram_cell_I_off_worst_case_len_temp;
00206 double dram_cell_C;
00207 double gm_sense_amp_latch;
00208
00209 double w_nmos_b_mux;
00210 double w_nmos_sa_mux;
00211 double w_pmos_bl_precharge;
00212 double w_pmos_bl_eq;
00213 double MIN_GAP_BET_P_AND_N_DIFFS;
00214 double MIN_GAP_BET_SAME_TYPE_DIFFS;
00215 double HPOWERRAIL;
00216 double cell_h_def;
00217
00218 double chip_layout_overhead;
00219 double macro_layout_overhead;
00220 double sckt_co_eff;
00221
00222 uint64_t h_dec;
00223
00224 DeviceType sram_cell;
00225 DeviceType dram_acc;
00226 DeviceType dram_wl;
00227 DeviceType peri_global;
00228 DeviceType cam_cell;
00229
00230 InterconnectType wire_local;
00231 InterconnectType wire_inside_mat;
00232 InterconnectType wire_outside_mat;
00233
00234 ScalingFactor scaling_factor;
00235
00236 double horiz_dielectric_constant;
00237 double vert_dielectric_constant;
00238 double aspect_ratio;
00239 double miller_value;
00240
00241 MemoryType sram;
00242 MemoryType dram;
00243 MemoryType cam;
00244
00245 void display(uint32_t indent = 0);
00246
00247 void reset()
00248 {
00249 dram_cell_Vdd = 0;
00250 dram_cell_I_on = 0;
00251 dram_cell_C = 0;
00252 vpp = 0;
00253
00254 dram_cell_I_off_worst_case_len_temp = 0;
00255
00256 sram_cell.reset();
00257 dram_acc.reset();
00258 dram_wl.reset();
00259 peri_global.reset();
00260 cam_cell.reset();
00261
00262 scaling_factor.reset();
00263
00264 wire_local.reset();
00265 wire_inside_mat.reset();
00266 wire_outside_mat.reset();
00267
00268 sram.reset();
00269 dram.reset();
00270 cam.reset();
00271
00272 chip_layout_overhead = 0;
00273 macro_layout_overhead = 0;
00274 sckt_co_eff = 0;
00275 }
00276 };
00277
00278
00279
00280 class DynamicParameter
00281 {
00282 public:
00283 bool is_tag;
00284 bool pure_ram;
00285 bool pure_cam;
00286 bool fully_assoc;
00287 int tagbits;
00288 int num_subarrays;
00289 int num_mats;
00290 double Nspd;
00291 int Ndwl;
00292 int Ndbl;
00293 int Ndcm;
00294 int deg_bl_muxing;
00295 int deg_senseamp_muxing_non_associativity;
00296 int Ndsam_lev_1;
00297 int Ndsam_lev_2;
00298 int number_addr_bits_mat;
00299 int number_subbanks_decode;
00300 int num_di_b_bank_per_port;
00301 int num_do_b_bank_per_port;
00302 int num_di_b_mat;
00303 int num_do_b_mat;
00304 int num_di_b_subbank;
00305 int num_do_b_subbank;
00306
00307 int num_si_b_mat;
00308 int num_so_b_mat;
00309 int num_si_b_subbank;
00310 int num_so_b_subbank;
00311 int num_si_b_bank_per_port;
00312 int num_so_b_bank_per_port;
00313
00314 int number_way_select_signals_mat;
00315 int num_act_mats_hor_dir;
00316
00317 int num_act_mats_hor_dir_sl;
00318 bool is_dram;
00319 double V_b_sense;
00320 unsigned int num_r_subarray;
00321 unsigned int num_c_subarray;
00322 int tag_num_r_subarray;
00323 int tag_num_c_subarray;
00324 int data_num_r_subarray;
00325 int data_num_c_subarray;
00326 int num_mats_h_dir;
00327 int num_mats_v_dir;
00328 uint32_t ram_cell_tech_type;
00329 double dram_refresh_period;
00330
00331 DynamicParameter();
00332 DynamicParameter(
00333 bool is_tag_,
00334 int pure_ram_,
00335 int pure_cam_,
00336 double Nspd_,
00337 unsigned int Ndwl_,
00338 unsigned int Ndbl_,
00339 unsigned int Ndcm_,
00340 unsigned int Ndsam_lev_1_,
00341 unsigned int Ndsam_lev_2_,
00342 bool is_main_mem_);
00343
00344 int use_inp_params;
00345 unsigned int num_rw_ports;
00346 unsigned int num_rd_ports;
00347 unsigned int num_wr_ports;
00348 unsigned int num_se_rd_ports;
00349 unsigned int num_search_ports;
00350 unsigned int out_w;
00351 bool is_main_mem;
00352 Area cell, cam_cell;
00353 bool is_valid;
00354 };
00355
00356
00357
00358 extern InputParameter * g_ip;
00359 extern TechnologyParameter g_tp;
00360
00361 #endif
00362