00001 /* 00002 * memory_analyzer.h - memory analyzer 00003 * 00004 * This file is a part of the PowerAnalyzer tool suite written by 00005 * Nam Sung Kim as a part of the PowerAnalyzer Project. 00006 * 00007 * The tool suite is currently maintained by Nam Sung Kim. 00008 * 00009 * Copyright (C) 2001 by Nam Sung Kim 00010 * 00011 * This source file is distributed "as is" in the hope that it will be 00012 * useful. The tool set comes with no warranty, and no author or 00013 * distributor accepts any responsibility for the consequences of its 00014 * use. 00015 * 00016 * Everyone is granted permission to copy, modify and redistribute 00017 * this tool set under the following conditions: 00018 * 00019 * This source code is distributed for non-commercial use only. 00020 * Please contact the maintainer for restrictions applying to 00021 * commercial use. 00022 * 00023 * Permission is granted to anyone to make or distribute copies 00024 * of this source code, either as received or modified, in any 00025 * medium, provided that all copyright notices, permission and 00026 * nonwarranty notices are preserved, and that the distributor 00027 * grants the recipient permission for further redistribution as 00028 * permitted by this document. 00029 * 00030 * Permission is granted to distribute this file in compiled 00031 * or executable form under the same conditions that apply for 00032 * source code, provided that either: 00033 * 00034 * A. it is accompanied by the corresponding machine-readable 00035 * source code, 00036 * B. it is accompanied by a written offer, with no time limit, 00037 * to give anyone a machine-readable copy of the corresponding 00038 * source code in return for reimbursement of the cost of 00039 * distribution. This written offer must permit verbatim 00040 * duplication by anyone, or 00041 * C. it is distributed by someone who received only the 00042 * executable form, and is accompanied by a copy of the 00043 * written offer of source code that they received concurrently. 00044 * 00045 * In other words, you are welcome to use, share and improve this 00046 * source file. You are forbidden to forbid anyone else to use, share 00047 * and improve what you give them. 00048 */ 00049 00050 #ifndef MEMORY_ANALYZER_H 00051 #define MEMORY_ANALYZER_H 00052 #include "./technology.h" 00053 #include "./panalyzer.h" 00054 00055 /* layout parameters */ 00056 #define BitWidth 1.8 /* bit width of RAM cell in um */ 00057 #define BitHeight 3.6 /* bit height of RAM cell in um */ 00058 00059 #define Wmemcella 0.54 00060 #define Wmemcellbscale 3.0 /* means 3x bigger than Wmemcella */ 00061 #define Wmemcelldscale 4.0 /* means 4x bigger than Wmemcella */ 00062 00063 #define krise 0.09e-9 00064 00065 /* threshold voltage of logic gate */ 00066 #define VSINV 0.452 00067 00068 /* memory specification db type */ 00069 typedef struct _fu_memory_spec_t { 00070 char *name; /* memory name */ 00071 /* memory operating parameters: operating frequency/supply voltage */ 00072 double opfreq, svolt; /* operating voltage/frequency */ 00073 unsigned nacycles; /* relative num of access cycle for the given opfreq */ 00074 /* memory size parameters: 00075 * asize: total size, bsize: block size, assoc: associativity 00076 * bunit: number of bits in bsize */ 00077 unsigned nsets, assoc, bsize, asize, bunit; 00078 /* n: number of */ 00079 /* memory sub-array parameters: 00080 * nbls : bitlines, nwls : wordlines, nspds: sets in a wordline */ 00081 unsigned nbls, nwls, nspds; /* sub-array parameters */ 00082 /* memory port parameters: 00083 * rwports: read/write, rports: read, wports: write, nsbanks: sub-banks */ 00084 unsigned nrwports, nrports, nwports, nsbanks; 00085 /* memory bus parameters: 00086 * nsbits: number of bits in bus, sCeff: capacitance (pF) / bus signal */ 00087 unsigned nsbits; double sCeff; 00088 00089 /* capacitance and resistance of interconnect wire */ 00090 double wireCeff, wireReff; 00091 00092 /* time analysis: row decoder, wordline, bitline senseamp, and obus */ 00093 double tdecoder, trow, tcol, tsense, tobus; 00094 /* capacitance analysis: decoder, word-line, bit-line, senseamp */ 00095 fu_Ceffs_t *decoderCeffs, *wlCeffs, *blCeffs, *senseCeffs; 00096 } fu_memory_spec_t; 00097 00098 /* create memory analyzer database 00099 * return an allocated location pointer. 00100 * caution: please deallocate the memory space */ 00101 fu_memory_spec_t * 00102 create_memory_spec( 00103 char *name, /* memory name */ 00104 /* memory operating parameters: operating frequency/supply voltage */ 00105 double opfreq, double svolt, 00106 unsigned nacycles, /* relative num of access cycle for the given opfreq */ 00107 /* memory size parameters: 00108 * nsets: number of sets, bsize: block size, assoc: associativity 00109 * bunit: number of bits in bsize */ 00110 unsigned nsets, unsigned bsize, unsigned assoc, unsigned bunit, 00111 /* n: number of */ 00112 /* memory sub-array parameters: 00113 * nbls : bitlines, nwls : wordlines, nspds: sets in a wordline */ 00114 unsigned nbls, unsigned nwls, unsigned nspds, 00115 /* memory port parameters: 00116 * rwports: read/write, rports: read, wports: write, nsbanks: sub-banks */ 00117 unsigned nrwports, unsigned nrports, unsigned nwports, unsigned nsbanks, 00118 /* nsbits: number of bits in bus, sCeff: capacitance (pF) / bus signal */ 00119 unsigned nsbits, double sCeff); 00120 00121 /* analyze memory pdissipation and access time 00122 * return total access time of the memory structure */ 00123 double 00124 analyze_memory( 00125 fu_memory_spec_t *spec); 00126 00127 /* obtain effective x switching capacitance components from the estimation */ 00128 double 00129 obtain_memory_sCeff( 00130 fu_memory_spec_t *spec); 00131 00132 /* obtain effective internal capacitance components from the estimation */ 00133 double 00134 obtain_memory_iCeff( 00135 fu_memory_spec_t *spec); 00136 00137 /* obtain effective leakage capacitance components from the estimation */ 00138 double 00139 obtain_memory_lCeff( 00140 fu_memory_spec_t *spec); 00141 00142 /* layout parameters: transistor widths */ 00143 #define Wdecdrivep 80.00 00144 #define Wdecdriven 54.00 00145 #define Wdec3to8n 27.00 00146 #define Wdec3to8p 13.50 00147 #define WdecNORn 0.54 00148 #define WdecNORp 0.60 00149 #define Wdecinvn 4.50 00150 #define Wdecinvp 9.00 00151 00152 /* threshold voltage (not Vth) of logic gate */ 00153 #define VTHINV80x54 0.420 /* inverter with p=80, n=54 */ 00154 #define VTHNAND27x13P5 0.522 00155 #define VTHNORP6x4x1 0.503 /* nor with p=12, n=4, 1 input */ 00156 #define VTHNORP6x4x2 0.452 /* nor with p=12, n=4, 2 inputs */ 00157 #define VTHNORP6x4x3 0.417 /* nor with p=12, n=4, 3 inputs */ 00158 #define VTHNORP6x4x4 0.390 /* nor with p=12, n=4, 4 inputs */ 00159 00160 /* analyze row decoder access time and effective switching capacitances. 00161 * return outrise time */ 00162 double 00163 analyze_decoder( 00164 fu_memory_spec_t *spec); 00165 00166 /* layout parameters: transistor widths */ 00167 #define Wworddrivemax 22.5 00168 00169 /* analyze wordline access time and effective switching capacitance. 00170 * return outrise time */ 00171 double analyze_wl( 00172 fu_memory_spec_t *spec, 00173 double trise /* row decoder output rise time */); 00174 00175 /* layout parameters: transistor widths */ 00176 #define Wbitpreequ 18.0 00177 #define Wbitmuxn 2.5 00178 #define Wbitmuxp 4.5 00179 #define WsenseQ1to4 1.0 00180 /* voltage parameters: */ 00181 #define Vbitpre 1.8 /* precharge voltage */ 00182 #define Vbitsense 0.10 /* sensing voltage difference: to be updated */ 00183 00184 /* analyzer bitline access time and effective swiching capacitances. 00185 * return the outrise time */ 00186 double 00187 analyze_bl( 00188 fu_memory_spec_t *spec, 00189 double tinrise /* wline out inrise time */); 00190 00191 00192 /* need to be updated using SPICE simulation */ 00193 #define Tsfall 1.8e-10 00194 #define Tsenseamp 1.3e-10 00195 #define Psenseamp 1.64e-13 00196 00197 /* analyze wordline access time and effective switching capacitance. 00198 * return outrise time */ 00199 double 00200 analyze_sense( 00201 fu_memory_spec_t *spec, 00202 double tinrise /* bitline column mux output rise time */); 00203 00204 /* analyzer bitline access time and effective swiching capacitances. 00205 * return the outrise time */ 00206 double 00207 analyze_ydriver( 00208 fu_memory_spec_t *spec, 00209 double tinrise /* sense out inrise time */); 00210 #endif /* MEMORY_ANALYZER_H */