00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049 #ifndef CORE_H_
00050 #define CORE_H_
00051
00052 #include "XML_Parse.h"
00053 #include "area.h"
00054 #include "decoder.h"
00055 #include "parameter.h"
00056
00057 #include "array.h"
00058 #include "wires.h"
00059 #include "arbiter.h"
00060 #include "Undifferentiated_Core_Area.h"
00061 #include <vector>
00062 #include "basic_components.h"
00063
00064
00065 class processor_core {
00066 public:
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093 virtual void initialize(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_)=0;
00094 virtual void computeMaxPower()=0;
00095 virtual void computeRuntimePower(int ithCore_)=0;
00096 virtual ~processor_core(){};
00097
00098 };
00099
00100
00101 class InorderCore :public processor_core {
00102 public:
00103
00104 ParseXML *XML;
00105 InputParameter interface_ip;
00106 int ithCore;
00107 bool inorder, reservationStationBased, renamingCAM, regWindowing;
00108 int globalCheckpoint, instructionLength;
00109 tlb_core itlb, dtlb;
00110 cache_processor icache, dcache;
00111 BTB_core BTB;
00112 RF_core IRF, FRF, RFWIN, phyIRF, phyFRF;
00113 IB_core IB;
00114 RS_core iRS, iISQ,fRS, fISQ;
00115 LSQ_core LSQ;
00116
00117
00118 resultbus int_bypass,intTagBypass, fp_bypass, fpTagBypass;
00119 selection_logic instruction_selection;
00120 dep_resource_conflict_check idcl,fdcl;
00121 full_decoder inst_decoder;
00122 core_pipeline corepipe;
00123 MCclock_network clockNetwork;
00124
00125 UndifferentiatedCore undifferentiatedCore;
00126 powerDef tot_power, max_power;
00127
00128 double maxIEXEpower, maxFPUPower, runtimeDynamicIEXEpower, runtimeDynamicFPUPower;
00129 double area, maxPower, runtimeDynamicPower, totalLeakage, totalPower;
00130 double scktRatio, clockRate,executionTime;
00131 AreaPower coreTot,total, ifu, lsu, mmu, exu, fpu, ooou, bypass, rfu;
00132
00133 virtual void initialize(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_);
00134 virtual void computeMaxPower();
00135 virtual void computeRuntimePower(int ithCore_);
00136
00137
00138
00139 cache_processor SSTreturnICACHE(void){ return icache; };
00140 cache_processor SSTreturnDCACHE(void){ return dcache; };
00141 tlb_core SSTreturnITLB(void){ return itlb; };
00142 tlb_core SSTreturnDTLB(void){ return dtlb; };
00143 RF_core SSTreturnIRF(void){ return IRF; };
00144 RF_core SSTreturnFRF(void){ return FRF; };
00145 RF_core SSTreturnRFWIN(void){ return RFWIN; };
00146 IB_core SSTreturnIB(void){ return IB; };
00147 RS_core SSTreturnIRS(void){ return iRS; };
00148 full_decoder SSTreturnDECODER(void){ return inst_decoder; };
00149 core_pipeline SSTreturnPIPELINE(void){ return corepipe; };
00150 resultbus SSTreturnINTBYPASS(void){ return int_bypass; };
00151 resultbus SSTreturnINTTAGBYPASS(void){ return intTagBypass; };
00152 resultbus SSTreturnFPBYPASS(void){ return fp_bypass; };
00153 selection_logic SSTreturnINSTSELEC(void){ return instruction_selection; };
00154 dep_resource_conflict_check SSTreturnIDCL(void){ return idcl; };
00155 dep_resource_conflict_check SSTreturnFDCL(void){ return fdcl; };
00156 MCclock_network SSTreturnCLOCK(void){ return clockNetwork; };
00157 UndifferentiatedCore SSTreturnUNCORE(void){ return undifferentiatedCore; };
00158 LSQ_core SSTreturnLSQ(void){ return LSQ; };
00159 };
00160
00161 class OOOCore :public processor_core {
00162 public:
00163 ROB_core ROB;
00164 LSQ_core loadQ;
00165 predictor_core predictor;
00166 RAT_core RAT, iRRAT,iFRAT,iFRATCG, fRRAT,fFRAT,fFRATCG;
00167
00168 ParseXML *XML;
00169 InputParameter interface_ip;
00170 int ithCore;
00171 bool inorder, reservationStationBased, renamingCAM, regWindowing;
00172 int globalCheckpoint, instructionLength;
00173 tlb_core itlb, dtlb;
00174 cache_processor icache, dcache;
00175 BTB_core BTB;
00176 RF_core IRF, FRF, RFWIN, phyIRF, phyFRF;
00177 IB_core IB;
00178 RS_core iRS, iISQ,fRS, fISQ;
00179 LSQ_core LSQ;
00180
00181
00182 resultbus int_bypass,intTagBypass, fp_bypass, fpTagBypass;
00183 selection_logic instruction_selection;
00184 dep_resource_conflict_check idcl,fdcl;
00185 full_decoder inst_decoder;
00186 core_pipeline corepipe;
00187 MCclock_network clockNetwork;
00188
00189 UndifferentiatedCore undifferentiatedCore;
00190 powerDef tot_power, max_power;
00191 double bypassPower;
00192 double maxIEXEpower, maxFPUPower, runtimeDynamicIEXEpower, runtimeDynamicFPUPower;
00193 double area, maxPower, runtimeDynamicPower, totalLeakage, totalPower;
00194 double scktRatio, clockRate, executionTime;
00195 AreaPower coreTot, ifu, lsu, mmu, exu, fpu, ooou, renamingu, scheduleru, rfu, branchPredictor,bypass;
00196
00197 OOOCore();
00198 ~OOOCore();
00199 virtual void initialize(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_);
00200 virtual void computeMaxPower();
00201 virtual void computeRuntimePower(int ithCore_);
00202
00203
00204
00205 cache_processor SSTreturnICACHE(void){ return icache; };
00206 cache_processor SSTreturnDCACHE(void){ return dcache; };
00207 tlb_core SSTreturnITLB(void){ return itlb; };
00208 tlb_core SSTreturnDTLB(void){ return dtlb; };
00209 RF_core SSTreturnIRF(void){ return IRF; };
00210 RF_core SSTreturnFRF(void){ return FRF; };
00211 RF_core SSTreturnRFWIN(void){ return RFWIN; };
00212 IB_core SSTreturnIB(void){ return IB; };
00213 RS_core SSTreturnIRS(void){ return iRS; };
00214 full_decoder SSTreturnDECODER(void){ return inst_decoder; };
00215 core_pipeline SSTreturnPIPELINE(void){ return corepipe; };
00216 resultbus SSTreturnINTBYPASS(void){ return int_bypass; };
00217 resultbus SSTreturnINTTAGBYPASS(void){ return intTagBypass; };
00218 resultbus SSTreturnFPBYPASS(void){ return fp_bypass; };
00219 selection_logic SSTreturnINSTSELEC(void){ return instruction_selection; };
00220 dep_resource_conflict_check SSTreturnIDCL(void){ return idcl; };
00221 dep_resource_conflict_check SSTreturnFDCL(void){ return fdcl; };
00222 MCclock_network SSTreturnCLOCK(void){ return clockNetwork; };
00223 UndifferentiatedCore SSTreturnUNCORE(void){ return undifferentiatedCore; };
00224 LSQ_core SSTreturnLSQ(void){ return LSQ; };
00225 LSQ_core SSTreturnLOADQ(void){ return loadQ; };
00226 ROB_core SSTreturnROB(void){ return ROB; };
00227 predictor_core SSTreturnPREDICTOR(void){ return predictor; };
00228 BTB_core SSTreturnBTB(void){ return BTB; };
00229 RS_core SSTreturnIISQ(void){ return iISQ; };
00230 RS_core SSTreturnFISQ(void){ return fISQ; };
00231 RF_core SSTreturnPHYIRF(void){ return phyIRF; };
00232 RF_core SSTreturnPHYFRF(void){ return phyFRF; };
00233 resultbus SSTreturnFPTAGBYPASS(void){ return fpTagBypass; };
00234 RAT_core SSTreturnIRRAT(void){ return iRRAT; };
00235 RAT_core SSTreturnFRRAT(void){ return fRRAT; };
00236 RAT_core SSTreturnIFRAT(void){ return iFRAT; };
00237 RAT_core SSTreturnFFRAT(void){ return fFRAT; };
00238 RAT_core SSTreturnIFRATCG(void){ return iFRATCG; };
00239 RAT_core SSTreturnFFRATCG(void){ return fFRATCG; };
00240
00241
00242 };
00243
00244
00245 #endif