00001 #if !defined (__MIPS_CPU_H__)
00002 #define __MIPS_CPU_H__
00003
00004 #define TARGET_HAS_ICE 1
00005
00006 #define ELF_MACHINE EM_MIPS
00007
00008 #include "config.h"
00009 #include "mips-defs.h"
00010 #include "cpu-defs.h"
00011 #include "softfloat.h"
00012
00013
00014
00015 #if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
00016 typedef unsigned char uint_fast8_t;
00017 typedef unsigned int uint_fast16_t;
00018 #endif
00019
00020 struct CPUMIPSState;
00021
00022 typedef struct r4k_tlb_t r4k_tlb_t;
00023 struct r4k_tlb_t {
00024 target_ulong VPN;
00025 uint32_t PageMask;
00026 uint_fast8_t ASID;
00027 uint_fast16_t G:1;
00028 uint_fast16_t C0:3;
00029 uint_fast16_t C1:3;
00030 uint_fast16_t V0:1;
00031 uint_fast16_t V1:1;
00032 uint_fast16_t D0:1;
00033 uint_fast16_t D1:1;
00034 target_ulong PFN[2];
00035 };
00036
00037 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
00038 struct CPUMIPSTLBContext {
00039 uint32_t nb_tlb;
00040 uint32_t tlb_in_use;
00041 int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
00042 void (*do_tlbwi) (void);
00043 void (*do_tlbwr) (void);
00044 void (*do_tlbp) (void);
00045 void (*do_tlbr) (void);
00046 union {
00047 struct {
00048 r4k_tlb_t tlb[MIPS_TLB_MAX];
00049 } r4k;
00050 } mmu;
00051 };
00052
00053 typedef union fpr_t fpr_t;
00054 union fpr_t {
00055 float64 fd;
00056 float32 fs[2];
00057 uint64_t d;
00058 uint32_t w[2];
00059 };
00060
00061
00062
00063 #if defined(WORDS_BIGENDIAN)
00064 # define FP_ENDIAN_IDX 1
00065 #else
00066 # define FP_ENDIAN_IDX 0
00067 #endif
00068
00069 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
00070 struct CPUMIPSFPUContext {
00071
00072 fpr_t fpr[32];
00073 float_status fp_status;
00074
00075 uint32_t fcr0;
00076 #define FCR0_F64 22
00077 #define FCR0_L 21
00078 #define FCR0_W 20
00079 #define FCR0_3D 19
00080 #define FCR0_PS 18
00081 #define FCR0_D 17
00082 #define FCR0_S 16
00083 #define FCR0_PRID 8
00084 #define FCR0_REV 0
00085
00086 uint32_t fcr31;
00087 #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
00088 #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
00089 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
00090 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
00091 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
00092 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
00093 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
00094 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
00095 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
00096 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
00097 #define FP_INEXACT 1
00098 #define FP_UNDERFLOW 2
00099 #define FP_OVERFLOW 4
00100 #define FP_DIV0 8
00101 #define FP_INVALID 16
00102 #define FP_UNIMPLEMENTED 32
00103 };
00104
00105 #define NB_MMU_MODES 3
00106
00107 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
00108 struct CPUMIPSMVPContext {
00109 int32_t CP0_MVPControl;
00110 #define CP0MVPCo_CPA 3
00111 #define CP0MVPCo_STLB 2
00112 #define CP0MVPCo_VPC 1
00113 #define CP0MVPCo_EVP 0
00114 int32_t CP0_MVPConf0;
00115 #define CP0MVPC0_M 31
00116 #define CP0MVPC0_TLBS 29
00117 #define CP0MVPC0_GS 28
00118 #define CP0MVPC0_PCP 27
00119 #define CP0MVPC0_PTLBE 16
00120 #define CP0MVPC0_TCA 15
00121 #define CP0MVPC0_PVPE 10
00122 #define CP0MVPC0_PTC 0
00123 int32_t CP0_MVPConf1;
00124 #define CP0MVPC1_CIM 31
00125 #define CP0MVPC1_CIF 30
00126 #define CP0MVPC1_PCX 20
00127 #define CP0MVPC1_PCP2 10
00128 #define CP0MVPC1_PCP1 0
00129 };
00130
00131 typedef struct mips_def_t mips_def_t;
00132
00133 #define MIPS_SHADOW_SET_MAX 16
00134 #define MIPS_TC_MAX 5
00135 #define MIPS_FPU_MAX 1
00136 #define MIPS_DSP_ACC 4
00137
00138 typedef struct TCState TCState;
00139 struct TCState {
00140 target_ulong gpr[32];
00141 target_ulong PC;
00142 target_ulong HI[MIPS_DSP_ACC];
00143 target_ulong LO[MIPS_DSP_ACC];
00144 target_ulong ACX[MIPS_DSP_ACC];
00145 target_ulong DSPControl;
00146 int32_t CP0_TCStatus;
00147 #define CP0TCSt_TCU3 31
00148 #define CP0TCSt_TCU2 30
00149 #define CP0TCSt_TCU1 29
00150 #define CP0TCSt_TCU0 28
00151 #define CP0TCSt_TMX 27
00152 #define CP0TCSt_RNST 23
00153 #define CP0TCSt_TDS 21
00154 #define CP0TCSt_DT 20
00155 #define CP0TCSt_DA 15
00156 #define CP0TCSt_A 13
00157 #define CP0TCSt_TKSU 11
00158 #define CP0TCSt_IXMT 10
00159 #define CP0TCSt_TASID 0
00160 int32_t CP0_TCBind;
00161 #define CP0TCBd_CurTC 21
00162 #define CP0TCBd_TBE 17
00163 #define CP0TCBd_CurVPE 0
00164 target_ulong CP0_TCHalt;
00165 target_ulong CP0_TCContext;
00166 target_ulong CP0_TCSchedule;
00167 target_ulong CP0_TCScheFBack;
00168 int32_t CP0_Debug_tcstatus;
00169 };
00170
00171 typedef struct CPUMIPSState CPUMIPSState;
00172 struct CPUMIPSState {
00173 TCState active_tc;
00174 CPUMIPSFPUContext active_fpu;
00175
00176 CPUMIPSMVPContext *mvp;
00177 CPUMIPSTLBContext *tlb;
00178 uint32_t current_tc;
00179 uint32_t current_fpu;
00180
00181 uint32_t SEGBITS;
00182 uint32_t PABITS;
00183 target_ulong SEGMask;
00184 target_ulong PAMask;
00185
00186 int32_t CP0_Index;
00187
00188 int32_t CP0_Random;
00189 int32_t CP0_VPEControl;
00190 #define CP0VPECo_YSI 21
00191 #define CP0VPECo_GSI 20
00192 #define CP0VPECo_EXCPT 16
00193 #define CP0VPECo_TE 15
00194 #define CP0VPECo_TargTC 0
00195 int32_t CP0_VPEConf0;
00196 #define CP0VPEC0_M 31
00197 #define CP0VPEC0_XTC 21
00198 #define CP0VPEC0_TCS 19
00199 #define CP0VPEC0_SCS 18
00200 #define CP0VPEC0_DSC 17
00201 #define CP0VPEC0_ICS 16
00202 #define CP0VPEC0_MVP 1
00203 #define CP0VPEC0_VPA 0
00204 int32_t CP0_VPEConf1;
00205 #define CP0VPEC1_NCX 20
00206 #define CP0VPEC1_NCP2 10
00207 #define CP0VPEC1_NCP1 0
00208 target_ulong CP0_YQMask;
00209 target_ulong CP0_VPESchedule;
00210 target_ulong CP0_VPEScheFBack;
00211 int32_t CP0_VPEOpt;
00212 #define CP0VPEOpt_IWX7 15
00213 #define CP0VPEOpt_IWX6 14
00214 #define CP0VPEOpt_IWX5 13
00215 #define CP0VPEOpt_IWX4 12
00216 #define CP0VPEOpt_IWX3 11
00217 #define CP0VPEOpt_IWX2 10
00218 #define CP0VPEOpt_IWX1 9
00219 #define CP0VPEOpt_IWX0 8
00220 #define CP0VPEOpt_DWX7 7
00221 #define CP0VPEOpt_DWX6 6
00222 #define CP0VPEOpt_DWX5 5
00223 #define CP0VPEOpt_DWX4 4
00224 #define CP0VPEOpt_DWX3 3
00225 #define CP0VPEOpt_DWX2 2
00226 #define CP0VPEOpt_DWX1 1
00227 #define CP0VPEOpt_DWX0 0
00228 target_ulong CP0_EntryLo0;
00229 target_ulong CP0_EntryLo1;
00230 target_ulong CP0_Context;
00231 int32_t CP0_PageMask;
00232 int32_t CP0_PageGrain;
00233 int32_t CP0_Wired;
00234 int32_t CP0_SRSConf0_rw_bitmask;
00235 int32_t CP0_SRSConf0;
00236 #define CP0SRSC0_M 31
00237 #define CP0SRSC0_SRS3 20
00238 #define CP0SRSC0_SRS2 10
00239 #define CP0SRSC0_SRS1 0
00240 int32_t CP0_SRSConf1_rw_bitmask;
00241 int32_t CP0_SRSConf1;
00242 #define CP0SRSC1_M 31
00243 #define CP0SRSC1_SRS6 20
00244 #define CP0SRSC1_SRS5 10
00245 #define CP0SRSC1_SRS4 0
00246 int32_t CP0_SRSConf2_rw_bitmask;
00247 int32_t CP0_SRSConf2;
00248 #define CP0SRSC2_M 31
00249 #define CP0SRSC2_SRS9 20
00250 #define CP0SRSC2_SRS8 10
00251 #define CP0SRSC2_SRS7 0
00252 int32_t CP0_SRSConf3_rw_bitmask;
00253 int32_t CP0_SRSConf3;
00254 #define CP0SRSC3_M 31
00255 #define CP0SRSC3_SRS12 20
00256 #define CP0SRSC3_SRS11 10
00257 #define CP0SRSC3_SRS10 0
00258 int32_t CP0_SRSConf4_rw_bitmask;
00259 int32_t CP0_SRSConf4;
00260 #define CP0SRSC4_SRS15 20
00261 #define CP0SRSC4_SRS14 10
00262 #define CP0SRSC4_SRS13 0
00263 int32_t CP0_HWREna;
00264 target_ulong CP0_BadVAddr;
00265 int32_t CP0_Count;
00266 target_ulong CP0_EntryHi;
00267 int32_t CP0_Compare;
00268 int32_t CP0_Status;
00269 #define CP0St_CU3 31
00270 #define CP0St_CU2 30
00271 #define CP0St_CU1 29
00272 #define CP0St_CU0 28
00273 #define CP0St_RP 27
00274 #define CP0St_FR 26
00275 #define CP0St_RE 25
00276 #define CP0St_MX 24
00277 #define CP0St_PX 23
00278 #define CP0St_BEV 22
00279 #define CP0St_TS 21
00280 #define CP0St_SR 20
00281 #define CP0St_NMI 19
00282 #define CP0St_IM 8
00283 #define CP0St_KX 7
00284 #define CP0St_SX 6
00285 #define CP0St_UX 5
00286 #define CP0St_KSU 3
00287 #define CP0St_ERL 2
00288 #define CP0St_EXL 1
00289 #define CP0St_IE 0
00290 int32_t CP0_IntCtl;
00291 #define CP0IntCtl_IPTI 29
00292 #define CP0IntCtl_IPPC1 26
00293 #define CP0IntCtl_VS 5
00294 int32_t CP0_SRSCtl;
00295 #define CP0SRSCtl_HSS 26
00296 #define CP0SRSCtl_EICSS 18
00297 #define CP0SRSCtl_ESS 12
00298 #define CP0SRSCtl_PSS 6
00299 #define CP0SRSCtl_CSS 0
00300 int32_t CP0_SRSMap;
00301 #define CP0SRSMap_SSV7 28
00302 #define CP0SRSMap_SSV6 24
00303 #define CP0SRSMap_SSV5 20
00304 #define CP0SRSMap_SSV4 16
00305 #define CP0SRSMap_SSV3 12
00306 #define CP0SRSMap_SSV2 8
00307 #define CP0SRSMap_SSV1 4
00308 #define CP0SRSMap_SSV0 0
00309 int32_t CP0_Cause;
00310 #define CP0Ca_BD 31
00311 #define CP0Ca_TI 30
00312 #define CP0Ca_CE 28
00313 #define CP0Ca_DC 27
00314 #define CP0Ca_PCI 26
00315 #define CP0Ca_IV 23
00316 #define CP0Ca_WP 22
00317 #define CP0Ca_IP 8
00318 #define CP0Ca_IP_mask 0x0000FF00
00319 #define CP0Ca_EC 2
00320 target_ulong CP0_EPC;
00321 int32_t CP0_PRid;
00322 int32_t CP0_EBase;
00323 int32_t CP0_Config0;
00324 #define CP0C0_M 31
00325 #define CP0C0_K23 28
00326 #define CP0C0_KU 25
00327 #define CP0C0_MDU 20
00328 #define CP0C0_MM 17
00329 #define CP0C0_BM 16
00330 #define CP0C0_BE 15
00331 #define CP0C0_AT 13
00332 #define CP0C0_AR 10
00333 #define CP0C0_MT 7
00334 #define CP0C0_VI 3
00335 #define CP0C0_K0 0
00336 int32_t CP0_Config1;
00337 #define CP0C1_M 31
00338 #define CP0C1_MMU 25
00339 #define CP0C1_IS 22
00340 #define CP0C1_IL 19
00341 #define CP0C1_IA 16
00342 #define CP0C1_DS 13
00343 #define CP0C1_DL 10
00344 #define CP0C1_DA 7
00345 #define CP0C1_C2 6
00346 #define CP0C1_MD 5
00347 #define CP0C1_PC 4
00348 #define CP0C1_WR 3
00349 #define CP0C1_CA 2
00350 #define CP0C1_EP 1
00351 #define CP0C1_FP 0
00352 int32_t CP0_Config2;
00353 #define CP0C2_M 31
00354 #define CP0C2_TU 28
00355 #define CP0C2_TS 24
00356 #define CP0C2_TL 20
00357 #define CP0C2_TA 16
00358 #define CP0C2_SU 12
00359 #define CP0C2_SS 8
00360 #define CP0C2_SL 4
00361 #define CP0C2_SA 0
00362 int32_t CP0_Config3;
00363 #define CP0C3_M 31
00364 #define CP0C3_DSPP 10
00365 #define CP0C3_LPA 7
00366 #define CP0C3_VEIC 6
00367 #define CP0C3_VInt 5
00368 #define CP0C3_SP 4
00369 #define CP0C3_MT 2
00370 #define CP0C3_SM 1
00371 #define CP0C3_TL 0
00372 int32_t CP0_Config6;
00373 int32_t CP0_Config7;
00374
00375 target_ulong CP0_LLAddr;
00376 target_ulong CP0_WatchLo[8];
00377 int32_t CP0_WatchHi[8];
00378 target_ulong CP0_XContext;
00379 int32_t CP0_Framemask;
00380 int32_t CP0_Debug;
00381 #define CP0DB_DBD 31
00382 #define CP0DB_DM 30
00383 #define CP0DB_LSNM 28
00384 #define CP0DB_Doze 27
00385 #define CP0DB_Halt 26
00386 #define CP0DB_CNT 25
00387 #define CP0DB_IBEP 24
00388 #define CP0DB_DBEP 21
00389 #define CP0DB_IEXI 20
00390 #define CP0DB_VER 15
00391 #define CP0DB_DEC 10
00392 #define CP0DB_SSt 8
00393 #define CP0DB_DINT 5
00394 #define CP0DB_DIB 4
00395 #define CP0DB_DDBS 3
00396 #define CP0DB_DDBL 2
00397 #define CP0DB_DBp 1
00398 #define CP0DB_DSS 0
00399 target_ulong CP0_DEPC;
00400 int32_t CP0_Performance0;
00401 int32_t CP0_TagLo;
00402 int32_t CP0_DataLo;
00403 int32_t CP0_TagHi;
00404 int32_t CP0_DataHi;
00405 target_ulong CP0_ErrorEPC;
00406 int32_t CP0_DESAVE;
00407
00408 TCState tcs[MIPS_SHADOW_SET_MAX];
00409 CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
00410
00411 int error_code;
00412 uint32_t hflags;
00413
00414 #define MIPS_HFLAG_TMASK 0x03FF
00415 #define MIPS_HFLAG_MODE 0x0007
00416
00417
00418
00419 #define MIPS_HFLAG_KSU 0x0003
00420 #define MIPS_HFLAG_UM 0x0002
00421 #define MIPS_HFLAG_SM 0x0001
00422 #define MIPS_HFLAG_KM 0x0000
00423 #define MIPS_HFLAG_DM 0x0004
00424 #define MIPS_HFLAG_64 0x0008
00425 #define MIPS_HFLAG_CP0 0x0010
00426 #define MIPS_HFLAG_FPU 0x0020
00427 #define MIPS_HFLAG_F64 0x0040
00428
00429
00430
00431 #define MIPS_HFLAG_COP1X 0x0080
00432 #define MIPS_HFLAG_RE 0x0100
00433 #define MIPS_HFLAG_UX 0x0200
00434
00435
00436
00437
00438 #define MIPS_HFLAG_BMASK 0x1C00
00439 #define MIPS_HFLAG_B 0x0400
00440 #define MIPS_HFLAG_BC 0x0800
00441 #define MIPS_HFLAG_BL 0x0C00
00442 #define MIPS_HFLAG_BR 0x1000
00443 target_ulong btarget;
00444 int bcond;
00445
00446 int SYNCI_Step;
00447 int CCRes;
00448 uint32_t CP0_Status_rw_bitmask;
00449 uint32_t CP0_TCStatus_rw_bitmask;
00450 int insn_flags;
00451
00452 target_ulong tls_value;
00453
00454 CPU_COMMON
00455
00456 const mips_def_t *cpu_model;
00457 void *irq[8];
00458 struct QEMUTimer *timer;
00459 };
00460
00461 int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
00462 target_ulong address, int rw, int access_type);
00463 int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
00464 target_ulong address, int rw, int access_type);
00465 int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
00466 target_ulong address, int rw, int access_type);
00467 void r4k_do_tlbwi (void);
00468 void r4k_do_tlbwr (void);
00469 void r4k_do_tlbp (void);
00470 void r4k_do_tlbr (void);
00471 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
00472
00473 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
00474 int unused, int size);
00475
00476 #define CPUState CPUMIPSState
00477 #define cpu_init cpu_mips_init
00478 #define cpu_exec cpu_mips_exec
00479 #define cpu_gen_code cpu_mips_gen_code
00480 #define cpu_signal_handler cpu_mips_signal_handler
00481 #define cpu_list mips_cpu_list
00482
00483 #define CPU_SAVE_VERSION 3
00484
00485
00486
00487 #define MMU_MODE0_SUFFIX _kernel
00488 #define MMU_MODE1_SUFFIX _super
00489 #define MMU_MODE2_SUFFIX _user
00490 #define MMU_USER_IDX 2
00491 static inline int cpu_mmu_index (CPUState *env)
00492 {
00493 return env->hflags & MIPS_HFLAG_KSU;
00494 }
00495
00496 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
00497 {
00498 if (newsp)
00499 env->active_tc.gpr[29] = newsp;
00500 env->active_tc.gpr[7] = 0;
00501 env->active_tc.gpr[2] = 0;
00502 }
00503
00504 #include "cpu-all.h"
00505 #include "exec-all.h"
00506
00507
00508
00509
00510 enum {
00511
00512 ACCESS_USER = 0x00,
00513 ACCESS_SUPER = 0x01,
00514
00515 ACCESS_STORE = 0x02,
00516
00517 ACCESS_CODE = 0x10,
00518 ACCESS_INT = 0x20,
00519 ACCESS_FLOAT = 0x30,
00520 };
00521
00522
00523 enum {
00524 EXCP_NONE = -1,
00525 EXCP_RESET = 0,
00526 EXCP_SRESET,
00527 EXCP_DSS,
00528 EXCP_DINT,
00529 EXCP_DDBL,
00530 EXCP_DDBS,
00531 EXCP_NMI,
00532 EXCP_MCHECK,
00533 EXCP_EXT_INTERRUPT,
00534 EXCP_DFWATCH,
00535 EXCP_DIB,
00536 EXCP_IWATCH,
00537 EXCP_AdEL,
00538 EXCP_AdES,
00539 EXCP_TLBF,
00540 EXCP_IBE,
00541 EXCP_DBp,
00542 EXCP_SYSCALL,
00543 EXCP_BREAK,
00544 EXCP_CpU,
00545 EXCP_RI,
00546 EXCP_OVERFLOW,
00547 EXCP_TRAP,
00548 EXCP_FPE,
00549 EXCP_DWATCH,
00550 EXCP_LTLBL,
00551 EXCP_TLBL,
00552 EXCP_TLBS,
00553 EXCP_DBE,
00554 EXCP_THREAD,
00555 EXCP_MDMX,
00556 EXCP_C2E,
00557 EXCP_CACHE,
00558
00559 EXCP_LAST = EXCP_CACHE,
00560 };
00561
00562 int cpu_mips_exec(CPUMIPSState *s);
00563 CPUMIPSState *cpu_mips_init(const char *cpu_model);
00564
00565 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
00566
00567
00568 uint32_t cpu_mips_get_random (CPUState *env);
00569 uint32_t cpu_mips_get_count (CPUState *env);
00570 void cpu_mips_store_count (CPUState *env, uint32_t value);
00571 void cpu_mips_store_compare (CPUState *env, uint32_t value);
00572 void cpu_mips_start_count(CPUState *env);
00573 void cpu_mips_stop_count(CPUState *env);
00574
00575
00576 void cpu_mips_update_irq (CPUState *env);
00577
00578
00579 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
00580 int mmu_idx, int is_softmmu);
00581 void do_interrupt (CPUState *env);
00582 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
00583
00584 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
00585 {
00586 env->active_tc.PC = tb->pc;
00587 env->hflags &= ~MIPS_HFLAG_BMASK;
00588 env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
00589 }
00590
00591 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
00592 target_ulong *cs_base, int *flags)
00593 {
00594 *pc = env->active_tc.PC;
00595 *cs_base = 0;
00596 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
00597 }
00598
00599 #endif