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sst/elements/genericProc/ssBackEnd/sharedMemory.h

00001 // Copyright 2007 Sandia Corporation. Under the terms
00002 // of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
00003 // Government retains certain rights in this software.
00004 // 
00005 // Copyright (c) 2007, Sandia Corporation
00006 // All rights reserved.
00007 // 
00008 // This file is part of the SST software package. For license
00009 // information, see the LICENSE file in the top level directory of the
00010 // distribution.
00011 
00012 
00013 #ifndef SHAREDMEMORY_H
00014 #define SHAREDMEMORY_H
00015 
00016 #include "memory.h"
00017 #include <vector>
00018 
00019 //: Interface for shared memory processors
00020 // 
00021 // Allows the processor to react to bus transactions. The shared mem
00022 // proc is responsible for registering itself with a shared memory
00023 // object.
00024 //
00025 //!SEC:shmem
00026 class sharedMemProc {
00027 public:
00028   virtual ~sharedMemProc() {;}
00029   virtual void busReadMiss(simAddress)=0;
00030   virtual void busWriteMiss(simAddress)=0;
00031   virtual void busWriteHit(simAddress)=0;
00032 };
00033 
00034 //: A shared memory
00035 //
00036 // Implements the simple cache coherence protocol in Hennessy and Patterson.
00037 //
00038 //!NOTE: Assumes all bus transactions are atomic. 
00039 //!SEC:shmem
00040 class sharedMemory : public memory_interface {
00041   base_memory *myMem;
00042   //:Registered Processors
00043   vector<sharedMemProc*> procs;
00044 public:
00045   //: Bus Message types
00046   typedef enum {READ_MISS, WRITE_MISS, WRITE_HIT} msgType;
00047   //: Register a new processor
00048   void registerProcessor(sharedMemProc* p) {procs.push_back(p);}
00049   //: add in contention on the bus (if any)
00050   virtual void registerPost() = 0;
00051   // Post a message to the bus
00052   int postMessage(msgType t, simAddress addr, sharedMemProc* poster) {
00053     int nP = procs.size();
00054     for(int i=0; i < nP; ++i) {
00055       sharedMemProc* targP = procs[i];
00056       if (targP != poster) {
00057         switch(t) {
00058         case READ_MISS:
00059           targP->busReadMiss(addr); break;
00060         case WRITE_MISS:
00061           targP->busWriteMiss(addr); break;
00062         case WRITE_HIT:
00063           targP->busWriteHit(addr); break;
00064         default:
00065           printf("unknown bus message tyoe %d\n", t);
00066         }
00067       }
00068     }
00069     registerPost();
00070     return 0;
00071   }
00072 
00073 #define MEM_FUNC_GEN(S)                                                 \
00074   virtual uint##S ReadMemory##S(const simAddress sa, const bool s) {    \
00075     return myMem->ReadMemory##S(sa, s);                                 \
00076   }                                                                     \
00077   virtual bool WriteMemory##S(const simAddress sa, const uint##S d, const bool s) { \
00078     return myMem->WriteMemory##S(sa, d, s);                             \
00079   }
00080 
00081   MEM_FUNC_GEN(8)
00082   MEM_FUNC_GEN(16)
00083   MEM_FUNC_GEN(32)
00084 
00085   virtual uint8 getFE(const simAddress sa) {return myMem->getFE(sa);}
00086   virtual void setFE(const simAddress sa, const uint8 FEValue) {
00087     myMem->setFE(sa, FEValue);
00088   }
00089   virtual void squashSpec() {myMem->squashSpec();}
00090 
00091 
00092   base_memory *getBaseMem() {return myMem;}
00093 
00094   sharedMemory(string cfgstr) {myMem = new base_memory(cfgstr);}
00095   ~sharedMemory() {
00096     delete myMem;
00097   }
00098   virtual void setup()=0;
00099   virtual void finish()=0;
00100   virtual void handleParcel(parcel *p)=0;
00101   virtual void preTic()=0;
00102   virtual void postTic()=0;
00103 };
00104 
00105 
00106 #endif

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