00001 #ifndef _SST_POWER_H
00002 #define _SST_POWER_H
00003
00004 #include <stdlib.h>
00005 #include <stdio.h>
00006 #include <unistd.h>
00007 #include <math.h>
00008 #include <string>
00009 #include <map>
00010 #include <sst/core/component.h>
00011 #include <sst/core/debug.h>
00012 #include <sst/core/sst.h>
00013 #include <sst/core/boost.h>
00014
00015
00016
00017
00018
00019
00020
00021
00022 extern "C"{
00023 #ifdef PANALYZER_H
00024
00025 #ifdef LV1_PANALYZER_H
00026 #include "../sst/core/techModels/libsim-panalyzer/lv1_opts.h"
00027 #include "../sst/core/techModels/libsim-panalyzer/lv1_panalyzer.h"
00028 #include "../sst/core/techModels/libsim-panalyzer/lv1_cache_panalyzer.h"
00029 #include "../sst/core/techModels/libsim-panalyzer/io_panalyzer.h"
00030 #endif
00031
00032 #ifdef LV2_PANALYZER_H
00033 #include "../sst/core/techModels/libsim-panalyzer/technology.h"
00034 #include "../sst/core/techModels/libsim-panalyzer/alu_panalyzer.h"
00035 #include "../sst/core/techModels/libsim-panalyzer/mult_panalyzer.h"
00036 #include "../sst/core/techModels/libsim-panalyzer/fpu_panalyzer.h"
00037 #include "../sst/core/techModels/libsim-panalyzer/uarch_panalyzer.h"
00038 #endif //lv2_panalyzer_h
00039
00040 #endif //panalyzer_h
00041 }
00042
00043
00044
00045
00046
00047
00048 #ifdef McPAT05_H
00049 #include "../sst/core/techModels/libMcPAT/io.h"
00050 #include "../sst/core/techModels/libMcPAT/logic.h"
00051 #include "../sst/core/techModels/libMcPAT/full_decoder.h"
00052 #include "../sst/core/techModels/libMcPAT/crossbarswitch.h"
00053 #include "../sst/core/techModels/libMcPAT/basic_circuit.h"
00054 #include "../sst/core/techModels/libMcPAT/processor.h"
00055 #endif //mcpat05_h
00056
00057
00058
00059 #define McPAT06_H
00060
00061
00062 #ifdef McPAT06_H
00063 #include "../sst/core/techModels/libMcPATbeta/io.h"
00064 #include "../sst/core/techModels/libMcPATbeta/logic.h"
00065
00066
00067 #include "../sst/core/techModels/libMcPATbeta/basic_circuit.h"
00068 #include "../sst/core/techModels/libMcPATbeta/processor.h"
00069 #endif //mcpat06_h
00070
00071
00072 namespace SST {
00073
00074 typedef int nm;
00075 typedef int ns;
00076
00077 enum logic_style {STATIC, DYNAMIC};
00078 enum clock_style{NORM_H, BALANCED_H};
00079 enum io_style{IN, OUT, BI};
00080 enum topology_style{TWODMESH, RING, CROSSBAR};
00081
00082
00083 enum ptype {CACHE_IL1, CACHE_IL2, CACHE_DL1, CACHE_DL2, CACHE_ITLB, CACHE_DTLB, CLOCK, BPRED, RF, IO, LOGIC, EXEU_ALU, EXEU_FPU, MULT, IB, ISSUE_Q, INST_DECODER, BYPASS, EXEU, PIPELINE, LSQ, RAT, ROB, BTB, CACHE_L2, MEM_CTRL, ROUTER, LOAD_Q, RENAME_U, SCHEDULER_U, CACHE_L3, CACHE_L1DIR, CACHE_L2DIR, UARCH};
00084 enum pmodel{McPAT, SimPanalyzer, McPAT05, MySimpleModel};
00085
00086
00087
00088
00089 typedef struct
00090 {
00091 watts il1_read, il1_write;
00092 watts il2_read, il2_write;
00093 watts dl1_read, dl1_write;
00094 watts dl2_read, dl2_write;
00095 watts itlb_read, itlb_write;
00096 watts dtlb_read, dtlb_write;
00097 watts aio, dio;
00098 watts clock;
00099 watts logic;
00100 watts rf, bpred;
00101 watts alu, fpu, mult, exeu, lsq;
00102 watts uarch;
00103 }Punit_t;
00104
00105 typedef struct
00106 {
00107 unsigned core_physical_address_width, core_temperature, core_tech_node;
00108 unsigned core_virtual_address_width, core_virtual_memory_page_size, core_number_hardware_threads;
00109 unsigned machine_bits, archi_Regs_IRF_size, archi_Regs_FRF_size, core_phy_Regs_IRF_size, core_phy_Regs_FRF_size;
00110 unsigned core_register_windows_size, core_opcode_width;
00111 unsigned core_instruction_window_size;
00112 unsigned core_issue_width, core_decode_width, core_fetch_width, core_commit_width;
00113 unsigned core_instruction_length;
00114 unsigned core_instruction_buffer_size;
00115 unsigned ALU_per_core, FPU_per_core;
00116 unsigned core_store_buffer_size, core_memory_ports;
00117 unsigned core_int_pipeline_depth, core_RAS_size, core_ROB_size, core_load_buffer_size, core_number_of_NoCs;
00118 unsigned core_number_instruction_fetch_ports, core_fp_issue_width, core_fp_instruction_window_size;
00119 } core_params_t;
00120
00121 typedef struct
00122 {
00123 farads unit_scap;
00124 farads unit_icap;
00125 farads unit_lcap;
00126 farads unit_ecap;
00127 volts vss;
00128 double op_freq;
00129 unsigned core_physical_address_width;
00130 unsigned core_virtual_address_width, core_virtual_memory_page_size, core_number_hardware_threads;
00131 unsigned core_temperature, core_tech_node;
00132
00133
00134 int num_sets;
00135 int line_size;
00136 int num_bitlines;
00137 int num_wordlines;
00138 int assoc;
00139 unsigned num_rwports, num_rports, num_wports, num_banks;
00140 double throughput, latency;
00141 unsigned miss_buf_size, fill_buf_size, prefetch_buf_size, wbb_buf_size;
00142 unsigned number_entries;
00143 unsigned device_type, directory_type;
00144 } cache_params_t;
00145
00146
00147
00148 struct clock_params_t
00149 {
00150 farads unit_scap;
00151 farads unit_icap;
00152 farads unit_lcap;
00153 farads unit_ecap;
00154 volts vss;
00155 double op_freq;
00156 unsigned core_temperature, core_tech_node;
00157
00158
00159 clock_style clk_style;
00160 double skew;
00161 nm chip_area;
00162 farads node_cap;
00163 int opt_clock_buffer_num;
00164 };
00165
00166 struct bpred_params_t
00167 {
00168 farads unit_icap;
00169 farads unit_ecap;
00170 farads unit_scap;
00171 volts vss;
00172 double op_freq;
00173
00174 unsigned global_predictor_bits, global_predictor_entries, prediction_width, local_predictor_size, local_predictor_entries;
00175 unsigned chooser_predictor_bits, chooser_predictor_entries;
00176 unsigned nrows, ncols;
00177 unsigned num_rwports, num_rports, num_wports;
00178 unsigned long bpred_access;
00179
00180
00181 };
00182
00183 struct rf_params_t
00184 {
00185 farads unit_icap;
00186 farads unit_ecap;
00187 farads unit_scap;
00188 volts vss;
00189 unsigned machine_bits, archi_Regs_IRF_size, archi_Regs_FRF_size;
00190 unsigned core_issue_width, core_register_windows_size, core_number_hardware_threads, core_opcode_width, core_virtual_address_width;
00191 unsigned core_temperature, core_tech_node;
00192
00193 double op_freq;
00194 unsigned nrows, ncols;
00195 unsigned num_rwports, num_rports, num_wports;
00196 unsigned long rf_access;
00197 };
00198
00199 struct io_params_t
00200 {
00201 farads unit_scap;
00202 farads unit_icap;
00203 farads unit_lcap;
00204 farads unit_ecap;
00205 volts vss;
00206 double op_freq;
00207
00208
00209 io_style i_o_style;
00210 unsigned opt_io_buffer_num;
00211 double ustrip_len;
00212 unsigned bus_width;
00213 unsigned bus_size;
00214 unsigned io_access_time;
00215 unsigned io_cycle_time;
00216 };
00217
00218 struct logic_params_t
00219 {
00220 farads unit_scap;
00221 farads unit_icap;
00222 farads unit_lcap;
00223 farads unit_ecap;
00224 volts vss;
00225 double op_freq;
00226 unsigned core_instruction_window_size, core_issue_width, core_number_hardware_threads;
00227 unsigned core_decode_width, archi_Regs_IRF_size, archi_Regs_FRF_size;
00228 unsigned core_temperature, core_tech_node;
00229
00230
00231 logic_style lgc_style;
00232 unsigned num_gates;
00233 unsigned num_functions;
00234 unsigned num_fan_in;
00235 unsigned num_fan_out;
00236 };
00237
00238 struct other_params_t
00239 {
00240 farads unit_scap;
00241 farads unit_icap;
00242 farads unit_lcap;
00243 farads unit_ecap;
00244 volts vss;
00245 double op_freq;
00246
00247 };
00248
00249
00250 struct ib_params_t
00251 {
00252 unsigned core_instruction_length, core_issue_width, core_number_hardware_threads;
00253 unsigned core_instruction_buffer_size, num_rwports;
00254 unsigned core_temperature, core_tech_node, core_virtual_address_width, core_virtual_memory_page_size;
00255 };
00256
00257 struct irs_params_t
00258 {
00259 unsigned core_number_hardware_threads, core_instruction_length, core_instruction_window_size;
00260 unsigned core_issue_width;
00261 unsigned core_temperature, core_tech_node;
00262 };
00263
00264 struct decoder_params_t
00265 {
00266 unsigned core_opcode_width;
00267 unsigned core_temperature, core_tech_node;
00268 };
00269
00270 struct bypass_params_t
00271 {
00272 unsigned core_number_hardware_threads, ALU_per_core, machine_bits, FPU_per_core;
00273 unsigned core_opcode_width, core_virtual_address_width;
00274 unsigned core_store_buffer_size, core_memory_ports;
00275 unsigned core_temperature, core_tech_node;
00276 };
00277
00278 struct pipeline_params_t
00279 {
00280 unsigned core_number_hardware_threads, core_fetch_width, core_decode_width;
00281 unsigned core_issue_width, core_commit_width, core_instruction_length, core_virtual_address_width;
00282 unsigned core_opcode_width, core_int_pipeline_depth;
00283 unsigned machine_bits, archi_Regs_IRF_size;
00284 unsigned core_temperature, core_tech_node;
00285 };
00286
00287 typedef struct
00288 {
00289 farads unit_scap;
00290 volts vss;
00291 double op_freq;
00292
00293
00294
00295 int line_size, assoc;
00296 unsigned num_banks;
00297 double throughput, latency;
00298 } btb_params_t;
00299
00300 typedef struct
00301 {
00302 double mc_clock;
00303 unsigned llc_line_length, databus_width, addressbus_width, req_window_size_per_channel;
00304 unsigned memory_channels_per_mc, IO_buffer_size_per_channel;
00305 unsigned memory_number_ranks, memory_peak_transfer_rate;
00306 } mc_params_t;
00307
00308 typedef struct
00309 {
00310 double clockrate;
00311 unsigned has_global_link, flit_bits, input_buffer_entries_per_vc, virtual_channel_per_port, input_ports;
00312 unsigned output_ports, link_throughput, link_latency, horizontal_nodes, vertical_nodes;
00313 topology_style topology;
00314 } router_params_t;
00315
00316
00317 typedef struct
00318 {
00319
00320 double branch_read, branch_write, RAS_read, RAS_write;
00321 double il1_read, il1_readmiss, IB_read, IB_write, BTB_read, BTB_write;
00322 double int_win_read, int_win_write, fp_win_read, fp_win_write, ROB_read, ROB_write;
00323 double iFRAT_read, iFRAT_write, iFRAT_search, fFRAT_read, fFRAT_write, fFRAT_search, iRRAT_write, fRRAT_write;
00324 double ifreeL_read, ifreeL_write, ffreeL_read, ffreeL_write, idcl_read, fdcl_read;
00325 double dl1_read, dl1_readmiss, dl1_write, dl1_writemiss, LSQ_read, LSQ_write;
00326 double itlb_read, itlb_readmiss, dtlb_read, dtlb_readmiss;
00327 double int_regfile_reads, int_regfile_writes, float_regfile_reads, float_regfile_writes, RFWIN_read, RFWIN_write;
00328 double bypass_access;
00329 double router_access;
00330 double L2_read, L2_readmiss, L2_write, L2_writemiss, L3_read, L3_readmiss, L3_write, L3_writemiss;
00331 double L1Dir_read, L1Dir_readmiss, L1Dir_write, L1Dir_writemiss, L2Dir_read, L2Dir_readmiss, L2Dir_write, L2Dir_writemiss;
00332 double memctrl_read, memctrl_write;
00333
00334 double il1_ReadorWrite, il1_accessaddress, il1_datablock, il1_latency, il1_access;
00335 double il2_ReadorWrite, il2_accessaddress, il2_datablock, il2_latency, il2_access;
00336 double dl1_ReadorWrite, dl1_accessaddress, dl1_datablock, dl1_latency, dl1_access;
00337 double dl2_ReadorWrite, dl2_accessaddress, dl2_datablock, dl2_latency, dl2_access;
00338 double itlb_ReadorWrite, itlb_accessaddress, itlb_datablock, itlb_latency, itlb_access;
00339 double dtlb_ReadorWrite, dtlb_accessaddress, dtlb_datablock, dtlb_latency, dtlb_access;
00340 double bpred_access, rf_access, alu_access, fpu_access, mult_access, logic_access, clock_access;
00341 double io_ReadorWrite, io_accessaddress, io_datablock, io_latency, io_access;
00342 } usagecounts_t;
00343
00344
00345
00346 class Power{
00347 public:
00348 Pdissipation_t p_usage_cache_il1;
00349 Pdissipation_t p_usage_cache_il2;
00350 Pdissipation_t p_usage_cache_dl1;
00351 Pdissipation_t p_usage_cache_dl2;
00352 Pdissipation_t p_usage_cache_itlb;
00353 Pdissipation_t p_usage_cache_dtlb;
00354 Pdissipation_t p_usage_clock;
00355 Pdissipation_t p_usage_io;
00356 Pdissipation_t p_usage_logic;
00357 Pdissipation_t p_usage_alu;
00358 Pdissipation_t p_usage_fpu;
00359 Pdissipation_t p_usage_mult;
00360 Pdissipation_t p_usage_rf;
00361 Pdissipation_t p_usage_bpred;
00362 Pdissipation_t p_usage_ib;
00363 Pdissipation_t p_usage_rs;
00364 Pdissipation_t p_usage_decoder;
00365 Pdissipation_t p_usage_bypass;
00366 Pdissipation_t p_usage_exeu;
00367 Pdissipation_t p_usage_pipeline;
00368 Pdissipation_t p_usage_lsq;
00369 Pdissipation_t p_usage_rat;
00370 Pdissipation_t p_usage_rob;
00371 Pdissipation_t p_usage_btb;
00372 Pdissipation_t p_usage_cache_l2;
00373 Pdissipation_t p_usage_mc;
00374 Pdissipation_t p_usage_router;
00375 Pdissipation_t p_usage_loadQ;
00376 Pdissipation_t p_usage_renameU;
00377 Pdissipation_t p_usage_schedulerU;
00378 Pdissipation_t p_usage_cache_l3;
00379 Pdissipation_t p_usage_cache_l1dir;
00380 Pdissipation_t p_usage_cache_l2dir;
00381 Pdissipation_t p_usage_uarch;
00382
00383 cache_params_t cache_il1_tech;
00384 cache_params_t cache_il2_tech;
00385 cache_params_t cache_dl1_tech;
00386 cache_params_t cache_dl2_tech;
00387 cache_params_t cache_itlb_tech;
00388 cache_params_t cache_dtlb_tech;
00389 cache_params_t cache_l2_tech;
00390 cache_params_t cache_l3_tech;
00391 cache_params_t cache_l1dir_tech;
00392 cache_params_t cache_l2dir_tech;
00393 clock_params_t clock_tech;
00394 bpred_params_t bpred_tech;
00395 rf_params_t rf_tech;
00396 io_params_t io_tech;
00397 logic_params_t logic_tech;
00398 other_params_t alu_tech;
00399 other_params_t fpu_tech;
00400 other_params_t mult_tech;
00401 other_params_t uarch_tech;
00402 ib_params_t ib_tech;
00403 irs_params_t irs_tech;
00404 bypass_params_t bypass_tech;
00405 decoder_params_t decoder_tech;
00406 pipeline_params_t pipeline_tech;
00407 core_params_t core_tech;
00408 btb_params_t btb_tech;
00409 mc_params_t mc_tech;
00410 router_params_t router_tech;
00411
00412 float clockRate;
00413 ComponentId_t p_compID;
00414 int p_powerLevel;
00415 bool p_powerMonitor;
00416 pmodel p_powerModel;
00417 Punit_t p_unitPower;
00418 I p_meanPeak, p_meanPeakAll;
00419 double p_areaMcPAT;
00420 unsigned p_numL2, p_machineType;
00421 char *p_McPATxmlpath;
00422 bool p_ifReadEntireXML, p_ifGetMcPATUnitP;
00423
00424
00425 #ifdef LV2_PANALYZER_H
00426 #ifdef CACHE_PANALYZER_H
00427 fu_cache_pspec_t *il1_pspec;
00428 fu_cache_pspec_t *il2_pspec;
00429 fu_cache_pspec_t *dl1_pspec;
00430 fu_cache_pspec_t *dl2_pspec;
00431 fu_cache_pspec_t *itlb_pspec;
00432 fu_cache_pspec_t *dtlb_pspec;
00433 #endif
00434 #ifdef CLOCK_PANALYZER_H
00435 fu_clock_pspec_t *clock_pspec;
00436 #endif
00437 #ifdef MEMORY_PANALYZER_H
00438 fu_sbank_pspec_t *rf_pspec;
00439 fu_sbank_pspec_t *bpred_pspec;
00440 #endif
00441 #ifdef LOGIC_PANALYZER_H
00442 fu_logic_pspec_t *logic_pspec;
00443 #endif
00444 fu_alu_pspec_t *alu_pspec;
00445 fu_mult_pspec_t *mult_pspec;
00446 fu_fpu_pspec_t *fpu_pspec;
00447 #endif
00448
00449 #ifdef IO_PANALYZER_H
00450
00451 fu_io_pspec_t *aio_pspec;
00452
00453 fu_io_pspec_t *dio_pspec;
00454 #endif
00455
00456
00457 int perThreadState;
00458 double C_EXEU;
00459
00460 #ifdef McPAT05_H
00461 #ifdef XML_PARSE_H_
00462 ParseXML *p_Mp1;
00463 #endif
00464 #ifdef PROCESSOR_H_
00465 Processor p_Mproc;
00466 InputParameter interface_ip;
00467 #endif
00468 #ifdef CORE_H_
00469 tlb_core itlb, dtlb;
00470 cache_processor icache, dcache;
00471 BTB_core BTB;
00472 RF_core IRF, FRF, RFWIN, phyIRF, phyFRF;
00473 IB_core IB;
00474 RS_core iRS, iISQ,fRS, fISQ;
00475 LSQ_core LSQ, loadQ;
00476 resultbus int_bypass,intTagBypass, fp_bypass, fpTagBypass;
00477 selection_logic instruction_selection;
00478 dep_resource_conflict_check idcl,fdcl;
00479 full_decoder inst_decoder;
00480 core_pipeline corepipe;
00481 UndifferentiatedCore undifferentiatedCore;
00482 MCclock_network clockNetwork;
00483 ROB_core ROB;
00484 predictor_core predictor;
00485 RAT_core iRRAT,iFRAT,iFRATCG, fRRAT,fFRAT,fFRATCG;
00486 #endif
00487 #ifdef SHAREDCACHE_H_
00488 cache_processor llCache,directory;
00489 pipeline pipeLogicCache, pipeLogicDirectory;
00490 MCclock_network L2clockNetwork;
00491 #endif
00492 #ifdef MEMORYCTRL_H_
00493 selection_logic MC_arb;
00494 cache_processor frontendBuffer,readBuffer, writeBuffer;
00495 pipeline MCpipeLogic;
00496 MCclock_network MCclockNetwork;
00497 MCBackend transecEngine;
00498 MCPHY PHY;
00499 #endif
00500 #ifdef ROUTER_H_
00501 cache_processor inputBuffer, routingTable;
00502 crossbarswitch xbar;
00503 Arbiter vcAllocatorStage1,vcAllocatorStage2, switchAllocatorStage1, switchAllocatorStage2;
00504 wire globalInterconnect;
00505 pipeline RTpipeLogic;
00506 MCclock_network RTclockNetwork;
00507 #endif
00508 #endif
00509
00510
00511
00512 #ifdef McPAT06_H
00513 #ifdef XML_PARSE_H_
00514 ParseXML *p_Mp1;
00515 #endif
00516 #ifdef PROCESSOR_H_
00517 Processor p_Mproc;
00518 Core *p_Mcore;
00519 SharedCache* l2array;
00520 SharedCache* l3array;
00521 SharedCache* l1dirarray;
00522 SharedCache* l2dirarray;
00523 NoC* nocs;
00524 MemoryController* mc;
00525 #endif
00526 #ifdef CORE_H_
00527 InstFetchU * ifu;
00528 LoadStoreU * lsu;
00529 MemManU * mmu;
00530 EXECU * exu;
00531 RENAMINGU * rnu;
00532 Pipeline * corepipe;
00533 UndiffCore * undiffCore;
00534 CoreDynParam coredynp;
00535
00536 ArrayST * globalBPT;
00537 ArrayST * L1_localBPT;
00538 ArrayST * L2_localBPT;
00539 ArrayST * chooser;
00540 ArrayST * RAS;
00541
00542 InstCache icache;
00543 ArrayST * IB;
00544 ArrayST * BTB;
00545 BranchPredictor * BPT;
00546
00547 ArrayST * int_inst_window;
00548 ArrayST * fp_inst_window;
00549 ArrayST * ROB;
00550 selection_logic * instruction_selection;
00551
00552 ArrayST * iFRAT;
00553 ArrayST * fFRAT;
00554 ArrayST * iRRAT;
00555 ArrayST * fRRAT;
00556 ArrayST * ifreeL;
00557 ArrayST * ffreeL;
00558 dep_resource_conflict_check * idcl;
00559 dep_resource_conflict_check * fdcl;
00560
00561 DataCache dcache;
00562 ArrayST * LSQ;
00563 ArrayST * LoadQ;
00564
00565 ArrayST * itlb;
00566 ArrayST * dtlb;
00567
00568 ArrayST * IRF;
00569 ArrayST * FRF;
00570 ArrayST * RFWIN;
00571
00572 RegFU * rfu;
00573 SchedulerU * scheu;
00574 FunctionalUnit * fp_u;
00575 FunctionalUnit * exeu;
00576 McPATComponent bypass;
00577 interconnect * int_bypass;
00578 interconnect * intTagBypass;
00579 interconnect * fp_bypass;
00580 interconnect * fpTagBypass;
00581 #endif
00582 #endif
00583
00584
00585 public:
00586
00587 Power();
00588 Power(ComponentId_t compID) {
00589 PowerInit(compID);}
00590 void PowerInit(ComponentId_t compID) {
00591 clockRate = 2200000000.0;
00592 p_compID = compID;
00593 p_powerLevel = 1; p_powerMonitor = false; p_powerModel = McPAT;
00594 p_meanPeak = p_meanPeakAll = 0.0;
00595 p_areaMcPAT = 0.0; p_machineType = 1; p_numL2 = 1;
00596 p_ifReadEntireXML = p_ifGetMcPATUnitP = false;
00597
00598 #ifdef McPAT05_H
00599 McPAT05initBasic();
00600 #endif
00601
00602
00603 memset(&p_usage_cache_il1,0,sizeof(Pdissipation_t));
00604 memset(&p_usage_cache_il2,0,sizeof(Pdissipation_t));
00605 memset(&p_usage_cache_dl1,0,sizeof(Pdissipation_t));
00606 memset(&p_usage_cache_dl2,0,sizeof(Pdissipation_t));
00607 memset(&p_usage_cache_itlb,0,sizeof(Pdissipation_t));
00608 memset(&p_usage_cache_dtlb,0,sizeof(Pdissipation_t));
00609 memset(&p_usage_clock,0,sizeof(Pdissipation_t));
00610 memset(&p_usage_io,0,sizeof(Pdissipation_t));
00611 memset(&p_usage_logic,0,sizeof(Pdissipation_t));
00612 memset(&p_usage_alu,0,sizeof(Pdissipation_t));
00613 memset(&p_usage_fpu,0,sizeof(Pdissipation_t));
00614 memset(&p_usage_mult,0,sizeof(Pdissipation_t));
00615 memset(&p_usage_uarch,0,sizeof(Pdissipation_t));
00616 memset(&p_usage_rf,0,sizeof(Pdissipation_t));
00617 memset(&p_usage_bpred,0,sizeof(Pdissipation_t));
00618 memset(&p_usage_ib,0,sizeof(Pdissipation_t));
00619 memset(&p_usage_rs,0,sizeof(Pdissipation_t));
00620 memset(&p_usage_decoder,0,sizeof(Pdissipation_t));
00621 memset(&p_usage_bypass,0,sizeof(Pdissipation_t));
00622 memset(&p_usage_exeu,0,sizeof(Pdissipation_t));
00623 memset(&p_usage_pipeline,0,sizeof(Pdissipation_t));
00624 memset(&p_usage_lsq,0,sizeof(Pdissipation_t));
00625 memset(&p_usage_rat,0,sizeof(Pdissipation_t));
00626 memset(&p_usage_rob,0,sizeof(Pdissipation_t));
00627 memset(&p_usage_btb,0,sizeof(Pdissipation_t));
00628 memset(&p_usage_cache_l2,0,sizeof(Pdissipation_t));
00629 memset(&p_usage_mc,0,sizeof(Pdissipation_t));
00630 memset(&p_usage_router,0,sizeof(Pdissipation_t));
00631 memset(&p_usage_loadQ,0,sizeof(Pdissipation_t));
00632 memset(&p_usage_renameU,0,sizeof(Pdissipation_t));
00633 memset(&p_usage_schedulerU,0,sizeof(Pdissipation_t));
00634 memset(&p_usage_cache_l3,0,sizeof(Pdissipation_t));
00635 memset(&p_usage_cache_l1dir,0,sizeof(Pdissipation_t));
00636 memset(&p_usage_cache_l2dir,0,sizeof(Pdissipation_t));
00637 memset(&p_unitPower,0,sizeof(Punit_t));
00638
00639
00640 cache_il1_tech.unit_scap = 32768.0; cache_il1_tech.vss = 0.0; cache_il1_tech.op_freq = 0; cache_il1_tech.num_sets = 0;
00641 cache_il1_tech.line_size = 32; cache_il1_tech.num_bitlines = 0; cache_il1_tech.num_wordlines = 0; cache_il1_tech.assoc = 8;
00642 cache_il1_tech.unit_icap = 0.0; cache_il1_tech.unit_lcap = 0.0; cache_il1_tech.unit_ecap = 0;
00643 cache_il1_tech.num_rwports = cache_il1_tech.num_rports = cache_il1_tech.num_wports = 0; cache_il1_tech.num_banks = 1;
00644 cache_il1_tech.throughput = 3.0; cache_il1_tech.latency = 3.0; cache_il1_tech.core_physical_address_width = 52;
00645 cache_il1_tech.miss_buf_size = cache_il1_tech.fill_buf_size = cache_il1_tech.prefetch_buf_size = 16; cache_il1_tech.wbb_buf_size = 0;
00646 cache_il1_tech.core_virtual_address_width = 64; cache_il1_tech.core_virtual_memory_page_size = 4096; cache_il1_tech.core_number_hardware_threads = 2;
00647 cache_il1_tech.number_entries = 0; cache_il1_tech.core_temperature=360; cache_il1_tech.core_tech_node=32; cache_il1_tech.device_type = 0;
00648 cache_il1_tech.directory_type = 1;
00649
00650 cache_il2_tech.unit_scap = 0.0; cache_il2_tech.vss = 0.0; cache_il2_tech.op_freq = 0; cache_il2_tech.num_sets = 0;
00651 cache_il2_tech.line_size = 0; cache_il2_tech.num_bitlines = 0; cache_il2_tech.num_wordlines = 0; cache_il2_tech.assoc = 0;
00652 cache_il2_tech.unit_icap = 0.0; cache_il2_tech.unit_lcap = 0.0; cache_il2_tech.unit_ecap = 0;
00653 cache_il2_tech.num_rwports = cache_il2_tech.num_rports = cache_il2_tech.num_wports = cache_il2_tech.num_banks = 0;
00654 cache_il2_tech.throughput = cache_il2_tech.latency = 0.0; cache_il2_tech.core_physical_address_width = 0;
00655 cache_il2_tech.miss_buf_size = cache_il2_tech.fill_buf_size = cache_il2_tech.prefetch_buf_size = 0; cache_il2_tech.wbb_buf_size = 0;
00656 cache_il2_tech.core_virtual_address_width = cache_il2_tech.core_virtual_memory_page_size = cache_il2_tech.core_number_hardware_threads = 0;
00657 cache_il2_tech.number_entries = 0; cache_il2_tech.core_temperature=360; cache_il2_tech.core_tech_node=65; cache_il2_tech.device_type = 0;
00658 cache_il2_tech.directory_type = 1;
00659
00660 cache_dl1_tech.unit_scap = 16384.0; cache_dl1_tech.vss = 0.0; cache_dl1_tech.op_freq = 0; cache_dl1_tech.num_sets = 0;
00661 cache_dl1_tech.line_size = 32; cache_dl1_tech.num_bitlines = 0; cache_dl1_tech.num_wordlines = 0; cache_dl1_tech.assoc = 8;
00662 cache_dl1_tech.unit_icap = 0.0; cache_dl1_tech.unit_lcap = 0.0; cache_dl1_tech.unit_ecap = 0;
00663 cache_dl1_tech.num_rwports = cache_dl1_tech.num_rports = cache_dl1_tech.num_wports = cache_dl1_tech.num_banks = 1;
00664 cache_dl1_tech.throughput =3.0; cache_dl1_tech.latency = 3.0; cache_dl1_tech.core_physical_address_width = 52;
00665 cache_dl1_tech.miss_buf_size = cache_dl1_tech.fill_buf_size = cache_dl1_tech.prefetch_buf_size = cache_dl1_tech.wbb_buf_size = 16;
00666 cache_dl1_tech.core_virtual_address_width = cache_dl1_tech.core_virtual_memory_page_size = cache_dl1_tech.core_number_hardware_threads = 0;
00667 cache_dl1_tech.number_entries = 0; cache_dl1_tech.core_temperature=360; cache_dl1_tech.core_tech_node=32; cache_dl1_tech.device_type = 0;
00668 cache_dl1_tech.directory_type = 1;
00669
00670 cache_dl2_tech.unit_scap = 0.0; cache_dl2_tech.vss = 0.0; cache_dl2_tech.op_freq = 0; cache_dl2_tech.num_sets = 0;
00671 cache_dl2_tech.line_size = 0; cache_dl2_tech.num_bitlines = 0; cache_dl2_tech.num_wordlines = 0; cache_dl2_tech.assoc = 0;
00672 cache_dl2_tech.unit_icap = 0.0; cache_dl2_tech.unit_lcap = 0.0; cache_dl2_tech.unit_ecap = 0;
00673 cache_dl2_tech.num_rwports = cache_dl2_tech.num_rports = cache_dl2_tech.num_wports = cache_dl2_tech.num_banks = 0;
00674 cache_dl2_tech.throughput = cache_dl2_tech.latency = 0.0; cache_dl2_tech.core_physical_address_width = 0;
00675 cache_dl2_tech.miss_buf_size = cache_dl2_tech.fill_buf_size = cache_dl2_tech.prefetch_buf_size = 0; cache_dl2_tech.wbb_buf_size = 0;
00676 cache_dl2_tech.core_virtual_address_width = cache_dl2_tech.core_virtual_memory_page_size = cache_dl2_tech.core_number_hardware_threads = 0;
00677 cache_dl2_tech.number_entries = 0; cache_dl2_tech.core_temperature=360; cache_dl2_tech.core_tech_node=65; cache_dl2_tech.device_type = 0;
00678 cache_dl2_tech.directory_type = 1;
00679
00680 cache_itlb_tech.unit_scap = 0.0; cache_itlb_tech.vss = 0.0; cache_itlb_tech.op_freq = 0; cache_itlb_tech.num_sets = 0;
00681 cache_itlb_tech.line_size = 0; cache_itlb_tech.num_bitlines = 0; cache_itlb_tech.num_wordlines = 0; cache_itlb_tech.assoc = 0;
00682 cache_itlb_tech.unit_icap = 0.0; cache_itlb_tech.unit_lcap = 0.0; cache_itlb_tech.unit_ecap = 0;
00683 cache_itlb_tech.num_rwports = cache_itlb_tech.num_rports = cache_itlb_tech.num_wports = cache_itlb_tech.num_banks = 0;
00684 cache_itlb_tech.throughput = cache_itlb_tech.latency = 0.0; cache_itlb_tech.core_physical_address_width = 0;
00685 cache_itlb_tech.miss_buf_size = cache_itlb_tech.fill_buf_size = cache_itlb_tech.prefetch_buf_size = 0; cache_itlb_tech.wbb_buf_size = 0;
00686 cache_itlb_tech.core_virtual_address_width = 64; cache_itlb_tech.core_virtual_memory_page_size = 4096;
00687 cache_itlb_tech.core_number_hardware_threads = 2; cache_itlb_tech.core_physical_address_width = 52; cache_itlb_tech.number_entries = 128;
00688 cache_itlb_tech.core_temperature=360; cache_itlb_tech.core_tech_node=32; cache_itlb_tech.device_type = 0;
00689 cache_itlb_tech.directory_type = 1;
00690
00691 cache_dtlb_tech.unit_scap = 0.0; cache_dtlb_tech.vss = 0.0; cache_dtlb_tech.op_freq = 0; cache_dtlb_tech.num_sets = 0;
00692 cache_dtlb_tech.line_size = 0; cache_dtlb_tech.num_bitlines = 0; cache_dtlb_tech.num_wordlines = 0; cache_dtlb_tech.assoc = 0;
00693 cache_dtlb_tech.unit_icap = 0.0; cache_dtlb_tech.unit_lcap = 0.0; cache_dtlb_tech.unit_ecap = 0;
00694 cache_dtlb_tech.num_rwports = cache_dtlb_tech.num_rports = cache_dtlb_tech.num_wports = cache_dtlb_tech.num_banks = 0;
00695 cache_dtlb_tech.throughput = cache_dtlb_tech.latency = 0.0; cache_dtlb_tech.core_physical_address_width = 0;
00696 cache_dtlb_tech.miss_buf_size = cache_dtlb_tech.fill_buf_size = cache_dtlb_tech.prefetch_buf_size = 0; cache_dtlb_tech.wbb_buf_size = 0;
00697 cache_dtlb_tech.core_virtual_address_width = 64; cache_dtlb_tech.core_virtual_memory_page_size = 4096;
00698 cache_dtlb_tech.core_number_hardware_threads = 2; cache_dtlb_tech.core_physical_address_width = 52; cache_dtlb_tech.number_entries = 128;
00699 cache_dtlb_tech.core_temperature=360; cache_dtlb_tech.core_tech_node=32; cache_dtlb_tech.device_type = 0;
00700 cache_dtlb_tech.directory_type = 1;
00701
00702 clock_tech.unit_scap=0.0; clock_tech.unit_icap=0.0; clock_tech.unit_lcap=0.0; clock_tech.vss=0.0;
00703 clock_tech.op_freq=0; clock_tech.clk_style=NORM_H; clock_tech.skew=0.0; clock_tech.chip_area=0;
00704 clock_tech.node_cap=0.0; clock_tech.opt_clock_buffer_num=0; clock_tech.unit_ecap=0.0;
00705 clock_tech.core_temperature=360; clock_tech.core_tech_node=65;
00706
00707 bpred_tech.unit_icap=0.0; bpred_tech.unit_ecap=0.0; bpred_tech.vss=0.0;
00708 bpred_tech.op_freq=0; bpred_tech.unit_scap=0.0; bpred_tech.bpred_access=0; bpred_tech.nrows=0; bpred_tech.ncols=0;
00709 bpred_tech.num_rwports = bpred_tech.num_rports = bpred_tech.num_wports = 0;
00710 bpred_tech.global_predictor_bits=2; bpred_tech.global_predictor_entries=4096; bpred_tech.prediction_width=1; bpred_tech.local_predictor_size=10;
00711 bpred_tech.local_predictor_entries=1024; bpred_tech.chooser_predictor_bits=2; bpred_tech.chooser_predictor_entries=4096;
00712
00713 rf_tech.unit_scap=0.0; rf_tech.unit_icap=0.0; rf_tech.unit_ecap=0.0; rf_tech.vss=0.0;
00714 rf_tech.op_freq=0; rf_tech.rf_access=0; rf_tech.nrows=0; rf_tech.ncols=0;
00715 rf_tech.num_rwports = rf_tech.num_rports = rf_tech.num_wports = 0;
00716 rf_tech.machine_bits = 64; rf_tech.archi_Regs_IRF_size = 32; rf_tech.archi_Regs_FRF_size = 32; rf_tech.core_issue_width = 1;
00717 rf_tech.core_register_windows_size = 8; rf_tech.core_number_hardware_threads = 4;
00718 rf_tech.core_temperature=360; rf_tech.core_tech_node=65; rf_tech.core_opcode_width =8; rf_tech.core_virtual_address_width = 64;
00719
00720 io_tech.unit_scap=0.0; io_tech.unit_icap=0.0; io_tech.unit_lcap=0.0; io_tech.vss=0.0; io_tech.op_freq=0;
00721 io_tech.i_o_style=OUT; io_tech.opt_io_buffer_num=0; io_tech.ustrip_len=0.0; io_tech.bus_width=0;
00722 io_tech.bus_size=0; io_tech.io_access_time=0; io_tech.io_cycle_time=0; io_tech.unit_ecap=0.0;
00723
00724
00725 logic_tech.unit_scap=0.0; logic_tech.unit_icap=0.0; logic_tech.unit_lcap=0.0; logic_tech.vss=0.0;
00726 logic_tech.op_freq=0; logic_tech.lgc_style=STATIC; logic_tech.num_gates=0; logic_tech.num_functions=0;
00727 logic_tech.num_fan_in=0; logic_tech.num_fan_out=0; logic_tech.unit_ecap=0.0;
00728 logic_tech.core_instruction_window_size = 64; logic_tech.core_issue_width = 1; logic_tech.core_number_hardware_threads = 4;
00729 logic_tech.core_decode_width = 1; logic_tech.archi_Regs_IRF_size = 32; logic_tech.archi_Regs_FRF_size = 32;
00730 logic_tech.core_temperature=360; logic_tech.core_tech_node=65;
00731
00732 alu_tech.unit_scap=50.0; alu_tech.unit_icap=0.0; alu_tech.unit_lcap=0.0; alu_tech.vss=0.0;
00733 alu_tech.op_freq=0; alu_tech.unit_ecap=0.0;
00734
00735 fpu_tech.unit_scap=350.0; fpu_tech.unit_icap=0.0; fpu_tech.unit_lcap=0.0; fpu_tech.vss=0.0;
00736 fpu_tech.op_freq=0; fpu_tech.unit_ecap=0.0;
00737
00738 mult_tech.unit_scap=0.0; mult_tech.unit_icap=0.0; mult_tech.unit_lcap=0.0; mult_tech.vss=0.0;
00739 mult_tech.op_freq=0; mult_tech.unit_ecap=0.0;
00740
00741 ib_tech.core_instruction_length = 32; ib_tech.core_issue_width = 1; ib_tech.core_number_hardware_threads = 4;
00742 ib_tech.core_instruction_buffer_size = 20; ib_tech.num_rwports = 1; ib_tech.core_temperature=360; ib_tech.core_tech_node=65;
00743 ib_tech.core_virtual_address_width = 64; ib_tech.core_virtual_memory_page_size = 4096;
00744
00745 irs_tech.core_number_hardware_threads = 4; irs_tech.core_instruction_length = 32; irs_tech.core_instruction_window_size = 64;
00746 irs_tech.core_issue_width = 1;
00747 irs_tech.core_temperature=360; irs_tech.core_tech_node=65;
00748 #ifdef McPAT05_H
00749 perThreadState = 4;
00750 #endif
00751
00752 decoder_tech.core_opcode_width = 8; decoder_tech.core_temperature=360; decoder_tech.core_tech_node=65;
00753
00754 bypass_tech.core_number_hardware_threads = 4; bypass_tech.ALU_per_core = 3; bypass_tech.machine_bits = 64;
00755 bypass_tech.FPU_per_core = 1; bypass_tech.core_opcode_width = 8; bypass_tech.core_virtual_address_width =64; bypass_tech.machine_bits = 64;
00756 bypass_tech.core_store_buffer_size =32; bypass_tech.core_memory_ports = 1; bypass_tech.core_temperature=360; bypass_tech.core_tech_node=65;
00757
00758 #ifdef McPAT05_H
00759 C_EXEU = 100.0;
00760 #endif
00761
00762 pipeline_tech.core_number_hardware_threads = 4; pipeline_tech.core_fetch_width = 1; pipeline_tech.core_decode_width = 1;
00763 pipeline_tech.core_issue_width = 1; pipeline_tech.core_commit_width = 1; pipeline_tech.core_instruction_length = 32;
00764 pipeline_tech.core_virtual_address_width = 64; pipeline_tech.core_opcode_width = 8; pipeline_tech.core_int_pipeline_depth = 12;
00765 pipeline_tech.machine_bits = 64; pipeline_tech.archi_Regs_IRF_size = 32; pipeline_tech.core_temperature=360; pipeline_tech.core_tech_node=65;
00766
00767 #ifdef McPAT06_H
00768 perThreadState = 8;
00769 #endif
00770
00771 uarch_tech.unit_scap=0.0; uarch_tech.unit_icap=0.0; uarch_tech.unit_lcap=0.0; uarch_tech.vss=0.0;
00772 uarch_tech.op_freq=0; uarch_tech.unit_ecap=0.0;
00773
00774 btb_tech.unit_scap = 8192.0; btb_tech.vss = 0.0; btb_tech.op_freq = 0;
00775 btb_tech.line_size = 4; btb_tech.assoc = 2; btb_tech.num_banks = 1;
00776 btb_tech.throughput =1.0; btb_tech.latency = 3.0;
00777
00778 core_tech.core_physical_address_width=52; core_tech.core_temperature=360; core_tech.core_tech_node=65;
00779 core_tech.core_virtual_address_width =64; core_tech.core_virtual_memory_page_size=4096; core_tech.core_number_hardware_threads=4;
00780 core_tech.machine_bits=64; core_tech.archi_Regs_IRF_size=32; core_tech.archi_Regs_FRF_size=32;
00781 core_tech.core_issue_width=1; core_tech.core_register_windows_size=8; core_tech.core_opcode_width=8;
00782 core_tech.core_instruction_window_size=64; core_tech.core_decode_width=1; core_tech.core_instruction_length=32;
00783 core_tech.core_instruction_buffer_size=20; core_tech.ALU_per_core=3; core_tech.FPU_per_core=1; core_tech.core_ROB_size = 80;
00784 core_tech.core_store_buffer_size=32; core_tech.core_load_buffer_size=32; core_tech.core_memory_ports=1; core_tech.core_fetch_width=1;
00785 core_tech.core_commit_width=1; core_tech.core_int_pipeline_depth=12; core_tech.core_phy_Regs_IRF_size=80; core_tech.core_phy_Regs_FRF_size=80; core_tech.core_RAS_size=32;
00786 core_tech.core_number_of_NoCs = 1; core_tech.core_number_instruction_fetch_ports = 1; core_tech.core_fp_issue_width = 1; core_tech.core_fp_instruction_window_size =64;
00787
00788
00789
00790
00791
00792
00793
00794
00795
00796
00797
00798 cache_l2_tech.unit_scap = 262144.0; cache_l2_tech.vss = 0.0; cache_l2_tech.op_freq = 3500000000.0; cache_l2_tech.num_sets = 0;
00799 cache_l2_tech.line_size = 64; cache_l2_tech.num_bitlines = 0; cache_l2_tech.num_wordlines = 0; cache_l2_tech.assoc = 16;
00800 cache_l2_tech.unit_icap = 0.0; cache_l2_tech.unit_lcap = 0.0; cache_l2_tech.unit_ecap = 0;
00801 cache_l2_tech.num_rwports = cache_l2_tech.num_rports = cache_l2_tech.num_wports = cache_l2_tech.num_banks = 1;
00802 cache_l2_tech.throughput = 2.0; cache_l2_tech.latency = 100.0; cache_l2_tech.core_physical_address_width = 52;
00803 cache_l2_tech.miss_buf_size = cache_l2_tech.fill_buf_size = cache_l2_tech.prefetch_buf_size = 64; cache_l2_tech.wbb_buf_size = 64;
00804 cache_l2_tech.core_virtual_address_width = cache_l2_tech.core_virtual_memory_page_size = cache_l2_tech.core_number_hardware_threads = 0;
00805 cache_l2_tech.number_entries = 0; cache_l2_tech.core_temperature=360; cache_l2_tech.core_tech_node=65; cache_l2_tech.device_type = 1;
00806 cache_l2_tech.directory_type = 1;
00807
00808 cache_l3_tech.unit_scap = 1048576.0; cache_l3_tech.vss = 0.0; cache_l3_tech.op_freq = 3500000000.0; cache_l3_tech.num_sets = 0;
00809 cache_l3_tech.line_size = 64; cache_l3_tech.num_bitlines = 0; cache_l3_tech.num_wordlines = 0; cache_l3_tech.assoc = 16;
00810 cache_l3_tech.unit_icap = 0.0; cache_l3_tech.unit_lcap = 0.0; cache_l3_tech.unit_ecap = 0;
00811 cache_l3_tech.num_rwports = cache_l3_tech.num_rports = cache_l3_tech.num_wports = cache_l3_tech.num_banks = 1;
00812 cache_l3_tech.throughput = 2.0; cache_l3_tech.latency = 100.0; cache_l3_tech.core_physical_address_width = 52;
00813 cache_l3_tech.miss_buf_size = cache_l3_tech.fill_buf_size = cache_l3_tech.prefetch_buf_size = 16; cache_l3_tech.wbb_buf_size = 16;
00814 cache_l3_tech.core_virtual_address_width = cache_l3_tech.core_virtual_memory_page_size = cache_l3_tech.core_number_hardware_threads = 0;
00815 cache_l3_tech.number_entries = 0; cache_l3_tech.core_temperature=360; cache_l3_tech.core_tech_node=65; cache_l3_tech.device_type = 0;
00816 cache_l3_tech.directory_type = 1;
00817
00818 cache_l1dir_tech.unit_scap = 1048576.0; cache_l1dir_tech.vss = 0.0; cache_l1dir_tech.op_freq = 3500000000.0; cache_l1dir_tech.num_sets = 0;
00819 cache_l1dir_tech.line_size = 16; cache_l1dir_tech.num_bitlines = 0; cache_l1dir_tech.num_wordlines = 0; cache_l1dir_tech.assoc = 16;
00820 cache_l1dir_tech.unit_icap = 0.0; cache_l1dir_tech.unit_lcap = 0.0; cache_l1dir_tech.unit_ecap = 0;
00821 cache_l1dir_tech.num_rwports = cache_l1dir_tech.num_rports = cache_l1dir_tech.num_wports = cache_l1dir_tech.num_banks = 1;
00822 cache_l1dir_tech.throughput = 2.0; cache_l1dir_tech.latency = 100.0; cache_l1dir_tech.core_physical_address_width = 52;
00823 cache_l1dir_tech.miss_buf_size = cache_l1dir_tech.fill_buf_size = cache_l1dir_tech.prefetch_buf_size = 8; cache_l1dir_tech.wbb_buf_size = 8;
00824 cache_l1dir_tech.core_virtual_address_width = cache_l1dir_tech.core_virtual_memory_page_size = cache_l1dir_tech.core_number_hardware_threads = 0;
00825 cache_l1dir_tech.number_entries = 0; cache_l1dir_tech.core_temperature=360; cache_l1dir_tech.core_tech_node=65; cache_l1dir_tech.device_type = 0;
00826 cache_l1dir_tech.directory_type = 1;
00827
00828 cache_l2dir_tech.unit_scap = 1048576.0; cache_l2dir_tech.vss = 0.0; cache_l2dir_tech.op_freq = 3500000000.0; cache_l2dir_tech.num_sets = 0;
00829 cache_l2dir_tech.line_size = 16; cache_l2dir_tech.num_bitlines = 0; cache_l2dir_tech.num_wordlines = 0; cache_l2dir_tech.assoc = 16;
00830 cache_l2dir_tech.unit_icap = 0.0; cache_l2dir_tech.unit_lcap = 0.0; cache_l2dir_tech.unit_ecap = 0;
00831 cache_l2dir_tech.num_rwports = cache_l2dir_tech.num_rports = cache_l2dir_tech.num_wports = cache_l2dir_tech.num_banks = 1;
00832 cache_l2dir_tech.throughput = 2.0; cache_l2dir_tech.latency = 100.0; cache_l2dir_tech.core_physical_address_width = 52;
00833 cache_l2dir_tech.miss_buf_size = cache_l2dir_tech.fill_buf_size = cache_l2dir_tech.prefetch_buf_size = 8; cache_l2dir_tech.wbb_buf_size = 8;
00834 cache_l2dir_tech.core_virtual_address_width = cache_l2dir_tech.core_virtual_memory_page_size = cache_l2dir_tech.core_number_hardware_threads = 0;
00835 cache_l2dir_tech.number_entries = 0; cache_l2dir_tech.core_temperature=360; cache_l2dir_tech.core_tech_node=65; cache_l2dir_tech.device_type = 0;
00836 cache_l2dir_tech.directory_type = 1;
00837
00838 mc_tech.mc_clock=400000000.0; mc_tech.llc_line_length=64; mc_tech.databus_width=128; mc_tech.addressbus_width=51; mc_tech.req_window_size_per_channel=32;
00839 mc_tech.memory_channels_per_mc=2; mc_tech.IO_buffer_size_per_channel=32;
00840 mc_tech.memory_number_ranks=2; mc_tech.memory_peak_transfer_rate=6400;
00841
00842 router_tech.clockrate=3500000000.0; router_tech.has_global_link=0; router_tech.flit_bits=128; router_tech.input_buffer_entries_per_vc=16;
00843 router_tech.virtual_channel_per_port=2; router_tech.input_ports=5; router_tech.horizontal_nodes=1; router_tech.vertical_nodes=2;
00844 router_tech.output_ports=8; router_tech.link_throughput=1; router_tech.link_latency=1; router_tech.topology = RING;
00845
00846 #ifdef LV2_PANALYZER_H
00847 il1_pspec = NULL; il2_pspec = NULL; dl1_pspec = NULL; dl2_pspec = NULL; itlb_pspec = NULL;
00848 dtlb_pspec = NULL; clock_pspec = NULL; logic_pspec = NULL; mult_pspec = NULL;
00849 bpred_pspec = NULL; rf_pspec = NULL; alu_pspec = NULL; fpu_pspec = NULL;
00850 #endif
00851 #ifdef IO_PANALYZER_H
00852 aio_pspec = dio_pspec = NULL;
00853 #endif
00854 #ifdef XML_PARSE_H_
00855 p_Mp1= new ParseXML();
00856 #endif
00857 }
00858
00859
00860
00861
00862
00863 void setTech(ComponentId_t compID, Component::Params_t params, ptype power_type);
00864 void getUnitPower(ptype power_type, int user_data);
00865
00866 Pdissipation_t& getPower(Cycle_t current, ptype power_type, usagecounts_t counts, int total_cycles);
00867 void updatePowUsage(Pdissipation_t *comp_pusage, const I& totalPowerUsage, const I& dynamicPower, const I& leakage, const I& TDP, Cycle_t current);
00868 double estimateClockDieAreaSimPan();
00869 double estimateClockNodeCapSimPan();
00870 double estimateAreaMcPAT(){return p_areaMcPAT;};
00871 void resetCounts(usagecounts_t counts){ memset(&counts,0,sizeof(usagecounts_t));}
00872
00873
00874 #ifdef McPAT05_H
00875 void McPAT05Setup();
00876
00877 void McPAT05initBasic();
00878 void McPATinitIcache();
00879 void McPATinitDcache();
00880 void McPATinitItlb();
00881 void McPATinitDtlb();
00882 void McPATinitIB();
00883 void McPATinitIRS();
00884 void McPATinitRF();
00885 void McPATinitBypass();
00886 void McPATinitLogic();
00887 void McPATinitDecoder();
00888 void McPATinitPipeline();
00889 void McPATinitClock();
00890 #endif
00891
00892 #ifdef McPAT06_H
00893 void McPATSetup();
00894 #endif
00895
00896
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00924 };
00925 }
00926 #endif // POWER_H
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00930