00001 #ifndef PPCPIMCALLS_H
00002 #define PPCPIMCALLS_H
00003
00004 #include "pimSysCallDefs.h"
00005 #include "pimSysCallTypes.h"
00006
00007 #define _INLINE_ static inline
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017 _INLINE_ int PIM_AMO(void *addr, PIM_amo_types op, int imm)
00018 {
00019 int result;
00020 asm volatile ("mr r3, %1\n"
00021 "mr r4, %2\n"
00022 "mr r5, %3\n"
00023 "li r0, "SS_PIM_AMO_STR"\n"
00024 "sc\n"
00025 "mr %0, r3, 0\n"
00026 : "=r" (result)
00027 : "r" (addr), "r" (op), "r" (imm)
00028 : "r0", "r3", "r4", "r5", "memory");
00029 return result;
00030 }
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040 _INLINE_ int PIM_threadCreate(void* start_routine, void* arg)
00041 {
00042 int result;
00043 asm volatile ("mr r3, %1\n"
00044 "mr r4, %2\n"
00045 "li r0, "SS_PIM_FORK_STR"\n"
00046 "sc\n"
00047 "mr %0, r3, 0\n"
00048 : "=r" (result)
00049 : "r" (start_routine), "r" (arg)
00050 : "r0", "r3", "r4");
00051 return result;
00052 }
00053
00054
00055
00056
00057
00058
00059
00060
00061
00062
00063 _INLINE_ int PIM_threadCreateWithStack(void* start_routine, void* arg, void* stack)
00064 {
00065 int result;
00066 asm volatile (
00067 "mr r5, r1\n\t"
00068 "mr r1, %3\n\t"
00069 "mr r3, %1\n\t"
00070 "mr r4, %2\n\t"
00071 "li r0, "SS_PIM_FORK_STR"\n\t"
00072 "sc\n\t"
00073 "mr %0, r3, 0\n\t"
00074 "mr r1, r5\n"
00075 : "=r" (result)
00076 : "r" (start_routine), "r" (arg), "r" (stack)
00077 : "r0", "r3", "r4", "r5");
00078 return result;
00079 }
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089 _INLINE_ int PIM_spawnToCoProc(PIM_coProc coProc, void* start_routine,
00090 void* arg)
00091 {
00092 int result;
00093 asm volatile ("mr r3, %1\n"
00094 "mr r4, %2\n"
00095 "mr r5, %3\n"
00096 "li r0, "SS_PIM_SPAWN_TO_COPROC_STR"\n"
00097 "sc\n"
00098 "mr %0, r3\n"
00099 : "=r" (result)
00100 : "r" (coProc), "r" (start_routine), "r" (arg)
00101 : "r0", "r3", "r4", "r5");
00102 return result;
00103 }
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113
00114 _INLINE_ int PIM_spawnToCoProcWithStack(PIM_coProc coProc,
00115 void* start_routine,
00116 void* arg, void* stack)
00117 {
00118 int result;
00119 asm volatile (
00120 "mr r6, r1\n\t"
00121 "mr r1, %4\n\t"
00122 "mr r3, %1\n\t"
00123 "mr r4, %2\n\t"
00124 "mr r5, %3\n\t"
00125 "li r0, "SS_PIM_SPAWN_TO_COPROC_STR"\n\t"
00126 "sc\n\t"
00127 "mr %0, r3\n\t"
00128 "mr r1, r6\n"
00129 : "=r" (result)
00130 : "r" (coProc), "r" (start_routine), "r" (arg), "r" (stack)
00131 : "r0", "r3", "r4", "r5", "r6");
00132 return result;
00133 }
00134
00135
00136
00137
00138 _INLINE_ int PIM_loadAndSpawnToCoProcWithStack(PIM_coProc coProc,
00139 void* start_routine,
00140 void* r3Arg, void* r6Arg, void* r7Arg,
00141 void* r8Arg, void* r9Arg, void* stack)
00142 {
00143 int result;
00144 asm volatile (
00145 "mr r10, r1\n\t"
00146 "mr r1, %8\n\t"
00147 "mr r3, %1\n\t"
00148 "mr r4, %2\n\t"
00149 "mr r5, %3\n\t"
00150 "mr r6, %4\n\t"
00151 "mr r7, %5\n\t"
00152 "mr r8, %6\n\t"
00153 "mr r9, %7\n\t"
00154 "li r0, "SS_PIM_SPAWN_TO_COPROC_STR"\n\t"
00155 "sc\n\t"
00156 "mr %0, r3\n\t"
00157 "mr r1, r10\n"
00158 : "=r" (result)
00159 : "r" (coProc), "r" (start_routine), "r" (r3Arg), "r" (r6Arg),
00160 "r" (r7Arg), "r" (r8Arg), "r" (r9Arg), "r" (stack)
00161 : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10");
00162 return result;
00163 }
00164
00165
00166
00167
00168 _INLINE_ int PIM_loadAndSpawnToCoProc(PIM_coProc coProc, void* start_routine,
00169 void* r3Arg, void* r6Arg, void* r7Arg,
00170 void* r8Arg, void* r9Arg) {
00171 int result;
00172 asm volatile ("mr r3, %1\n"
00173 "mr r4, %2\n"
00174 "mr r5, %3\n"
00175 "mr r6, %4\n"
00176 "mr r7, %5\n"
00177 "mr r8, %6\n"
00178 "mr r9, %7\n"
00179 "li r0, "SS_PIM_SPAWN_TO_COPROC_STR"\n"
00180 "sc\n"
00181 "mr %0, r3\n"
00182 : "=r" (result)
00183 : "r" (coProc), "r" (start_routine), "r" (r3Arg), "r" (r6Arg),
00184 "r" (r7Arg), "r" (r8Arg), "r" (r9Arg)
00185 : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9");
00186 return result;
00187 }
00188
00189
00190
00191
00192
00193
00194
00195
00196
00197
00198
00199
00200
00201
00202
00203
00204
00205 _INLINE_ int PIM_loadAndSpawnToLocaleStack(int locale,
00206 void* start_routine,
00207 void* r3Arg, void* r6Arg,
00208 void* r7Arg, void* r8Arg,
00209 void* r9Arg) {
00210 int result;
00211 asm volatile ("mr r3, %1\n"
00212 "mr r4, %2\n"
00213 "mr r5, %3\n"
00214 "mr r6, %4\n"
00215 "mr r7, %5\n"
00216 "mr r8, %6\n"
00217 "mr r9, %7\n"
00218 "li r0, "SS_PIM_SPAWN_TO_LOCALE_STACK_STR"\n"
00219 "sc\n"
00220 "mr %0, r3\n"
00221 : "=r" (result)
00222 : "r" (locale), "r" (start_routine), "r" (r3Arg), "r" (r6Arg),
00223 "r" (r7Arg), "r" (r8Arg), "r" (r9Arg)
00224 : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9");
00225 return result;
00226 }
00227
00228
00229
00230
00231
00232 _INLINE_ int PIM_loadAndSpawnToLocaleStackStopped(int locale, void* start_routine,
00233 void* r3Arg, void* r6Arg, void* r7Arg,
00234 void* r8Arg, void* r9Arg)
00235 {
00236 int result;
00237 asm volatile (
00238 "mr r3, %1\n"
00239 "mr r4, %2\n"
00240 "mr r5, %3\n"
00241 "mr r6, %4\n"
00242 "mr r7, %5\n"
00243 "mr r8, %6\n"
00244 "mr r9, %7\n"
00245 "li r0, "SS_PIM_SPAWN_TO_LOCALE_STACK_STOPPED_STR"\n"
00246 "sc\n"
00247 "mr %0, r3\n"
00248 : "=r" (result)
00249 : "r" (locale), "r" (start_routine), "r" (r3Arg), "r" (r6Arg),
00250 "r" (r7Arg), "r" (r8Arg), "r" (r9Arg)
00251 : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9");
00252 return result;
00253 }
00254
00255
00256 _INLINE_ int PIM_startStoppedThread(int tid, int shep)
00257 {
00258 int result;
00259 asm volatile (
00260 "mr r3, %1\n"
00261 "mr r4, %2\n"
00262 "li r0, "SS_PIM_START_STOPPED_THREAD_STR"\n"
00263 "sc\n"
00264 "mr %0, r3\n"
00265 : "=r" (result)
00266 : "r" (tid), "r" (shep)
00267 : "r0", "r3", "r4");
00268 return result;
00269 }
00270
00271 _INLINE_ int PIM_switchAddrMode(PIM_addrMode mode)
00272 {
00273 int result;
00274 asm volatile ("mr r3, %1\n"
00275 "li r0, "SS_PIM_SWITCH_ADDR_MODE_STR"\n"
00276 "sc\n"
00277 "mr %0, r3\n"
00278 : "=r" (result)
00279 : "r" (mode)
00280 : "r0", "r3");
00281 return result;
00282 }
00283
00284
00285
00286
00287 _INLINE_ unsigned int PIM_fastFileRead (char * filename_addr,
00288 void * buf_addr,
00289 unsigned int maxBytes,
00290 unsigned int offset)
00291 {
00292 unsigned int bytes = 0;
00293 asm volatile ("mr r3, %1\n"
00294 "mr r4, %2\n"
00295 "mr r5, %3\n"
00296 "mr r6, %4\n"
00297 "li r0, "SS_PIM_FFILE_RD_STR"\n"
00298 "sc\n"
00299 "mr %0, r3\n"
00300 : "=r" (bytes)
00301 : "r" (filename_addr), "r" (buf_addr), "r" (maxBytes), "r" (offset)
00302 : "r0", "r3", "r4", "r5", "r6", "memory" );
00303 return bytes;
00304 }
00305
00306
00307
00308
00309
00310
00311 #define ALLOC_GLOBAL 0
00312 #define ALLOC_LOCAL_ADDR 1
00313 #define ALLOC_LOCAL_ID 2
00314
00315 _INLINE_ void* PIM_alloc(const unsigned int size, const unsigned int type, const unsigned int opt)
00316 {
00317 register unsigned int result;
00318 asm volatile ("mr r3, %1\n"
00319 "mr r4, %2\n"
00320 "mr r5, %3\n"
00321 "li r0, "SS_PIM_MALLOC_STR"\n"
00322 "sc\n"
00323 "mr %0, r3\n"
00324 : "=r" (result)
00325 : "r" (size), "r" (type), "r" (opt)
00326 : "r0", "r3", "r4", "r5", "memory");
00327 return (void*)result;
00328 }
00329
00330 _INLINE_ void* PIM_globalMalloc(const unsigned int size)
00331 {
00332 return PIM_alloc(size, ALLOC_GLOBAL, 0);
00333 }
00334
00335 _INLINE_ void* PIM_localMallocNearAddr(const unsigned int size, const void * addr)
00336 {
00337 return PIM_alloc(size, ALLOC_LOCAL_ADDR, (unsigned int)addr);
00338 }
00339
00340 _INLINE_ void* PIM_localMallocAtID(const unsigned int size, const unsigned int ID)
00341 {
00342 return PIM_alloc(size, ALLOC_LOCAL_ID, ID);
00343 }
00344
00345 _INLINE_ void* PIM_fastMalloc(unsigned int size)
00346 {
00347 unsigned int result;
00348 asm volatile ("lwz r3, %1\n"
00349 "li r4, 0\n"
00350 "li r0, "SS_PIM_MALLOC_STR"\n"
00351 "sc\n"
00352 "mr %0, r3\n"
00353 : "=r" (result)
00354 : "m" (size)
00355 : "r0", "r3", "r4", "memory");
00356 return (void*)result;
00357 }
00358
00359
00360
00361
00362
00363
00364
00365 _INLINE_ void* PIM_fastStackMalloc(unsigned int size)
00366 {
00367 unsigned int result;
00368 asm volatile ("lwz r3, %1\n"
00369 "li r4, 1\n"
00370 "li r0, "SS_PIM_MALLOC_STR"\n"
00371 "sc\n"
00372 "mr %0, r3\n"
00373 : "=r" (result)
00374 : "m" (size)
00375 : "r0", "r3", "r4", "memory");
00376 return (void*)result;
00377 }
00378
00379
00380
00381
00382
00383
00384 _INLINE_ unsigned int PIM_fastFreeSize(void *ptr, unsigned int size)
00385 {
00386 unsigned int result;
00387 unsigned int addr = (unsigned int)ptr;
00388 asm volatile ("lwz r3, %1\n"
00389 "lwz r4, %2\n"
00390 "li r0, "SS_PIM_FREE_STR"\n"
00391 "sc\n"
00392 "mr %0, r3\n"
00393 : "=r" (result)
00394 : "m" (addr), "m" (size)
00395 : "r0", "r3", "r4", "memory");
00396
00397 return result;
00398 }
00399
00400
00401
00402
00403 _INLINE_ void PIM_writeMem(unsigned int *addr, unsigned int data) {
00404 asm volatile ("lwz r3, %0\n"
00405 "lwz r4, %1\n"
00406 "li r0, "SS_PIM_WRITE_MEM_STR"\n"
00407 "sc\n"
00408 :
00409 : "m" (addr), "m" (data)
00410 : "r0", "r3", "r4", "memory");
00411 }
00412
00413 _INLINE_ unsigned int PIM_fastFree(void *ptr)
00414 {
00415 unsigned int size = 0;
00416 return PIM_fastFreeSize (ptr, size);
00417 }
00418
00419 _INLINE_ unsigned int PIM_hwRand(void)
00420 {
00421 unsigned int result;
00422 asm volatile ("li r0, "SS_PIM_RAND_STR"\n"
00423 "sc\n"
00424 "mr %0, r3\n"
00425 : "=r" (result)
00426 :
00427 : "r0", "r3");
00428 return result;
00429 }
00430
00431 _INLINE_ int PIM_quickPrint(unsigned int a, unsigned int b, unsigned int c)
00432 {
00433 int result;
00434 asm volatile ("mr r3, %1\n"
00435 "mr r4, %2\n"
00436 "mr r5, %3\n"
00437 "li r0, "SS_PIM_QUICK_PRINT_STR"\n"
00438 "sc\n"
00439 "mr %0, r3\n"
00440 : "=r" (result)
00441 : "r" (a), "r" (b), "r" (c)
00442 : "r0", "r3", "r4", "r5", "memory");
00443 return result;
00444 }
00445
00446 _INLINE_ int PIM_trace(unsigned int a, unsigned int b, unsigned int c)
00447 {
00448 int result;
00449 asm volatile ("mr r3, %1\n"
00450 "mr r4, %2\n"
00451 "mr r5, %3\n"
00452 "li r0, "SS_PIM_TRACE_STR"\n"
00453 "sc\n"
00454 "mr %0, r3\n"
00455 : "=r" (result)
00456 : "r" (a), "r" (b), "r" (c)
00457 : "r0", "r3", "r4", "r5");
00458 return result;
00459 }
00460
00461
00462
00463
00464
00465
00466
00467
00468
00469 _INLINE_ int PIM_mem_region_create(int region, void * vstart,
00470 unsigned long size, void * kstart, int cached)
00471 {
00472 int result;
00473 asm volatile ("mr r3, %1\n"
00474 "mr r4, %2\n"
00475 "mr r5, %3\n"
00476 "mr r6, %4\n"
00477 "mr r7, %5\n"
00478 "li r0, "SS_PIM_MEM_REGION_CREATE_STR"\n"
00479 "sc\n"
00480 "mr %0, r3\n"
00481 : "=r" (result)
00482 : "r" (region), "r" (vstart), "r" (size), "r" (kstart), "r" (cached)
00483 : "r0", "r3", "r4", "r5", "r6", "r7", "memory");
00484 return result;
00485 }
00486
00487 _INLINE_ int PIM_mem_region_get(int region, unsigned long *addr,
00488 unsigned long *size )
00489 {
00490 int result;
00491 asm volatile ("mr r3, %1\n"
00492 "mr r4, %2\n"
00493 "mr r5, %3\n"
00494 "li r0, "SS_PIM_MEM_REGION_GET_STR"\n"
00495 "sc\n"
00496 "mr %0, r3\n"
00497 : "=r" (result)
00498 : "r" (region), "r" (addr), "r" (size)
00499 : "r0", "r3", "r4", "r5", "memory");
00500 return result;
00501 }
00502
00503 _INLINE_ void PIM_writeSpecial(PIM_cmd c, unsigned int v1)
00504 {
00505 asm volatile ("mr r3, %0\n"
00506 "mr r4, %1\n"
00507 "li r0, "SS_PIM_WRITE_SPECIAL_STR"\n"
00508 "sc\n"
00509 :
00510 : "r" (c), "r" (v1)
00511 : "r0", "r3", "r4");
00512 }
00513
00514 _INLINE_ void PIM_writeSpecial2(PIM_cmd c, unsigned int v1, unsigned int v2)
00515 {
00516 asm volatile ("mr r3, %0\n"
00517 "mr r4, %1\n"
00518 "mr r5, %2\n"
00519 "li r0, "SS_PIM_WRITE_SPECIAL2_STR"\n"
00520 "sc\n"
00521 :
00522 : "r" (c), "r" (v1), "r" (v2)
00523 : "r0", "r3", "r4", "r5");
00524 }
00525
00526 _INLINE_ void PIM_writeSpecial3(PIM_cmd c, unsigned int v1, unsigned int v2,
00527 unsigned int v3)
00528 {
00529 asm volatile ("mr r3, %0\n"
00530 "mr r4, %1\n"
00531 "mr r5, %2\n"
00532 "mr r6, %3\n"
00533 "li r0, "SS_PIM_WRITE_SPECIAL3_STR"\n"
00534 "sc\n"
00535 :
00536 : "r" (c), "r" (v1), "r" (v2), "r" (v3)
00537 : "r0", "r3", "r4", "r5", "r6");
00538 }
00539
00540 _INLINE_ void PIM_writeSpecial4(PIM_cmd c, unsigned int v1, unsigned int v2,
00541 unsigned int v3, unsigned int v4)
00542 {
00543 asm volatile ("mr r3, %0\n"
00544 "mr r4, %1\n"
00545 "mr r5, %2\n"
00546 "mr r6, %3\n"
00547 "mr r7, %4\n"
00548 "li r0, "SS_PIM_WRITE_SPECIAL4_STR"\n"
00549 "sc\n"
00550 :
00551 : "r" (c), "r" (v1), "r" (v2), "r" (v3), "r" (v4)
00552 : "r0", "r3", "r4", "r5", "r6", "r7");
00553 }
00554
00555 _INLINE_ void PIM_writeSpecial5(PIM_cmd c, unsigned int v1, unsigned int v2,
00556 unsigned int v3, unsigned int v4,
00557 unsigned int v5)
00558 {
00559 asm volatile ("mr r3, %0\n"
00560 "mr r4, %1\n"
00561 "mr r5, %2\n"
00562 "mr r6, %3\n"
00563 "mr r7, %4\n"
00564 "mr r8, %5\n"
00565 "li r0, "SS_PIM_WRITE_SPECIAL5_STR"\n"
00566 "sc\n"
00567 :
00568 : "r" (c), "r" (v1), "r" (v2), "r" (v3), "r" (v4), "r" (v5)
00569 : "r0", "r3", "r4", "r5", "r6", "r7", "r8");
00570 }
00571
00572 _INLINE_ void PIM_writeSpecial6(PIM_cmd c, unsigned int v1, unsigned int v2,
00573 unsigned int v3, unsigned int v4,
00574 unsigned int v5, unsigned int v6)
00575 {
00576 asm volatile ("mr r3, %0\n"
00577 "mr r4, %1\n"
00578 "mr r5, %2\n"
00579 "mr r6, %3\n"
00580 "mr r7, %4\n"
00581 "mr r8, %5\n"
00582 "mr r9, %6\n"
00583 "li r0, "SS_PIM_WRITE_SPECIAL6_STR"\n"
00584 "sc\n"
00585 :
00586 : "r" (c), "r" (v1), "r" (v2), "r" (v3), "r" (v4), "r" (v5), "r" (v6)
00587 : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9");
00588 }
00589
00590 _INLINE_ void PIM_writeSpecial7(PIM_cmd c, unsigned int v1, unsigned int v2,
00591 unsigned int v3, unsigned int v4,
00592 unsigned int v5, unsigned int v6,
00593 unsigned int v7)
00594 {
00595 asm volatile ("mr r3, %0\n"
00596 "mr r4, %1\n"
00597 "mr r5, %2\n"
00598 "mr r6, %3\n"
00599 "mr r7, %4\n"
00600 "mr r8, %5\n"
00601 "mr r9, %6\n"
00602 "mr r10, %7\n"
00603 "li r0, "SS_PIM_WRITE_SPECIAL7_STR"\n"
00604 "sc\n"
00605 :
00606 : "r" (c), "r" (v1), "r" (v2), "r" (v3), "r" (v4), "r" (v5), "r" (v6), "r" (v7)
00607 : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10");
00608 }
00609
00610 _INLINE_ int PIM_rwSpecial3(PIM_cmd c, unsigned int v1, unsigned int v2,
00611 unsigned int v3)
00612 {
00613 int result;
00614 asm volatile ("mr r3, %1\n"
00615 "mr r4, %2\n"
00616 "mr r5, %3\n"
00617 "mr r6, %4\n"
00618 "li r0, "SS_PIM_WRITE_SPECIAL3_STR"\n"
00619 "sc\n"
00620 "mr %0, r3\n"
00621 : "=r" (result)
00622 : "r" (c), "r" (v1), "r" (v2), "r" (v3)
00623 : "r0", "r3", "r4", "r5", "r6", "memory");
00624 return result;
00625 }
00626
00627 _INLINE_ int PIM_readSpecial(PIM_cmd c)
00628 {
00629 int result;
00630 asm volatile ("mr r3, %1\n"
00631 "li r0, "SS_PIM_READ_SPECIAL_STR"\n"
00632 "sc\n"
00633 "mr %0, r3\n"
00634 : "=r" (result)
00635 : "r" (c)
00636 : "r0", "r3", "memory");
00637 return result;
00638 }
00639
00640 _INLINE_ int PIM_readSpecial1(PIM_cmd c, unsigned int v)
00641 {
00642 int result;
00643 asm volatile ("mr r3, %1\n"
00644 "mr r4, %2\n"
00645 "li r0, "SS_PIM_READ_SPECIAL1_STR"\n"
00646 "sc\n"
00647 "mr %0, r3\n"
00648 : "=r" (result)
00649 : "r" (c), "r" (v)
00650 : "r0", "r3", "r4", "memory");
00651 return result;
00652 }
00653
00654 _INLINE_ int PIM_readSpecial2(PIM_cmd c, unsigned int v1, unsigned int v2)
00655 {
00656 int result;
00657 asm volatile ("mr r3, %1\n"
00658 "mr r4, %2\n"
00659 "mr r5, %3\n"
00660 "li r0, "SS_PIM_READ_SPECIAL2_STR"\n"
00661 "sc\n"
00662 "mr %0, r3\n"
00663 : "=r" (result)
00664 : "r" (c), "r" (v1), "r" (v2)
00665 : "r0", "r3", "r4", "r5", "memory");
00666 return result;
00667 }
00668
00669 _INLINE_ int PIM_readSpecial3(PIM_cmd c, unsigned int v1, unsigned int v2,
00670 unsigned int v3)
00671 {
00672 int result;
00673 asm volatile ("mr r3, %1\n"
00674 "mr r4, %2\n"
00675 "mr r5, %3\n"
00676 "mr r6, %4\n"
00677 "li r0, "SS_PIM_READ_SPECIAL3_STR"\n"
00678 "sc\n"
00679 "mr %0, r3\n"
00680 : "=r" (result)
00681 : "r" (c), "r" (v1), "r" (v2), "r" (v3)
00682 : "r0", "r3", "r4", "r5", "r6", "memory");
00683 return result;
00684 }
00685
00686 _INLINE_ int PIM_readSpecial4(PIM_cmd c, unsigned int v1, unsigned int v2,
00687 unsigned int v3, unsigned int v4)
00688 {
00689 int result;
00690 asm volatile ("mr r3, %1\n"
00691 "mr r4, %2\n"
00692 "mr r5, %3\n"
00693 "mr r6, %4\n"
00694 "mr r7, %5\n"
00695 "li r0, "SS_PIM_READ_SPECIAL4_STR"\n"
00696 "sc\n"
00697 "mr %0, r3\n"
00698 : "=r" (result)
00699 : "r" (c), "r" (v1), "r" (v2), "r" (v3), "r" (v4)
00700 : "r0", "r3", "r4", "r5", "r6", "r7", "memory");
00701 return result;
00702 }
00703
00704 _INLINE_ int PIM_readSpecial1_2(PIM_cmd c, unsigned int v, unsigned int *o2)
00705 {
00706 int result1;
00707 int result2;
00708 asm volatile ("mr r3, %2\n"
00709 "mr r4, %3\n"
00710 "li r0, "SS_PIM_READ_SPECIAL1_2_STR"\n"
00711 "sc\n"
00712 "mr %0, r3\n"
00713 "mr %1, r4\n"
00714 : "=r" (result1), "=r" (result2)
00715 : "r" (c), "r" (v)
00716 : "r0", "r3", "r4", "memory");
00717 *o2 = result1;
00718 return result2;
00719 }
00720
00721 _INLINE_ int PIM_readSpecial_2(PIM_cmd c, unsigned int *o2)
00722 {
00723 int result1;
00724 int result2;
00725 asm volatile ("mr r3, %2\n"
00726 "li r0, "SS_PIM_READ_SPECIAL_2_STR"\n"
00727 "sc\n"
00728 "mr %0, r3\n"
00729 "mr %1, r4\n"
00730 : "=r" (result1), "=r" (result2)
00731 : "r" (c)
00732 : "r0", "r3", "r4", "memory");
00733 *o2 = result1;
00734 return result2;
00735 }
00736
00737 _INLINE_ int PIM_readSpecial1_5(PIM_cmd c, unsigned int v, unsigned int *o2,
00738 unsigned int *o3, unsigned int *o4,
00739 unsigned int *o5)
00740 {
00741 int result1, result2, result3, result4, result5;
00742 asm volatile ("mr r3, %5\n"
00743 "mr r4, %6\n"
00744 "li r0, "SS_PIM_READ_SPECIAL1_5_STR"\n"
00745 "sc\n"
00746 "mr %0, r3\n"
00747 "mr %1, r4\n"
00748 "mr %2, r5\n"
00749 "mr %3, r6\n"
00750 "mr %4, r7\n"
00751 : "=r" (result1), "=r" (result2), "=r" (result3), "=r" (result4), "=r" (result5)
00752 : "r" (c), "r" (v)
00753 : "r0", "r3", "r4", "r5", "r6", "r7", "memory");
00754 *o2 = result1; *o3 = result2; *o4 = result3; *o5 = result4;
00755 return result5;
00756 }
00757
00758 _INLINE_ void PIM_readSpecial1_6(PIM_cmd c, unsigned int v, unsigned int *o1,
00759 unsigned int *o2, unsigned int *o3,
00760 unsigned int *o4, unsigned int *o5,
00761 unsigned *o6)
00762 {
00763 int result1, result2, result3, result4, result5, result6;
00764 asm volatile ("mr r3, %6\n"
00765 "mr r4, %7\n"
00766 "li r0, "SS_PIM_READ_SPECIAL1_6_STR"\n"
00767 "sc\n"
00768 "mr %0, r3\n"
00769 "mr %1, r4\n"
00770 "mr %2, r5\n"
00771 "mr %3, r6\n"
00772 "mr %4, r7\n"
00773 "mr %5, r8\n"
00774 : "=r" (result1), "=r" (result2), "=r" (result3), "=r" (result4), "=r" (result5), "=r" (result6)
00775 : "r" (c), "r" (v)
00776 : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "memory");
00777 *o1 = result1; *o2 = result2; *o3 = result3; *o4 = result4;
00778 *o5 = result5; *o6 = result6;
00779 }
00780
00781 _INLINE_ void PIM_readSpecial1_7(PIM_cmd c, unsigned int v, unsigned int *o1,
00782 unsigned int *o2, unsigned int *o3,
00783 unsigned int *o4, unsigned int *o5,
00784 unsigned int *o6, unsigned int *o7)
00785 {
00786 int result1, result2, result3, result4, result5, result6, result7;
00787 asm volatile ("mr r3, %7\n"
00788 "mr r4, %8\n"
00789 "li r0, "SS_PIM_READ_SPECIAL1_7_STR"\n"
00790 "sc\n"
00791 "mr %0, r3\n"
00792 "mr %1, r4\n"
00793 "mr %2, r5\n"
00794 "mr %3, r6\n"
00795 "mr %4, r7\n"
00796 "mr %5, r8\n"
00797 "mr %6, r9\n"
00798 : "=r" (result1), "=r" (result2), "=r" (result3), "=r" (result4), "=r" (result5), "=r" (result6), "=r" (result7)
00799 : "r" (c), "r" (v)
00800 : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "memory");
00801 *o1 = result1; *o2 = result2; *o3 = result3; *o4 = result4;
00802 *o5 = result5; *o6 = result6; *o7 = result7;
00803 }
00804
00805 #if defined(__cplusplus)
00806 _INLINE_ void PIM_writeSpecial(PIM_cmd c, unsigned int v1, unsigned int v2) {
00807 PIM_writeSpecial2(c, v1, v2);
00808 }
00809 _INLINE_ void PIM_writeSpecial(PIM_cmd c, unsigned int v1, unsigned int v2,
00810 unsigned int v3) {
00811 PIM_writeSpecial3(c, v1, v2, v3);
00812 }
00813 _INLINE_ void PIM_writeSpecial(PIM_cmd c, unsigned int v1, unsigned int v2,
00814 unsigned int v3, unsigned int v4) {
00815 PIM_writeSpecial4(c, v1, v2, v3, v4);
00816 }
00817 _INLINE_ void PIM_writeSpecial(PIM_cmd c, unsigned int v1, unsigned int v2,
00818 unsigned int v3, unsigned int v4,
00819 unsigned int v5) {
00820 PIM_writeSpecial5(c, v1, v2, v3, v4, v5);
00821 }
00822 _INLINE_ int PIM_readSpecial(PIM_cmd c, unsigned int v) {
00823 return PIM_readSpecial1(c, v);
00824 }
00825 _INLINE_ int PIM_readSpecial(PIM_cmd c, unsigned int v1, unsigned int v2) {
00826 return PIM_readSpecial2(c, v1, v2);
00827 }
00828 _INLINE_ int PIM_readSpecial(PIM_cmd c, unsigned int v1, unsigned int v2,
00829 unsigned int v3) {
00830 return PIM_readSpecial3(c, v1, v2, v3);
00831 }
00832 _INLINE_ int PIM_readSpecial(PIM_cmd c, unsigned int v1, unsigned int v2,
00833 unsigned int v3, unsigned int v4) {
00834 return PIM_readSpecial4(c, v1, v2, v3, v4);
00835 }
00836 #endif
00837
00838
00839
00840
00841
00842
00843
00844
00845 _INLINE_ unsigned int PIM_feb_lock(unsigned int* a)
00846 {
00847 unsigned int result;
00848 asm volatile ("mr r3, %1\n"
00849 "li r0, "SS_PIM_LOCK_STR"\n"
00850 "sc\n"
00851 "mr %0, r3\n"
00852 : "=r" (result)
00853 : "r" (a)
00854 : "r0", "r3", "memory");
00855 return result;
00856 }
00857
00858
00859
00860
00861
00862
00863
00864
00865 _INLINE_ unsigned int PIM_feb_unlock(unsigned int* a)
00866 {
00867 unsigned int result;
00868 asm volatile ("mr r3, %1\n"
00869 "li r0, "SS_PIM_UNLOCK_STR"\n"
00870 "sc\n"
00871 "mr %0, r3\n"
00872 : "=r" (result)
00873 : "r" (a)
00874 : "r0", "r3", "memory");
00875 return result;
00876 }
00877
00878
00879
00880
00881
00882
00883 _INLINE_ unsigned int PIM_feb_readff(volatile unsigned int* a)
00884 {
00885 unsigned int result;
00886 asm volatile ("mr r3, %1\n"
00887 "li r0, "SS_PIM_READFF_STR"\n"
00888 "sc\n"
00889 "mr %0, r3\n"
00890 : "=r" (result)
00891 : "r" (a)
00892 : "r0", "r3", "memory");
00893 return result;
00894 }
00895
00896
00897
00898
00899
00900
00901 _INLINE_ unsigned int PIM_feb_readfe(volatile unsigned int* a)
00902 {
00903 unsigned int result;
00904 asm volatile ("mr r3, %1\n"
00905 "li r0, "SS_PIM_READFE_STR"\n"
00906 "sc\n"
00907 "mr %0, r3\n"
00908 : "=r" (result)
00909 : "r" (a)
00910 : "r0", "r3", "memory");
00911 return result;
00912 }
00913
00914
00915
00916
00917 _INLINE_ int PIM_atomicIncrement(volatile unsigned int* a, unsigned int i)
00918 {
00919 int result;
00920
00921 asm volatile ("mr r3, %1\n"
00922 "mr r4, %2\n"
00923 "li r0, "SS_PIM_ATOMIC_INCREMENT_STR"\n"
00924 "sc\n"
00925 "mr %0, r3\n"
00926 : "=r" (result)
00927 : "r" (a), "r" (i)
00928 : "r0", "r3", "r4", "memory");
00929
00930 return result;
00931 }
00932
00933
00934
00935
00936
00937 _INLINE_ void PIM_feb_writeef(volatile unsigned int* a, unsigned int v)
00938 {
00939 asm volatile ("mr r3, %0\n"
00940 "mr r4, %1\n"
00941 "li r0, "SS_PIM_WRITEEF_STR"\n"
00942 "sc\n"
00943 :
00944 : "r" (a), "r" (v)
00945 : "r0", "r3", "r4", "memory");
00946 }
00947
00948
00949
00950
00951
00952
00953
00954
00955 _INLINE_ void PIM_feb_fill(unsigned int* a) {
00956 asm volatile ("mr r3, %0\n"
00957 "li r0, "SS_PIM_FILL_FE_STR"\n"
00958 "sc\n"
00959 :
00960 : "r" (a)
00961 : "r0", "r3", "memory");
00962 }
00963
00964
00965
00966
00967
00968 _INLINE_ void PIM_feb_empty(unsigned int* a) {
00969 asm volatile ("mr r3, %0\n"
00970 "li r0, "SS_PIM_EMPTY_FE_STR"\n"
00971 "sc\n"
00972 :
00973 : "r" (a)
00974 : "r0", "r3", "memory");
00975 }
00976
00977
00978
00979
00980
00981
00982
00983
00984 _INLINE_ void PIM_feb_purge(unsigned int* a)
00985 {
00986 PIM_feb_empty(a);
00987 }
00988
00989
00990
00991
00992
00993 _INLINE_ int PIM_feb_is_full(unsigned int* a)
00994 {
00995 int result;
00996 asm volatile ("mr r3, %1\n"
00997 "li r0, "SS_PIM_IS_FE_FULL_STR"\n"
00998 "sc\n"
00999 "mr %0, r3\n"
01000 : "=r" (result)
01001 : "r" (a)
01002 : "r0", "r3");
01003 return result;
01004 }
01005
01006
01007
01008
01009
01010 _INLINE_ int PIM_feb_tryef(unsigned int* a)
01011 {
01012 int result;
01013 asm volatile ("mr r3, %1\n"
01014 "li r0, "SS_PIM_TRYEF_STR"\n"
01015 "sc\n"
01016 "mr %0, r3\n"
01017 : "=r" (result)
01018 : "r" (a)
01019 : "r0", "r3", "memory");
01020 return result;
01021 }
01022
01023 #ifdef __cplusplus
01024
01025
01026
01027
01028
01029
01030
01031
01032 template <class T>
01033 _INLINE_ T PIM_readff(volatile T* a) {
01034 return (T)PIM_feb_readff((volatile unsigned int*)a);
01035 }
01036
01037
01038
01039
01040
01041
01042
01043
01044 template <class T>
01045 _INLINE_ T PIM_readfe(volatile T* a) {
01046 return (T)PIM_feb_readfe((volatile unsigned int*)a);
01047 }
01048
01049
01050
01051
01052
01053
01054
01055 template <class T>
01056 _INLINE_ void PIM_writeef(volatile T* a, T v) {
01057 PIM_feb_writeef((volatile unsigned int*)a, (unsigned int)v);
01058 }
01059
01060
01061
01062
01063
01064
01065
01066 template <class T>
01067 _INLINE_ void PIM_fill(T* a) {
01068 PIM_feb_fill((unsigned int*)a);
01069 }
01070
01071
01072
01073
01074
01075
01076
01077 template <class T>
01078 _INLINE_ void PIM_empty(T* a) {
01079 PIM_feb_empty((unsigned int*) a);
01080 }
01081
01082
01083
01084
01085
01086
01087
01088
01089 template <class T>
01090 _INLINE_ int PIM_purge(T* a) {
01091 return PIM_feb_purge((unsigned int*)a);
01092 }
01093
01094
01095
01096
01097
01098
01099
01100 template <class T>
01101 _INLINE_ int PIM_is_full(T* a) {
01102 return PIM_feb_is_full((unsigned int*)a);
01103 }
01104 #endif
01105
01106
01107
01108
01109
01110 _INLINE_ void PIM_resetCounters(void)
01111 {
01112 asm volatile ("li r0, "SS_PIM_RESET_STR"\n"
01113 "sc\n"
01114 :
01115 :
01116 : "r0");
01117 }
01118
01119
01120
01121
01122 _INLINE_ void PIM_threadExit(void) __attribute__((noreturn));
01123 _INLINE_ void PIM_threadExit(void)
01124 {
01125 asm volatile ("li r0, "SS_PIM_EXIT_STR"\n"
01126 "sc\n"
01127 : : : "r0");
01128
01129
01130
01131
01132
01133
01134 for (;;) continue;
01135 }
01136
01137
01138 _INLINE_ void PIM_threadExitFree(void) __attribute__((__noreturn__));
01139 _INLINE_ void PIM_threadExitFree(void)
01140 {
01141 asm volatile ("li r0, "SS_PIM_EXIT_FREE_STR"\n"
01142 "sc\n"
01143 : : : "r0");
01144
01145
01146
01147
01148
01149
01150 for (;;) continue;
01151 }
01152
01153 #endif