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sst/core/techModels/libMcPAT/htree.h

00001 /*****************************************************************************
00002  *                                McPAT
00003  *                      SOFTWARE LICENSE AGREEMENT
00004  *            Copyright 2009 Hewlett-Packard Development Company, L.P.
00005  *                          All Rights Reserved
00006  *
00007  * Permission to use, copy, and modify this software and its documentation is
00008  * hereby granted only under the following terms and conditions.  Both the
00009  * above copyright notice and this permission notice must appear in all copies
00010  * of the software, derivative works or modified versions, and any portions
00011  * thereof, and both notices must appear in supporting documentation.
00012  *
00013  * Any User of the software ("User"), by accessing and using it, agrees to the
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00017  * modify, distribute copies, create derivate works and publicly display and
00018  * use, any changes, modifications, enhancements or extensions made to the
00019  * software by User, including but not limited to those affording
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00024  *
00025  * Correspondence should be provided to HP at:
00026  *
00027  * Director of Intellectual Property Licensing
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00033  * The software may be further distributed by User (but not offered for
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00038  * THE SOFTWARE IS PROVIDED "AS IS" WITH ANY AND ALL ERRORS AND DEFECTS
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00047  ***************************************************************************/
00048 #ifndef __HTREE_H__
00049 #define __HTREE_H__
00050 
00051 #include "area.h"
00052 #include "parameter.h"
00053 #include <vector>
00054 
00055 using namespace std;
00056 
00057 
00058 class HtreeNode
00059 {
00060  public:
00061   HtreeNode(int num_gate_stage);
00062 
00063   int number_gates;
00064   int min_number_gates;
00065   double width_n[MAX_NUMBER_GATES_STAGE];
00066   double width_p[MAX_NUMBER_GATES_STAGE];
00067   double c_gate_load;
00068   double c_wire_load;
00069   double r_wire_load;
00070   double f_wire;
00071   double delay;
00072   double width_nor2_n;  // only used in DataoutHtreeNode
00073   double width_nor2_p;  // only used in DataoutHtreeNode
00074   powerDef power;
00075 };
00076 
00077 
00078 class AddrDatainHtreeNode
00079 {
00080  public:
00081   AddrDatainHtreeNode(
00082       int num_htree_nodes_,
00083       double htree_seg_length,
00084       bool is_dram_);
00085 
00086   vector<HtreeNode> node;
00087   double            delay;
00088   powerDef          power;
00089   vector<double>    length_wire_htree_node;  //[MAX_NUMBER_GATES_STAGE];
00090   bool              is_dram;
00091   int               num_htree_nodes;
00092   vector<Area>      area;
00093 
00094   void initialize();
00095   void compute_widths();
00096   void compute_areas();
00097   powerDef compute_power(int htree_node);
00098   pair<double, double> compute_delays(double inrisetime);  // return <outrisetime, delay>
00099 };
00100 
00101 
00102 // TODO : following two classes must be combined properly
00103 class DataoutHtreeNode : public AddrDatainHtreeNode
00104 {
00105  public:
00106   DataoutHtreeNode(
00107       int num_htree_nodes_,
00108       const vector<double> & len_wire_htree_node_,
00109       bool is_dram_);
00110 
00111   const vector<double> & len_wire_htree_node;
00112 
00113   void initialize();
00114   void compute_widths();
00115   void compute_areas();
00116   // here compute_delays compute power as well
00117   pair<double, double> compute_delays(double inrisetime);  // return <outrisetime, delay>
00118 };
00119 
00120 
00121 class Dout_htree_node
00122 {
00123  public:
00124   Dout_htree_node(const Area & subarray, bool is_dram);
00125 
00126   uint32_t num_gates;
00127   uint32_t num_gates_min;
00128   double   width_n[MAX_NUMBER_GATES_STAGE];
00129   double   width_p[MAX_NUMBER_GATES_STAGE];
00130   double   width_nor2_n;
00131   double   width_nor2_p;
00132   double   C_gate_ld;
00133   double   C_wire_ld;
00134   double   R_wire_ld;
00135   double   f_wire;
00136   double   delay;
00137   powerDef power;
00138 };
00139 
00140 
00141 class AddrDatainHtreeAtMatInterval
00142 {
00143  public:
00144   AddrDatainHtreeAtMatInterval(
00145       double mat_dimension,
00146       int num_htree_nodes_,
00147       bool is_dram_);
00148 
00149   double buffer_opt_sizing;
00150   double buffer_segment_opt_length;
00151   double buffer_width_n[2];
00152   double buffer_width_p[2];
00153   double nand2_buffer_width_n[2];
00154   double nand2_buffer_width_p[2];
00155   double tristate_driver_nand2_width_n;
00156   double tristate_driver_nand2_width_p;
00157   double tristate_driver_nor2_width_n;
00158   double tristate_driver_nor2_width_p;
00159   double time_constant_internal_buffer;
00160   double time_constant_buffer_driving_buffer;
00161   double time_constant_buffer_driving_final_seg;
00162   powerDef power_buffer;
00163   powerDef power_buffer_driving_nand2_buffer;
00164   powerDef power_nand2_buffer_driving_buffer;
00165   powerDef power_nand2_buffer_driving_nand2_buffer;
00166   powerDef power_nand2_buffer_driving_final_seg;
00167   powerDef power_tristate_driver_driving_buffer;
00168   powerDef power_tristate_driver_driving_tristate_driver;
00169   powerDef power_buffer_driving_tristate_driver;
00170   powerDef power_tristate_driver_driving_final_seg;
00171   powerDef power_buffer_driving_final_seg;
00172   double area_nand2_buffer_driving_final_seg;
00173   double area_nand2_buffer_driving_nand2_buffer;
00174   double area_nand2_buffer_driving_buffer;
00175   double area_buffer;
00176   double area_buffer_driving_final_seg;
00177   double area_buffer_driving_nand2_buffer;
00178   double area_tristate_driver_driving_final_seg;
00179   double area_tristate_driver_driving_tristate_driver;
00180   double area_tristate_driver_driving_buffer;
00181   double mat_dimension;
00182   double max_delay_between_buffers;
00183 
00184   bool is_dram;
00185   int  num_htree_nodes;
00186 
00187   void compute_area_drivers(const BankHtreeSizing & bank_htree_sz);
00188   Area compute_area_addr_datain(double len_htree_seg, int htree_node_num, const BankHtreeSizing & bank_htree_sz) const;
00189   Area compute_area_dataout_ver(double len_htree_seg, int htree_node_num, const BankHtreeSizing & bank_htree_sz) const;
00190   pair<double, double> compute_delay_addr_datain(
00191       double c_output_load,
00192       int    broadcast,
00193       double inrisetime,
00194       const BankHtreeSizing & bank_htree_sz);  // return <outrisetime, delay>
00195   pair<double, double> compute_delay_dataout_ver(
00196       double inrisetime,
00197       const BankHtreeSizing & bank_htree_sz);  // return <outrisetime, delay>
00198   powerDef compute_power_addr_datain(
00199       double len_htree_seg,
00200       int    htree_node_num,
00201       const BankHtreeSizing & bank_htree_sz);
00202   powerDef compute_power_dataout_ver(
00203       double len_htree_seg,
00204       int    htree_node_num,
00205       const BankHtreeSizing & bank_htree_sz);
00206 };
00207 
00208 
00209 class ArrayEdgeToBankEdgeHtreeSizing
00210 {
00211  public:
00212   ArrayEdgeToBankEdgeHtreeSizing();
00213   void compute_widths(bool is_dram);
00214   pair<double, double> compute_delays(double inrisetime, double length, double horizontal_htree_input_load, bool is_dram, powerDef & power) const;  // return <outrisetime, delay>
00215   struct repeater_solution
00216   {
00217     double lcap;
00218     double wcap;
00219     double delay;
00220     powerDef power;
00221   };
00222 
00223  public:
00224   double opt_sizing;
00225   double opt_segment_length;
00226   double width_inverter_nmos;
00227   double width_inverter_pmos;
00228 };
00229 
00230 
00231 class BankHtreeSizing
00232 {
00233  public:
00234   BankHtreeSizing();
00235   void compute_widths(bool is_dram);
00236 
00237   struct buffer_solution
00238   {
00239     double lcap;
00240     double wcap;
00241     double delay;
00242     powerDef power;
00243   };
00244 
00245  public:
00246   double buffer_opt_sizing;
00247   double buffer_segment_opt_length;
00248   double buffer_width_n[2];
00249   double buffer_width_p[2];
00250   double nand2_buffer_width_n[2];
00251   double nand2_buffer_width_p[2];
00252   double tristate_driver_nand2_width_n;
00253   double tristate_driver_nand2_width_p;
00254   double tristate_driver_nor2_width_n;
00255   double tristate_driver_nor2_width_p;
00256 };
00257 
00258 
00259 #endif
00260 

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