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sst/core/techModels/libsim-panalyzer/clock_panalyzer.h

00001 /*
00002 * clock_panalyzer.h - basic clock power analyzer data types, strcutres and 
00003 * thier manipulation functions. 
00004 *
00005 * This file is a part of the PowerAnalyzer tool suite written by
00006 * Nam Sung Kim as a part of the PowerAnalyzer Project.
00007 *  
00008 * The tool suite is currently maintained by Nam Sung Kim.
00009 * 
00010 * Copyright (C) 2001 by Nam Sung Kim
00011 *
00012 * This source file is distributed "as is" in the hope that it will be
00013 * useful.  The tool set comes with no warranty, and no author or
00014 * distributor accepts any responsibility for the consequences of its
00015 * use. 
00016 * 
00017 * Everyone is granted permission to copy, modify and redistribute
00018 * this tool set under the following conditions:
00019 * 
00020 *    This source code is distributed for non-commercial use only. 
00021 *    Please contact the maintainer for restrictions applying to 
00022 *    commercial use.
00023 *
00024 *    Permission is granted to anyone to make or distribute copies
00025 *    of this source code, either as received or modified, in any
00026 *    medium, provided that all copyright notices, permission and
00027 *    nonwarranty notices are preserved, and that the distributor
00028 *    grants the recipient permission for further redistribution as
00029 *    permitted by this document.
00030 *
00031 *    Permission is granted to distribute this file in compiled
00032 *    or executable form under the same conditions that apply for
00033 *    source code, provided that either:
00034 *
00035 *    A. it is accompanied by the corresponding machine-readable
00036 *       source code,
00037 *    B. it is accompanied by a written offer, with no time limit,
00038 *       to give anyone a machine-readable copy of the corresponding
00039 *       source code in return for reimbursement of the cost of
00040 *       distribution.  This written offer must permit verbatim
00041 *       duplication by anyone, or
00042 *    C. it is distributed by someone who received only the
00043 *       executable form, and is accompanied by a copy of the
00044 *       written offer of source code that they received concurrently.
00045 *
00046 * In other words, you are welcome to use, share and improve this
00047 * source file.  You are forbidden to forbid anyone else to use, share
00048 * and improve what you give them.
00049 */
00050 
00051 #ifndef CLOCK_PANALYZER_H
00052 #define CLOCK_PANALYZER_H
00053 #include "panalyzer.h"
00054 
00055 /* clock clocktree style - this should be done by configurator - future work! */
00056 typedef enum _fu_clocktree_style_t{
00057     Htree,
00058     balHtree
00059 } fu_clocktree_style_t;
00060 
00061 typedef struct _fu_clock_pspec_t {
00062         char *name; /* name */
00063         fu_pmodel_mode_t pmodel; /* power model mode */
00064         double opfreq, svolt; /* operating frequency/supply voltage */
00065         fu_dimension_t *dimension;      
00066 
00067         fu_clocktree_style_t ctree_style; /* clock tree style */
00068         double cskew; /* clock skew */
00069         double tcnodeCeff; /* total clocked node capacitnace */
00070         double ncbstages_opt; /* number of clock buffer stages */
00071 
00072         /* effective pdissipation capacitances */
00073         fu_Ceffs_t *Ceffs;
00074         fu_pdissipation_t *pdissipation; /* pdissipation statistics */
00075         fu_pdissipation_t pmwindow[MaxPMWindows]; /* power monitoring window */
00076 } fu_clock_pspec_t;
00077 
00078 fu_clock_pspec_t *
00079 create_clock_panalyzer(
00080         char *name, /* memory name */
00081         fu_pmodel_mode_t pmodel, /* clock tree power model mode */
00082         /* memory operating parameters: operating frequency/supply voltage */
00083         double opfreq, double svolt, 
00084         double tdarea, /* total die area in um^2 */
00085         double tcnodeCeff, /* total clocked node capacitnace */
00086         fu_clocktree_style_t ctree_style, /* clock tree style */
00087         double cskew, /* clock skew */
00088         unsigned ncbstages_opt, /* optimial number of clock buffer stages */
00089 
00090         /* switching/internal/lekage  effective capacitances */
00091         double sCeff, double iCeff, double lCeff);
00092 
00093 /* clock panalyzer: estimate pdissipatino of the structure */
00094 void 
00095 clock_panalyzer(
00096         fu_clock_pspec_t *pspec, /* memory pspec*/
00097         tick_t now /* current simulation time */);
00098 
00099 /* estimate total clock distribution tree wire */
00100 double 
00101 estimate_tcdtwireCeff(
00102         fu_clock_pspec_t *pspec);
00103 
00104 /* estimate clock distribution tree branch wire length */
00105 double 
00106 estimate_lbr(
00107         int N, /* Nth branch */
00108         double ledge /* edge length */);
00109 
00110 /* estimate clock distribution tree and buffer capacitance */
00111 fu_Ceffs_t 
00112 estimate_tcdtCeff(
00113         fu_clock_pspec_t *pspec);
00114 
00115 /* Added for SST */
00116 double 
00117 SSTclock_panalyzer(
00118         fu_clock_pspec_t *pspec, /* memory pspec*/
00119         tick_t now /* current simulation time */);
00120 
00121 
00122 #endif /* CLOCK_PANALYZER_H */
00123 

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