00001 /* 00002 NetWinder Floating Point Emulator 00003 (c) Rebel.com, 1998-1999 00004 00005 Direct questions, comments to Scott Bambrough <scottb@netwinder.org> 00006 00007 This program is free software; you can redistribute it and/or modify 00008 it under the terms of the GNU General Public License as published by 00009 the Free Software Foundation; either version 2 of the License, or 00010 (at your option) any later version. 00011 00012 This program is distributed in the hope that it will be useful, 00013 but WITHOUT ANY WARRANTY; without even the implied warranty of 00014 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00015 GNU General Public License for more details. 00016 00017 You should have received a copy of the GNU General Public License 00018 along with this program; if not, write to the Free Software 00019 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 00020 */ 00021 00022 #ifndef __FPSR_H__ 00023 #define __FPSR_H__ 00024 00025 /* 00026 The FPSR is a 32 bit register consisting of 4 parts, each exactly 00027 one byte. 00028 00029 SYSTEM ID 00030 EXCEPTION TRAP ENABLE BYTE 00031 SYSTEM CONTROL BYTE 00032 CUMULATIVE EXCEPTION FLAGS BYTE 00033 00034 The FPCR is a 32 bit register consisting of bit flags. 00035 */ 00036 00037 /* SYSTEM ID 00038 ------------ 00039 Note: the system id byte is read only */ 00040 00041 typedef unsigned int FPSR; /* type for floating point status register */ 00042 typedef unsigned int FPCR; /* type for floating point control register */ 00043 00044 #define MASK_SYSID 0xff000000 00045 #define BIT_HARDWARE 0x80000000 00046 #define FP_EMULATOR 0x01000000 /* System ID for emulator */ 00047 #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */ 00048 00049 /* EXCEPTION TRAP ENABLE BYTE 00050 ----------------------------- */ 00051 00052 #define MASK_TRAP_ENABLE 0x00ff0000 00053 #define MASK_TRAP_ENABLE_STRICT 0x001f0000 00054 #define BIT_IXE 0x00100000 /* inexact exception enable */ 00055 #define BIT_UFE 0x00080000 /* underflow exception enable */ 00056 #define BIT_OFE 0x00040000 /* overflow exception enable */ 00057 #define BIT_DZE 0x00020000 /* divide by zero exception enable */ 00058 #define BIT_IOE 0x00010000 /* invalid operation exception enable */ 00059 00060 /* SYSTEM CONTROL BYTE 00061 ---------------------- */ 00062 00063 #define MASK_SYSTEM_CONTROL 0x0000ff00 00064 #define MASK_TRAP_STRICT 0x00001f00 00065 00066 #define BIT_AC 0x00001000 /* use alternative C-flag definition 00067 for compares */ 00068 #define BIT_EP 0x00000800 /* use expanded packed decimal format */ 00069 #define BIT_SO 0x00000400 /* select synchronous operation of FPA */ 00070 #define BIT_NE 0x00000200 /* NaN exception bit */ 00071 #define BIT_ND 0x00000100 /* no denormalized numbers bit */ 00072 00073 /* CUMULATIVE EXCEPTION FLAGS BYTE 00074 ---------------------------------- */ 00075 00076 #define MASK_EXCEPTION_FLAGS 0x000000ff 00077 #define MASK_EXCEPTION_FLAGS_STRICT 0x0000001f 00078 00079 #define BIT_IXC 0x00000010 /* inexact exception flag */ 00080 #define BIT_UFC 0x00000008 /* underflow exception flag */ 00081 #define BIT_OFC 0x00000004 /* overfloat exception flag */ 00082 #define BIT_DZC 0x00000002 /* divide by zero exception flag */ 00083 #define BIT_IOC 0x00000001 /* invalid operation exception flag */ 00084 00085 /* Floating Point Control Register 00086 ----------------------------------*/ 00087 00088 #define BIT_RU 0x80000000 /* rounded up bit */ 00089 #define BIT_IE 0x10000000 /* inexact bit */ 00090 #define BIT_MO 0x08000000 /* mantissa overflow bit */ 00091 #define BIT_EO 0x04000000 /* exponent overflow bit */ 00092 #define BIT_SB 0x00000800 /* store bounce */ 00093 #define BIT_AB 0x00000400 /* arithmetic bounce */ 00094 #define BIT_RE 0x00000200 /* rounding exception */ 00095 #define BIT_DA 0x00000100 /* disable FPA */ 00096 00097 #define MASK_OP 0x00f08010 /* AU operation code */ 00098 #define MASK_PR 0x00080080 /* AU precision */ 00099 #define MASK_S1 0x00070000 /* AU source register 1 */ 00100 #define MASK_S2 0x00000007 /* AU source register 2 */ 00101 #define MASK_DS 0x00007000 /* AU destination register */ 00102 #define MASK_RM 0x00000060 /* AU rounding mode */ 00103 #define MASK_ALU 0x9cfff2ff /* only ALU can write these bits */ 00104 #define MASK_RESET 0x00000d00 /* bits set on reset, all others cleared */ 00105 #define MASK_WFC MASK_RESET 00106 #define MASK_RFC ~MASK_RESET 00107 00108 #endif