00001
00002 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
00003 typedef struct clk_setup_t clk_setup_t;
00004 struct clk_setup_t {
00005 clk_setup_cb cb;
00006 void *opaque;
00007 };
00008 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
00009 {
00010 if (clk->cb != NULL)
00011 (*clk->cb)(clk->opaque, freq);
00012 }
00013
00014 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
00015
00016 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
00017 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
00018 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
00019 int (*dcr_write_error)(int dcrn));
00020 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
00021 dcr_read_cb drc_read, dcr_write_cb dcr_write);
00022 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
00023
00024 void ppc40x_core_reset (CPUState *env);
00025 void ppc40x_chip_reset (CPUState *env);
00026 void ppc40x_system_reset (CPUState *env);
00027 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
00028
00029 extern CPUWriteMemoryFunc *PPC_io_write[];
00030 extern CPUReadMemoryFunc *PPC_io_read[];
00031 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
00032
00033 void ppc40x_irq_init (CPUState *env);
00034 void ppce500_irq_init (CPUState *env);
00035 void ppc6xx_irq_init (CPUState *env);
00036 void ppc970_irq_init (CPUState *env);
00037
00038
00039 enum {
00040 ARCH_PREP = 0,
00041 ARCH_MAC99,
00042 ARCH_HEATHROW,
00043 };
00044