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00013 #ifndef COMPONENTS_TRIG_CPU_BANDWIDTH_H
00014 #define COMPONENTS_TRIG_CPU_BANDWIDTH_H
00015
00016 #include "sst/elements/portals4_sm/trig_cpu/application.h"
00017 #include "sst/elements/portals4_sm/trig_cpu/trig_cpu.h"
00018
00019 #define BW_BUF_SIZE (128*1024)
00020
00021 class bandwidth : public application {
00022 public:
00023 bandwidth(trig_cpu *cpu) : application(cpu)
00024 {
00025 ptl = cpu->getPortalsHandle();
00026 }
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00121
00122 bool
00123 operator()(Event *ev)
00124 {
00125 ptl_md_t md;
00126 ptl_me_t me;
00127
00128 ptl_handle_me_t me_handle;
00129
00130
00131 switch (state) {
00132 case 0:
00133 printf("%5d: Inializing...\n",my_id);
00134
00135 ptl->PtlCTAlloc(PTL_CT_OPERATION,ct_handle);
00136 ptl->PtlCTAlloc(PTL_CT_OPERATION,ct_handle2);
00137 state = 1;
00138 break;
00139
00140 case 1:
00141 recv_buffer = new uint64_t[2*1024];
00142 send_buffer = new uint64_t[2*1024];
00143
00144 {
00145 for ( int i = 0; i < (2*1024); i++ ) {
00146 recv_buffer[i] = 0;
00147 send_buffer[i] = i;
00148 }
00149 }
00150
00151 if ( my_id == 0 ) {
00152 md.start = NULL;
00153 md.length = 0;
00154 md.eq_handle = PTL_EQ_NONE;
00155 md.ct_handle = PTL_CT_NONE;
00156 ptl->PtlMDBind(md, &md_handle);
00157 }
00158 else {
00159 md.start = recv_buffer;
00160 md.length = 8*2*1024;
00161 md.eq_handle = PTL_EQ_NONE;
00162 md.ct_handle = ct_handle2;
00163 ptl->PtlMDBind(md, &md_handle);
00164 }
00165
00166 state = 2;
00167 break;
00168
00169 case 2:
00170
00171
00172 if ( my_id == 0 ) {
00173 me.start = send_buffer;
00174 me.length = 8*2*1024;
00175 me.ignore_bits = ~0x0;
00176 me.ct_handle = ct_handle;
00177 ptl->PtlMEAppend(0, me, PTL_PRIORITY_LIST, NULL, me_handle);
00178 }
00179 else {
00180 me.start = NULL;
00181 me.length = 0;
00182 me.ignore_bits = ~0x0;
00183 me.ct_handle = ct_handle;
00184 ptl->PtlMEAppend(0, me, PTL_PRIORITY_LIST, NULL, me_handle);
00185 }
00186 if ( my_id == 0 ) {
00187 state = 6;
00188 }
00189 else {
00190 state = 3;
00191 }
00192 break;
00193
00194 case 3:
00195 start_time = cpu->getCurrentSimTimeNano();
00196 loop_var_i = 0;
00197 state = 4;
00198 break;
00199 case 4:
00200 if ( loop_var_i < 4 ) {
00201 ptl->PtlTriggeredGet(md_handle,8*512*loop_var_i,8*512,0,0,0,NULL,8*512*loop_var_i,ct_handle,loop_var_i+1);
00202 loop_var_i++;
00203 }
00204 else {
00205 state = 5;
00206 }
00207 break;
00208
00209 case 5:
00210 if ( ptl->PtlCTWait(ct_handle2,4) ) {
00211 int bad = 0;
00212 for ( int i = 0; i < (2*1024); i++ ) {
00213 if ( (int) recv_buffer[i] != i ) bad++;
00214 }
00215 if ( bad ) {
00216 printf("Bad results\n");
00217 }
00218 else {
00219 printf("Good to go\n");
00220 }
00221 uint64_t elapsed_time = cpu->getCurrentSimTimeNano()-start_time;
00222 trig_cpu::addTimeToStats(elapsed_time);
00223 state = 1;
00224 return true;
00225 }
00226 break;
00227
00228
00229 case 6:
00230 start_time = cpu->getCurrentSimTimeNano();
00231 loop_var_i = 0;
00232 state = 7;
00233 break;
00234
00235 case 7:
00236 loop_var_j = 1;
00237 state = 8;
00238 break;
00239
00240 case 8:
00241 if ( loop_var_j < num_nodes ) {
00242 ptl->PtlPut(md_handle,0,0,0,loop_var_j,0,0,0,NULL,0);
00243 loop_var_j++;
00244 }
00245 else {
00246 state = 9;
00247 }
00248 break;
00249
00250 case 9:
00251 if ( loop_var_i < 4 ) {
00252 state = 7;
00253 loop_var_i++;
00254 }
00255 else {
00256
00257 uint64_t elapsed_time = cpu->getCurrentSimTimeNano()-start_time;
00258 trig_cpu::addTimeToStats(elapsed_time);
00259 return true;
00260 }
00261
00262 default:
00263 break;
00264 }
00265 return false;
00266 }
00267
00268 private:
00269 bandwidth();
00270 bandwidth(const application& a);
00271 void operator=(bandwidth const&);
00272
00273 trig_cpu *cpu;
00274 portals *ptl;
00275 ptl_handle_ct_t ct_handle;
00276 ptl_handle_ct_t ct_handle2;
00277 int state;
00278 int my_id;
00279 int num_nodes;
00280
00281 int loop_var_i;
00282 int loop_var_j;
00283
00284 ptl_handle_md_t md_handle;
00285
00286 uint64_t* send_buffer;
00287 uint64_t* recv_buffer;
00288
00289 SimTime_t start_time;
00290
00291 };
00292
00293 #endif // COMPONENTS_TRIG_CPU_TEST_PORTALS_H