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sst/core/techModels/libMcPAT/decoder.h

00001 /*****************************************************************************
00002  *                                McPAT
00003  *                      SOFTWARE LICENSE AGREEMENT
00004  *            Copyright 2009 Hewlett-Packard Development Company, L.P.
00005  *                          All Rights Reserved
00006  *
00007  * Permission to use, copy, and modify this software and its documentation is
00008  * hereby granted only under the following terms and conditions.  Both the
00009  * above copyright notice and this permission notice must appear in all copies
00010  * of the software, derivative works or modified versions, and any portions
00011  * thereof, and both notices must appear in supporting documentation.
00012  *
00013  * Any User of the software ("User"), by accessing and using it, agrees to the
00014  * terms and conditions set forth herein, and hereby grants back to Hewlett-
00015  * Packard Development Company, L.P. and its affiliated companies ("HP") a
00016  * non-exclusive, unrestricted, royalty-free right and license to copy,
00017  * modify, distribute copies, create derivate works and publicly display and
00018  * use, any changes, modifications, enhancements or extensions made to the
00019  * software by User, including but not limited to those affording
00020  * compatibility with other hardware or software, but excluding pre-existing
00021  * software applications that may incorporate the software.  User further
00022  * agrees to use its best efforts to inform HP of any such changes,
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00024  *
00025  * Correspondence should be provided to HP at:
00026  *
00027  * Director of Intellectual Property Licensing
00028  * Office of Strategy and Technology
00029  * Hewlett-Packard Company
00030  * 1501 Page Mill Road
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00032  *
00033  * The software may be further distributed by User (but not offered for
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00037  *
00038  * THE SOFTWARE IS PROVIDED "AS IS" WITH ANY AND ALL ERRORS AND DEFECTS
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00047  ***************************************************************************/
00048 #ifndef __DECODER_H__
00049 #define __DECODER_H__
00050 
00051 #include "area.h"
00052 #include "parameter.h"
00053 #include <vector>
00054 
00055 using namespace std;
00056 
00057 
00058 class Decoder
00059 {
00060  public:
00061   Decoder(int _num_dec_signals, bool _flag_way_select, double _C_ld_dec_out, double _R_wire_dec_out);
00062 
00063   bool   exist;
00064   int    num_in_signals;
00065   double C_ld_dec_out;
00066   double R_wire_dec_out;
00067   int    num_gates;
00068   int    num_gates_min;
00069   double w_dec_n[MAX_NUMBER_GATES_STAGE];
00070   double w_dec_p[MAX_NUMBER_GATES_STAGE];
00071   double delay;
00072   powerDef power;
00073 
00074   Area area;
00075 
00076   void compute_widths(bool fully_assoc, bool is_dram_, bool is_wl_tr_);
00077   void compute_area(const Area & cell, bool is_dram_);
00078   double compute_delays(
00079       double inrisetime,
00080       const  Area & cell,
00081       bool   is_dram,
00082       bool   is_wl_tr);  // return outrisetime
00083 };
00084 
00085 
00086 class PredecoderBlock
00087 {
00088  public:
00089   PredecoderBlock();
00090 
00091   bool exist;
00092   int number_input_addr_bits;
00093   double c_load_predecoder_block_output;
00094   double r_wire_predecoder_block_output;
00095   int branch_effort_nand2_gate_output;
00096   int branch_effort_nand3_gate_output;
00097   int flag_two_unique_paths;
00098   int flag_L2_gate;
00099   int number_inputs_L1_gate;
00100   int number_gates_L1_nand2_path;
00101   int number_gates_L1_nand3_path;
00102   int number_gates_L2;
00103   int min_number_gates_L1;
00104   int min_number_gates_L2;
00105   int number_L1_parallel_instances_nand2;
00106   int number_L1_parallel_instances_nand3;
00107   int number_L2_parallel_instances;
00108   double width_L1_nand2_path_n[MAX_NUMBER_GATES_STAGE];
00109   double width_L1_nand2_path_p[MAX_NUMBER_GATES_STAGE];
00110   double width_L1_nand3_path_n[MAX_NUMBER_GATES_STAGE];
00111   double width_L1_nand3_path_p[MAX_NUMBER_GATES_STAGE];
00112   double width_L2_n[MAX_NUMBER_GATES_STAGE];
00113   double width_L2_p[MAX_NUMBER_GATES_STAGE];
00114   double delay_nand2_path;
00115   double delay_nand3_path;
00116   powerDef power_nand2_path;
00117   powerDef power_nand3_path;
00118   powerDef power_L2;
00119 
00120   Area area;
00121   bool is_dram_;
00122 
00123   void compute_widths();
00124   static void initialize(
00125       int num_dec_signals,
00126       PredecoderBlock & blk1,
00127       PredecoderBlock & blk2,
00128       const Decoder & dec,
00129       double C_wire_predec_blk_out,
00130       double R_wire_predec_blk_out,
00131       int    num_dec_gates_driven_per_predec_out,
00132       bool   is_dram_);
00133   void compute_area();
00134   pair<double, double> compute_delays(pair<double, double> inrisetime); // <nand2, nand3>
00135   // return <outrise_nand2, outrise_nand3>
00136 };
00137 
00138 
00139 class PredecoderBlockDriver
00140 {
00141  public:
00142   PredecoderBlockDriver();
00143 
00144   int flag_driver_exists;
00145   int flag_driving_decoder_output;
00146   int number_input_addr_bits;
00147   int number_gates_nand2_path;
00148   int number_gates_nand3_path;
00149   int min_number_gates;
00150   int number_parallel_instances_driving_1_nand2_load;
00151   int number_parallel_instances_driving_2_nand2_load;
00152   int number_parallel_instances_driving_4_nand2_load;
00153   int number_parallel_instances_driving_2_nand3_load;
00154   int number_parallel_instances_driving_8_nand3_load;
00155   int number_parallel_instances_nand3_path;
00156   double c_load_nand2_path_predecode_block_driver_output;
00157   double c_load_nand3_path_predecode_block_driver_output;
00158   double r_load_nand2_path_predecode_block_driver_output;
00159   double r_load_nand3_path_predecode_block_driver_output;
00160   double width_nand2_path_n[MAX_NUMBER_GATES_STAGE];
00161   double width_nand2_path_p[MAX_NUMBER_GATES_STAGE];
00162   double width_nand3_path_n[MAX_NUMBER_GATES_STAGE];
00163   double width_nand3_path_p[MAX_NUMBER_GATES_STAGE];
00164   double delay_nand2_path;
00165   double delay_nand3_path;
00166   powerDef power_nand2_path;
00167   powerDef power_nand3_path;
00168 
00169   Area area;
00170   bool is_dram_;
00171 
00172   void compute_widths(
00173       const PredecoderBlock & predec_blk,
00174       const Decoder &ptr_dec,
00175       int way_select);
00176   static void initialize(
00177       int num_dec_signals,
00178       int flag_way_select,
00179       int way_select,
00180       PredecoderBlockDriver & blk_drv1,
00181       PredecoderBlockDriver & blk_drv2,
00182       const PredecoderBlock & blk1,
00183       const PredecoderBlock & blk2,
00184       const Decoder & dec,
00185       bool is_dram_);
00186   void compute_area();
00187   pair<double, double> compute_delays(
00188       double inrisetime_nand2_path,
00189       double inrisetime_nand3_path);  // return <outrise_nand2, outrise_nand3>
00190 
00191   inline int num_addr_bits_nand2_path()
00192   {
00193     return number_parallel_instances_driving_1_nand2_load +
00194            number_parallel_instances_driving_2_nand2_load +
00195            number_parallel_instances_driving_4_nand2_load;
00196   }
00197   inline int num_addr_bits_nand3_path()
00198   {
00199     return number_parallel_instances_driving_2_nand3_load +
00200            number_parallel_instances_driving_8_nand3_load;
00201   }
00202   double get_readOp_dynamic_power(int num_act_mats_hor_dir);
00203 };
00204 
00205 
00206 class Driver
00207 {
00208  public:
00209   Driver();
00210 
00211   int    number_gates;
00212   int    min_number_gates;
00213   double width_n[MAX_NUMBER_GATES_STAGE];
00214   double width_p[MAX_NUMBER_GATES_STAGE];
00215   double c_gate_load;
00216   double c_wire_load;
00217   double r_wire_load;
00218   double delay;
00219   powerDef power;
00220 
00221   void   compute_widths(bool is_dram_);
00222   double compute_delay(
00223       double inrisetime,
00224       bool is_dram_);
00225 };
00226 
00227 
00228 #endif

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