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00019 #ifndef __SH7750_REGS_H__
00020 #define __SH7750_REGS_H__
00021
00022
00023
00024
00025
00026 #define SH7750_P4_BASE 0xff000000
00027
00028 #define SH7750_A7_BASE 0x1f000000
00029
00030 #define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs))
00031 #define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs))
00032
00033
00034
00035
00036
00037
00038 #define SH7750_PTEH_REGOFS 0x000000
00039 #define SH7750_PTEH SH7750_P4_REG32(SH7750_PTEH_REGOFS)
00040 #define SH7750_PTEH_A7 SH7750_A7_REG32(SH7750_PTEH_REGOFS)
00041 #define SH7750_PTEH_VPN 0xfffffd00
00042 #define SH7750_PTEH_VPN_S 10
00043 #define SH7750_PTEH_ASID 0x000000ff
00044 #define SH7750_PTEH_ASID_S 0
00045
00046
00047 #define SH7750_PTEL_REGOFS 0x000004
00048 #define SH7750_PTEL SH7750_P4_REG32(SH7750_PTEL_REGOFS)
00049 #define SH7750_PTEL_A7 SH7750_A7_REG32(SH7750_PTEL_REGOFS)
00050 #define SH7750_PTEL_PPN 0x1ffffc00
00051 #define SH7750_PTEL_PPN_S 10
00052 #define SH7750_PTEL_V 0x00000100
00053 #define SH7750_PTEL_SZ1 0x00000080
00054 #define SH7750_PTEL_SZ0 0x00000010
00055 #define SH7750_PTEL_SZ_1KB 0x00000000
00056 #define SH7750_PTEL_SZ_4KB 0x00000010
00057 #define SH7750_PTEL_SZ_64KB 0x00000080
00058 #define SH7750_PTEL_SZ_1MB 0x00000090
00059 #define SH7750_PTEL_PR 0x00000060
00060 #define SH7750_PTEL_PR_ROPO 0x00000000
00061 #define SH7750_PTEL_PR_RWPO 0x00000020
00062 #define SH7750_PTEL_PR_ROPU 0x00000040
00063 #define SH7750_PTEL_PR_RWPU 0x00000060
00064 #define SH7750_PTEL_C 0x00000008
00065
00066 #define SH7750_PTEL_D 0x00000004
00067
00068 #define SH7750_PTEL_SH 0x00000002
00069
00070 #define SH7750_PTEL_WT 0x00000001
00071
00072
00073
00074
00075
00076 #define SH7750_PTEA_REGOFS 0x000034
00077 #define SH7750_PTEA SH7750_P4_REG32(SH7750_PTEA_REGOFS)
00078 #define SH7750_PTEA_A7 SH7750_A7_REG32(SH7750_PTEA_REGOFS)
00079 #define SH7750_PTEA_TC 0x00000008
00080
00081
00082 #define SH7750_PTEA_SA 0x00000007
00083 #define SH7750_PTEA_SA_UNDEF 0x00000000
00084 #define SH7750_PTEA_SA_IOVAR 0x00000001
00085 #define SH7750_PTEA_SA_IO8 0x00000002
00086 #define SH7750_PTEA_SA_IO16 0x00000003
00087 #define SH7750_PTEA_SA_CMEM8 0x00000004
00088 #define SH7750_PTEA_SA_CMEM16 0x00000005
00089 #define SH7750_PTEA_SA_AMEM8 0x00000006
00090 #define SH7750_PTEA_SA_AMEM16 0x00000007
00091
00092
00093
00094 #define SH7750_TTB_REGOFS 0x000008
00095 #define SH7750_TTB SH7750_P4_REG32(SH7750_TTB_REGOFS)
00096 #define SH7750_TTB_A7 SH7750_A7_REG32(SH7750_TTB_REGOFS)
00097
00098
00099 #define SH7750_TEA_REGOFS 0x00000c
00100 #define SH7750_TEA SH7750_P4_REG32(SH7750_TEA_REGOFS)
00101 #define SH7750_TEA_A7 SH7750_A7_REG32(SH7750_TEA_REGOFS)
00102
00103
00104 #define SH7750_MMUCR_REGOFS 0x000010
00105 #define SH7750_MMUCR SH7750_P4_REG32(SH7750_MMUCR_REGOFS)
00106 #define SH7750_MMUCR_A7 SH7750_A7_REG32(SH7750_MMUCR_REGOFS)
00107 #define SH7750_MMUCR_AT 0x00000001
00108 #define SH7750_MMUCR_TI 0x00000004
00109 #define SH7750_MMUCR_SV 0x00000100
00110 #define SH7750_MMUCR_SQMD 0x00000200
00111 #define SH7750_MMUCR_URC 0x0000FC00
00112 #define SH7750_MMUCR_URC_S 10
00113 #define SH7750_MMUCR_URB 0x00FC0000
00114 #define SH7750_MMUCR_URB_S 18
00115 #define SH7750_MMUCR_LRUI 0xFC000000
00116 #define SH7750_MMUCR_LRUI_S 26
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128 #define SH7750_CCR_REGOFS 0x00001c
00129 #define SH7750_CCR SH7750_P4_REG32(SH7750_CCR_REGOFS)
00130 #define SH7750_CCR_A7 SH7750_A7_REG32(SH7750_CCR_REGOFS)
00131
00132 #define SH7750_CCR_IIX 0x00008000
00133 #define SH7750_CCR_ICI 0x00000800
00134
00135 #define SH7750_CCR_ICE 0x00000100
00136 #define SH7750_CCR_OIX 0x00000080
00137 #define SH7750_CCR_ORA 0x00000020
00138
00139
00140 #define SH7750_CCR_OCI 0x00000008
00141 #define SH7750_CCR_CB 0x00000004
00142 #define SH7750_CCR_WT 0x00000002
00143 #define SH7750_CCR_OCE 0x00000001
00144
00145
00146 #define SH7750_QACR0_REGOFS 0x000038
00147 #define SH7750_QACR0 SH7750_P4_REG32(SH7750_QACR0_REGOFS)
00148 #define SH7750_QACR0_A7 SH7750_A7_REG32(SH7750_QACR0_REGOFS)
00149
00150
00151 #define SH7750_QACR1_REGOFS 0x00003c
00152 #define SH7750_QACR1 SH7750_P4_REG32(SH7750_QACR1_REGOFS)
00153 #define SH7750_QACR1_A7 SH7750_A7_REG32(SH7750_QACR1_REGOFS)
00154
00155
00156
00157
00158
00159
00160
00161 #define SH7750_TRA_REGOFS 0x000020
00162 #define SH7750_TRA SH7750_P4_REG32(SH7750_TRA_REGOFS)
00163 #define SH7750_TRA_A7 SH7750_A7_REG32(SH7750_TRA_REGOFS)
00164
00165 #define SH7750_TRA_IMM 0x000003fd
00166 #define SH7750_TRA_IMM_S 2
00167
00168
00169 #define SH7750_EXPEVT_REGOFS 0x000024
00170 #define SH7750_EXPEVT SH7750_P4_REG32(SH7750_EXPEVT_REGOFS)
00171 #define SH7750_EXPEVT_A7 SH7750_A7_REG32(SH7750_EXPEVT_REGOFS)
00172
00173 #define SH7750_EXPEVT_EX 0x00000fff
00174 #define SH7750_EXPEVT_EX_S 0
00175
00176
00177 #define SH7750_INTEVT_REGOFS 0x000028
00178 #define SH7750_INTEVT SH7750_P4_REG32(SH7750_INTEVT_REGOFS)
00179 #define SH7750_INTEVT_A7 SH7750_A7_REG32(SH7750_INTEVT_REGOFS)
00180 #define SH7750_INTEVT_EX 0x00000fff
00181 #define SH7750_INTEVT_EX_S 0
00182
00183
00184
00185
00186 #define SH7750_EVT_TO_NUM(evt) ((evt) >> 5)
00187
00188
00189 #define SH7750_EVT_POWER_ON_RST 0x000
00190 #define SH7750_EVT_MANUAL_RST 0x020
00191 #define SH7750_EVT_TLB_MULT_HIT 0x140
00192
00193
00194 #define SH7750_EVT_USER_BREAK 0x1E0
00195 #define SH7750_EVT_IADDR_ERR 0x0E0
00196 #define SH7750_EVT_TLB_READ_MISS 0x040
00197
00198 #define SH7750_EVT_TLB_READ_PROTV 0x0A0
00199
00200 #define SH7750_EVT_ILLEGAL_INSTR 0x180
00201
00202 #define SH7750_EVT_SLOT_ILLEGAL_INSTR 0x1A0
00203
00204 #define SH7750_EVT_FPU_DISABLE 0x800
00205 #define SH7750_EVT_SLOT_FPU_DISABLE 0x820
00206 #define SH7750_EVT_DATA_READ_ERR 0x0E0
00207 #define SH7750_EVT_DATA_WRITE_ERR 0x100
00208 #define SH7750_EVT_DTLB_WRITE_MISS 0x060
00209 #define SH7750_EVT_DTLB_WRITE_PROTV 0x0C0
00210
00211 #define SH7750_EVT_FPU_EXCEPTION 0x120
00212 #define SH7750_EVT_INITIAL_PGWRITE 0x080
00213 #define SH7750_EVT_TRAPA 0x160
00214
00215
00216 #define SH7750_EVT_NMI 0x1C0
00217 #define SH7750_EVT_IRQ0 0x200
00218 #define SH7750_EVT_IRQ1 0x220
00219 #define SH7750_EVT_IRQ2 0x240
00220 #define SH7750_EVT_IRQ3 0x260
00221 #define SH7750_EVT_IRQ4 0x280
00222 #define SH7750_EVT_IRQ5 0x2A0
00223 #define SH7750_EVT_IRQ6 0x2C0
00224 #define SH7750_EVT_IRQ7 0x2E0
00225 #define SH7750_EVT_IRQ8 0x300
00226 #define SH7750_EVT_IRQ9 0x320
00227 #define SH7750_EVT_IRQA 0x340
00228 #define SH7750_EVT_IRQB 0x360
00229 #define SH7750_EVT_IRQC 0x380
00230 #define SH7750_EVT_IRQD 0x3A0
00231 #define SH7750_EVT_IRQE 0x3C0
00232
00233
00234 #define SH7750_EVT_TUNI0 0x400
00235 #define SH7750_EVT_TUNI1 0x420
00236 #define SH7750_EVT_TUNI2 0x440
00237 #define SH7750_EVT_TICPI2 0x460
00238
00239
00240 #define SH7750_EVT_RTC_ATI 0x480
00241 #define SH7750_EVT_RTC_PRI 0x4A0
00242 #define SH7750_EVT_RTC_CUI 0x4C0
00243
00244
00245 #define SH7750_EVT_SCI_ERI 0x4E0
00246 #define SH7750_EVT_SCI_RXI 0x500
00247 #define SH7750_EVT_SCI_TXI 0x520
00248 #define SH7750_EVT_SCI_TEI 0x540
00249
00250
00251 #define SH7750_EVT_WDT_ITI 0x560
00252
00253
00254
00255
00256 #define SH7750_EVT_REF_RCMI 0x580
00257 #define SH7750_EVT_REF_ROVI 0x5A0
00258
00259
00260
00261 #define SH7750_EVT_HUDI 0x600
00262
00263
00264 #define SH7750_EVT_GPIO 0x620
00265
00266
00267 #define SH7750_EVT_DMAC_DMTE0 0x640
00268 #define SH7750_EVT_DMAC_DMTE1 0x660
00269 #define SH7750_EVT_DMAC_DMTE2 0x680
00270 #define SH7750_EVT_DMAC_DMTE3 0x6A0
00271 #define SH7750_EVT_DMAC_DMAE 0x6C0
00272
00273
00274
00275 #define SH7750_EVT_SCIF_ERI 0x700
00276 #define SH7750_EVT_SCIF_RXI 0x720
00277
00278 #define SH7750_EVT_SCIF_BRI 0x740
00279 #define SH7750_EVT_SCIF_TXI 0x760
00280
00281
00282
00283
00284 #define SH7750_STBCR_REGOFS 0xC00004
00285 #define SH7750_STBCR SH7750_P4_REG32(SH7750_STBCR_REGOFS)
00286 #define SH7750_STBCR_A7 SH7750_A7_REG32(SH7750_STBCR_REGOFS)
00287
00288 #define SH7750_STBCR_STBY 0x80
00289
00290
00291 #define SH7750_STBCR_PHZ 0x40
00292
00293
00294
00295
00296 #define SH7750_STBCR_PPU 0x20
00297 #define SH7750_STBCR_MSTP4 0x10
00298 #define SH7750_STBCR_DMAC_STP SH7750_STBCR_MSTP4
00299 #define SH7750_STBCR_MSTP3 0x08
00300 #define SH7750_STBCR_SCIF_STP SH7750_STBCR_MSTP3
00301 #define SH7750_STBCR_MSTP2 0x04
00302 #define SH7750_STBCR_TMU_STP SH7750_STBCR_MSTP2
00303 #define SH7750_STBCR_MSTP1 0x02
00304 #define SH7750_STBCR_RTC_STP SH7750_STBCR_MSTP1
00305 #define SH7750_STBCR_MSPT0 0x01
00306 #define SH7750_STBCR_SCI_STP SH7750_STBCR_MSTP0
00307
00308 #define SH7750_STBCR_STBY 0x80
00309
00310
00311 #define SH7750_STBCR2_REGOFS 0xC00010
00312 #define SH7750_STBCR2 SH7750_P4_REG32(SH7750_STBCR2_REGOFS)
00313 #define SH7750_STBCR2_A7 SH7750_A7_REG32(SH7750_STBCR2_REGOFS)
00314
00315 #define SH7750_STBCR2_DSLP 0x80
00316
00317
00318
00319
00320 #define SH7750_STBCR2_MSTP6 0x02
00321
00322 #define SH7750_STBCR2_SQ_STP SH7750_STBCR2_MSTP6
00323 #define SH7750_STBCR2_MSTP5 0x01
00324
00325 #define SH7750_STBCR2_UBC_STP SH7750_STBCR2_MSTP5
00326
00327
00328
00329
00330 #define SH7750_FRQCR_REGOFS 0xC00000
00331 #define SH7750_FRQCR SH7750_P4_REG32(SH7750_FRQCR_REGOFS)
00332 #define SH7750_FRQCR_A7 SH7750_A7_REG32(SH7750_FRQCR_REGOFS)
00333
00334 #define SH7750_FRQCR_CKOEN 0x0800
00335
00336
00337 #define SH7750_FRQCR_PLL1EN 0x0400
00338 #define SH7750_FRQCR_PLL2EN 0x0200
00339
00340 #define SH7750_FRQCR_IFC 0x01C0
00341 #define SH7750_FRQCR_IFCDIV1 0x0000
00342 #define SH7750_FRQCR_IFCDIV2 0x0040
00343 #define SH7750_FRQCR_IFCDIV3 0x0080
00344 #define SH7750_FRQCR_IFCDIV4 0x00C0
00345 #define SH7750_FRQCR_IFCDIV6 0x0100
00346 #define SH7750_FRQCR_IFCDIV8 0x0140
00347
00348 #define SH7750_FRQCR_BFC 0x0038
00349 #define SH7750_FRQCR_BFCDIV1 0x0000
00350 #define SH7750_FRQCR_BFCDIV2 0x0008
00351 #define SH7750_FRQCR_BFCDIV3 0x0010
00352 #define SH7750_FRQCR_BFCDIV4 0x0018
00353 #define SH7750_FRQCR_BFCDIV6 0x0020
00354 #define SH7750_FRQCR_BFCDIV8 0x0028
00355
00356 #define SH7750_FRQCR_PFC 0x0007
00357
00358 #define SH7750_FRQCR_PFCDIV2 0x0000
00359 #define SH7750_FRQCR_PFCDIV3 0x0001
00360 #define SH7750_FRQCR_PFCDIV4 0x0002
00361 #define SH7750_FRQCR_PFCDIV6 0x0003
00362 #define SH7750_FRQCR_PFCDIV8 0x0004
00363
00364
00365
00366
00367
00368
00369 #define SH7750_WTCNT_REGOFS 0xC00008
00370 #define SH7750_WTCNT SH7750_P4_REG32(SH7750_WTCNT_REGOFS)
00371 #define SH7750_WTCNT_A7 SH7750_A7_REG32(SH7750_WTCNT_REGOFS)
00372 #define SH7750_WTCNT_KEY 0x5A00
00373
00374
00375
00376
00377 #define SH7750_WTCSR_REGOFS 0xC0000C
00378 #define SH7750_WTCSR SH7750_P4_REG32(SH7750_WTCSR_REGOFS)
00379 #define SH7750_WTCSR_A7 SH7750_A7_REG32(SH7750_WTCSR_REGOFS)
00380 #define SH7750_WTCSR_KEY 0xA500
00381
00382
00383 #define SH7750_WTCSR_TME 0x80
00384 #define SH7750_WTCSR_MODE 0x40
00385 #define SH7750_WTCSR_MODE_WT 0x40
00386 #define SH7750_WTCSR_MODE_IT 0x00
00387 #define SH7750_WTCSR_RSTS 0x20
00388 #define SH7750_WTCSR_RST_MAN 0x20
00389 #define SH7750_WTCSR_RST_PWR 0x00
00390 #define SH7750_WTCSR_WOVF 0x10
00391 #define SH7750_WTCSR_IOVF 0x08
00392 #define SH7750_WTCSR_CKS 0x07
00393 #define SH7750_WTCSR_CKS_DIV32 0x00
00394 #define SH7750_WTCSR_CKS_DIV64 0x01
00395 #define SH7750_WTCSR_CKS_DIV128 0x02
00396 #define SH7750_WTCSR_CKS_DIV256 0x03
00397 #define SH7750_WTCSR_CKS_DIV512 0x04
00398 #define SH7750_WTCSR_CKS_DIV1024 0x05
00399 #define SH7750_WTCSR_CKS_DIV2048 0x06
00400 #define SH7750_WTCSR_CKS_DIV4096 0x07
00401
00402
00403
00404
00405
00406 #define SH7750_R64CNT_REGOFS 0xC80000
00407 #define SH7750_R64CNT SH7750_P4_REG32(SH7750_R64CNT_REGOFS)
00408 #define SH7750_R64CNT_A7 SH7750_A7_REG32(SH7750_R64CNT_REGOFS)
00409
00410
00411 #define SH7750_RSECCNT_REGOFS 0xC80004
00412 #define SH7750_RSECCNT SH7750_P4_REG32(SH7750_RSECCNT_REGOFS)
00413 #define SH7750_RSECCNT_A7 SH7750_A7_REG32(SH7750_RSECCNT_REGOFS)
00414
00415
00416 #define SH7750_RMINCNT_REGOFS 0xC80008
00417 #define SH7750_RMINCNT SH7750_P4_REG32(SH7750_RMINCNT_REGOFS)
00418 #define SH7750_RMINCNT_A7 SH7750_A7_REG32(SH7750_RMINCNT_REGOFS)
00419
00420
00421 #define SH7750_RHRCNT_REGOFS 0xC8000C
00422 #define SH7750_RHRCNT SH7750_P4_REG32(SH7750_RHRCNT_REGOFS)
00423 #define SH7750_RHRCNT_A7 SH7750_A7_REG32(SH7750_RHRCNT_REGOFS)
00424
00425
00426 #define SH7750_RWKCNT_REGOFS 0xC80010
00427 #define SH7750_RWKCNT SH7750_P4_REG32(SH7750_RWKCNT_REGOFS)
00428 #define SH7750_RWKCNT_A7 SH7750_A7_REG32(SH7750_RWKCNT_REGOFS)
00429
00430 #define SH7750_RWKCNT_SUN 0
00431 #define SH7750_RWKCNT_MON 1
00432 #define SH7750_RWKCNT_TUE 2
00433 #define SH7750_RWKCNT_WED 3
00434 #define SH7750_RWKCNT_THU 4
00435 #define SH7750_RWKCNT_FRI 5
00436 #define SH7750_RWKCNT_SAT 6
00437
00438
00439 #define SH7750_RDAYCNT_REGOFS 0xC80014
00440 #define SH7750_RDAYCNT SH7750_P4_REG32(SH7750_RDAYCNT_REGOFS)
00441 #define SH7750_RDAYCNT_A7 SH7750_A7_REG32(SH7750_RDAYCNT_REGOFS)
00442
00443
00444 #define SH7750_RMONCNT_REGOFS 0xC80018
00445 #define SH7750_RMONCNT SH7750_P4_REG32(SH7750_RMONCNT_REGOFS)
00446 #define SH7750_RMONCNT_A7 SH7750_A7_REG32(SH7750_RMONCNT_REGOFS)
00447
00448
00449 #define SH7750_RYRCNT_REGOFS 0xC8001C
00450 #define SH7750_RYRCNT SH7750_P4_REG32(SH7750_RYRCNT_REGOFS)
00451 #define SH7750_RYRCNT_A7 SH7750_A7_REG32(SH7750_RYRCNT_REGOFS)
00452
00453
00454 #define SH7750_RSECAR_REGOFS 0xC80020
00455 #define SH7750_RSECAR SH7750_P4_REG32(SH7750_RSECAR_REGOFS)
00456 #define SH7750_RSECAR_A7 SH7750_A7_REG32(SH7750_RSECAR_REGOFS)
00457 #define SH7750_RSECAR_ENB 0x80
00458
00459
00460 #define SH7750_RMINAR_REGOFS 0xC80024
00461 #define SH7750_RMINAR SH7750_P4_REG32(SH7750_RMINAR_REGOFS)
00462 #define SH7750_RMINAR_A7 SH7750_A7_REG32(SH7750_RMINAR_REGOFS)
00463 #define SH7750_RMINAR_ENB 0x80
00464
00465
00466 #define SH7750_RHRAR_REGOFS 0xC80028
00467 #define SH7750_RHRAR SH7750_P4_REG32(SH7750_RHRAR_REGOFS)
00468 #define SH7750_RHRAR_A7 SH7750_A7_REG32(SH7750_RHRAR_REGOFS)
00469 #define SH7750_RHRAR_ENB 0x80
00470
00471
00472 #define SH7750_RWKAR_REGOFS 0xC8002C
00473 #define SH7750_RWKAR SH7750_P4_REG32(SH7750_RWKAR_REGOFS)
00474 #define SH7750_RWKAR_A7 SH7750_A7_REG32(SH7750_RWKAR_REGOFS)
00475 #define SH7750_RWKAR_ENB 0x80
00476
00477 #define SH7750_RWKAR_SUN 0
00478 #define SH7750_RWKAR_MON 1
00479 #define SH7750_RWKAR_TUE 2
00480 #define SH7750_RWKAR_WED 3
00481 #define SH7750_RWKAR_THU 4
00482 #define SH7750_RWKAR_FRI 5
00483 #define SH7750_RWKAR_SAT 6
00484
00485
00486 #define SH7750_RDAYAR_REGOFS 0xC80030
00487 #define SH7750_RDAYAR SH7750_P4_REG32(SH7750_RDAYAR_REGOFS)
00488 #define SH7750_RDAYAR_A7 SH7750_A7_REG32(SH7750_RDAYAR_REGOFS)
00489 #define SH7750_RDAYAR_ENB 0x80
00490
00491
00492 #define SH7750_RMONAR_REGOFS 0xC80034
00493 #define SH7750_RMONAR SH7750_P4_REG32(SH7750_RMONAR_REGOFS)
00494 #define SH7750_RMONAR_A7 SH7750_A7_REG32(SH7750_RMONAR_REGOFS)
00495 #define SH7750_RMONAR_ENB 0x80
00496
00497
00498 #define SH7750_RCR1_REGOFS 0xC80038
00499 #define SH7750_RCR1 SH7750_P4_REG32(SH7750_RCR1_REGOFS)
00500 #define SH7750_RCR1_A7 SH7750_A7_REG32(SH7750_RCR1_REGOFS)
00501 #define SH7750_RCR1_CF 0x80
00502 #define SH7750_RCR1_CIE 0x10
00503 #define SH7750_RCR1_AIE 0x08
00504 #define SH7750_RCR1_AF 0x01
00505
00506
00507 #define SH7750_RCR2_REGOFS 0xC8003C
00508 #define SH7750_RCR2 SH7750_P4_REG32(SH7750_RCR2_REGOFS)
00509 #define SH7750_RCR2_A7 SH7750_A7_REG32(SH7750_RCR2_REGOFS)
00510 #define SH7750_RCR2_PEF 0x80
00511 #define SH7750_RCR2_PES 0x70
00512 #define SH7750_RCR2_PES_DIS 0x00
00513 #define SH7750_RCR2_PES_DIV256 0x10
00514 #define SH7750_RCR2_PES_DIV64 0x20
00515 #define SH7750_RCR2_PES_DIV16 0x30
00516 #define SH7750_RCR2_PES_DIV4 0x40
00517 #define SH7750_RCR2_PES_DIV2 0x50
00518 #define SH7750_RCR2_PES_x1 0x60
00519 #define SH7750_RCR2_PES_x2 0x70
00520 #define SH7750_RCR2_RTCEN 0x08
00521 #define SH7750_RCR2_ADJ 0x04
00522 #define SH7750_RCR2_RESET 0x02
00523 #define SH7750_RCR2_START 0x01
00524
00525
00526
00527
00528
00529
00530
00531 #define SH7750_BCR1_REGOFS 0x800000
00532 #define SH7750_BCR1 SH7750_P4_REG32(SH7750_BCR1_REGOFS)
00533 #define SH7750_BCR1_A7 SH7750_A7_REG32(SH7750_BCR1_REGOFS)
00534 #define SH7750_BCR1_ENDIAN 0x80000000
00535 #define SH7750_BCR1_MASTER 0x40000000
00536 #define SH7750_BCR1_A0MPX 0x20000000
00537 #define SH7750_BCR1_IPUP 0x02000000
00538
00539
00540
00541 #define SH7750_BCR1_OPUP 0x01000000
00542
00543
00544
00545 #define SH7750_BCR1_A1MBC 0x00200000
00546
00547
00548
00549
00550 #define SH7750_BCR1_A4MBC 0x00100000
00551
00552
00553
00554
00555 #define SH7750_BCR1_BREQEN 0x00080000
00556
00557
00558
00559
00560 #define SH7750_BCR1_PSHR 0x00040000
00561
00562
00563 #define SH7750_BCR1_MEMMPX 0x00020000
00564
00565
00566 #define SH7750_BCR1_HIZMEM 0x00008000
00567
00568
00569
00570
00571
00572 #define SH7750_BCR1_HIZCNT 0x00004000
00573
00574
00575
00576
00577
00578
00579 #define SH7750_BCR1_A0BST 0x00003800
00580 #define SH7750_BCR1_A0BST_SRAM 0x0000
00581 #define SH7750_BCR1_A0BST_ROM4 0x0800
00582
00583 #define SH7750_BCR1_A0BST_ROM8 0x1000
00584
00585 #define SH7750_BCR1_A0BST_ROM16 0x1800
00586
00587 #define SH7750_BCR1_A0BST_ROM32 0x2000
00588
00589
00590 #define SH7750_BCR1_A5BST 0x00000700
00591 #define SH7750_BCR1_A5BST_SRAM 0x0000
00592 #define SH7750_BCR1_A5BST_ROM4 0x0100
00593
00594 #define SH7750_BCR1_A5BST_ROM8 0x0200
00595
00596 #define SH7750_BCR1_A5BST_ROM16 0x0300
00597
00598 #define SH7750_BCR1_A5BST_ROM32 0x0400
00599
00600
00601 #define SH7750_BCR1_A6BST 0x000000E0
00602 #define SH7750_BCR1_A6BST_SRAM 0x0000
00603 #define SH7750_BCR1_A6BST_ROM4 0x0020
00604
00605 #define SH7750_BCR1_A6BST_ROM8 0x0040
00606
00607 #define SH7750_BCR1_A6BST_ROM16 0x0060
00608
00609 #define SH7750_BCR1_A6BST_ROM32 0x0080
00610
00611
00612 #define SH7750_BCR1_DRAMTP 0x001C
00613 #define SH7750_BCR1_DRAMTP_2SRAM_3SRAM 0x0000
00614
00615 #define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM 0x0008
00616
00617 #define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C
00618
00619 #define SH7750_BCR1_DRAMTP_2SRAM_3DRAM 0x0010
00620
00621 #define SH7750_BCR1_DRAMTP_2DRAM_3DRAM 0x0014
00622
00623
00624 #define SH7750_BCR1_A56PCM 0x00000001
00625
00626
00627
00628
00629 #define SH7750_BCR2_REGOFS 0x800004
00630 #define SH7750_BCR2 SH7750_P4_REG32(SH7750_BCR2_REGOFS)
00631 #define SH7750_BCR2_A7 SH7750_A7_REG32(SH7750_BCR2_REGOFS)
00632
00633 #define SH7750_BCR2_A0SZ 0xC000
00634 #define SH7750_BCR2_A0SZ_S 14
00635 #define SH7750_BCR2_A6SZ 0x3000
00636 #define SH7750_BCR2_A6SZ_S 12
00637 #define SH7750_BCR2_A5SZ 0x0C00
00638 #define SH7750_BCR2_A5SZ_S 10
00639 #define SH7750_BCR2_A4SZ 0x0300
00640 #define SH7750_BCR2_A4SZ_S 8
00641 #define SH7750_BCR2_A3SZ 0x00C0
00642 #define SH7750_BCR2_A3SZ_S 6
00643 #define SH7750_BCR2_A2SZ 0x0030
00644 #define SH7750_BCR2_A2SZ_S 4
00645 #define SH7750_BCR2_A1SZ 0x000C
00646 #define SH7750_BCR2_A1SZ_S 2
00647 #define SH7750_BCR2_SZ_64 0
00648 #define SH7750_BCR2_SZ_8 1
00649 #define SH7750_BCR2_SZ_16 2
00650 #define SH7750_BCR2_SZ_32 3
00651 #define SH7750_BCR2_PORTEN 0x0001
00652
00653
00654
00655
00656 #define SH7750_WCR1_REGOFS 0x800008
00657 #define SH7750_WCR1 SH7750_P4_REG32(SH7750_WCR1_REGOFS)
00658 #define SH7750_WCR1_A7 SH7750_A7_REG32(SH7750_WCR1_REGOFS)
00659 #define SH7750_WCR1_DMAIW 0x70000000
00660
00661 #define SH7750_WCR1_DMAIW_S 28
00662 #define SH7750_WCR1_A6IW 0x07000000
00663 #define SH7750_WCR1_A6IW_S 24
00664 #define SH7750_WCR1_A5IW 0x00700000
00665 #define SH7750_WCR1_A5IW_S 20
00666 #define SH7750_WCR1_A4IW 0x00070000
00667 #define SH7750_WCR1_A4IW_S 16
00668 #define SH7750_WCR1_A3IW 0x00007000
00669 #define SH7750_WCR1_A3IW_S 12
00670 #define SH7750_WCR1_A2IW 0x00000700
00671 #define SH7750_WCR1_A2IW_S 8
00672 #define SH7750_WCR1_A1IW 0x00000070
00673 #define SH7750_WCR1_A1IW_S 4
00674 #define SH7750_WCR1_A0IW 0x00000007
00675 #define SH7750_WCR1_A0IW_S 0
00676
00677
00678 #define SH7750_WCR2_REGOFS 0x80000C
00679 #define SH7750_WCR2 SH7750_P4_REG32(SH7750_WCR2_REGOFS)
00680 #define SH7750_WCR2_A7 SH7750_A7_REG32(SH7750_WCR2_REGOFS)
00681
00682 #define SH7750_WCR2_A6W 0xE0000000
00683 #define SH7750_WCR2_A6W_S 29
00684 #define SH7750_WCR2_A6B 0x1C000000
00685 #define SH7750_WCR2_A6B_S 26
00686 #define SH7750_WCR2_A5W 0x03800000
00687 #define SH7750_WCR2_A5W_S 23
00688 #define SH7750_WCR2_A5B 0x00700000
00689 #define SH7750_WCR2_A5B_S 20
00690 #define SH7750_WCR2_A4W 0x000E0000
00691 #define SH7750_WCR2_A4W_S 17
00692 #define SH7750_WCR2_A3W 0x0000E000
00693 #define SH7750_WCR2_A3W_S 13
00694 #define SH7750_WCR2_A2W 0x00000E00
00695 #define SH7750_WCR2_A2W_S 9
00696 #define SH7750_WCR2_A1W 0x000001C0
00697 #define SH7750_WCR2_A1W_S 6
00698 #define SH7750_WCR2_A0W 0x00000038
00699 #define SH7750_WCR2_A0W_S 3
00700 #define SH7750_WCR2_A0B 0x00000007
00701 #define SH7750_WCR2_A0B_S 0
00702
00703 #define SH7750_WCR2_WS0 0
00704 #define SH7750_WCR2_WS1 1
00705 #define SH7750_WCR2_WS2 2
00706 #define SH7750_WCR2_WS3 3
00707 #define SH7750_WCR2_WS6 4
00708 #define SH7750_WCR2_WS9 5
00709 #define SH7750_WCR2_WS12 6
00710 #define SH7750_WCR2_WS15 7
00711
00712 #define SH7750_WCR2_BPWS0 0
00713 #define SH7750_WCR2_BPWS1 1
00714 #define SH7750_WCR2_BPWS2 2
00715 #define SH7750_WCR2_BPWS3 3
00716 #define SH7750_WCR2_BPWS4 4
00717 #define SH7750_WCR2_BPWS5 5
00718 #define SH7750_WCR2_BPWS6 6
00719 #define SH7750_WCR2_BPWS7 7
00720
00721
00722 #define SH7750_WCR2_DRAM_CAS_ASW1 0
00723 #define SH7750_WCR2_DRAM_CAS_ASW2 1
00724 #define SH7750_WCR2_DRAM_CAS_ASW3 2
00725 #define SH7750_WCR2_DRAM_CAS_ASW4 3
00726 #define SH7750_WCR2_DRAM_CAS_ASW7 4
00727 #define SH7750_WCR2_DRAM_CAS_ASW10 5
00728 #define SH7750_WCR2_DRAM_CAS_ASW13 6
00729 #define SH7750_WCR2_DRAM_CAS_ASW16 7
00730
00731
00732 #define SH7750_WCR2_SDRAM_CAS_LAT1 1
00733 #define SH7750_WCR2_SDRAM_CAS_LAT2 2
00734 #define SH7750_WCR2_SDRAM_CAS_LAT3 3
00735 #define SH7750_WCR2_SDRAM_CAS_LAT4 4
00736 #define SH7750_WCR2_SDRAM_CAS_LAT5 5
00737
00738
00739 #define SH7750_WCR3_REGOFS 0x800010
00740 #define SH7750_WCR3 SH7750_P4_REG32(SH7750_WCR3_REGOFS)
00741 #define SH7750_WCR3_A7 SH7750_A7_REG32(SH7750_WCR3_REGOFS)
00742
00743 #define SH7750_WCR3_A6S 0x04000000
00744 #define SH7750_WCR3_A6H 0x03000000
00745 #define SH7750_WCR3_A6H_S 24
00746 #define SH7750_WCR3_A5S 0x00400000
00747 #define SH7750_WCR3_A5H 0x00300000
00748 #define SH7750_WCR3_A5H_S 20
00749 #define SH7750_WCR3_A4S 0x00040000
00750 #define SH7750_WCR3_A4H 0x00030000
00751 #define SH7750_WCR3_A4H_S 16
00752 #define SH7750_WCR3_A3S 0x00004000
00753 #define SH7750_WCR3_A3H 0x00003000
00754 #define SH7750_WCR3_A3H_S 12
00755 #define SH7750_WCR3_A2S 0x00000400
00756 #define SH7750_WCR3_A2H 0x00000300
00757 #define SH7750_WCR3_A2H_S 8
00758 #define SH7750_WCR3_A1S 0x00000040
00759 #define SH7750_WCR3_A1H 0x00000030
00760 #define SH7750_WCR3_A1H_S 4
00761 #define SH7750_WCR3_A0S 0x00000004
00762 #define SH7750_WCR3_A0H 0x00000003
00763 #define SH7750_WCR3_A0H_S 0
00764
00765 #define SH7750_WCR3_DHWS_0 0
00766 #define SH7750_WCR3_DHWS_1 1
00767 #define SH7750_WCR3_DHWS_2 2
00768 #define SH7750_WCR3_DHWS_3 3
00769
00770 #define SH7750_MCR_REGOFS 0x800014
00771 #define SH7750_MCR SH7750_P4_REG32(SH7750_MCR_REGOFS)
00772 #define SH7750_MCR_A7 SH7750_A7_REG32(SH7750_MCR_REGOFS)
00773
00774 #define SH7750_MCR_RASD 0x80000000
00775 #define SH7750_MCR_MRSET 0x40000000
00776 #define SH7750_MCR_PALL 0x00000000
00777 #define SH7750_MCR_TRC 0x38000000
00778
00779 #define SH7750_MCR_TRC_0 0x00000000
00780 #define SH7750_MCR_TRC_3 0x08000000
00781 #define SH7750_MCR_TRC_6 0x10000000
00782 #define SH7750_MCR_TRC_9 0x18000000
00783 #define SH7750_MCR_TRC_12 0x20000000
00784 #define SH7750_MCR_TRC_15 0x28000000
00785 #define SH7750_MCR_TRC_18 0x30000000
00786 #define SH7750_MCR_TRC_21 0x38000000
00787
00788 #define SH7750_MCR_TCAS 0x00800000
00789 #define SH7750_MCR_TCAS_1 0x00000000
00790 #define SH7750_MCR_TCAS_2 0x00800000
00791
00792 #define SH7750_MCR_TPC 0x00380000
00793
00794
00795
00796 #define SH7750_MCR_TPC_S 19
00797 #define SH7750_MCR_TPC_SDRAM_1 0x00000000
00798 #define SH7750_MCR_TPC_SDRAM_2 0x00080000
00799 #define SH7750_MCR_TPC_SDRAM_3 0x00100000
00800 #define SH7750_MCR_TPC_SDRAM_4 0x00180000
00801 #define SH7750_MCR_TPC_SDRAM_5 0x00200000
00802 #define SH7750_MCR_TPC_SDRAM_6 0x00280000
00803 #define SH7750_MCR_TPC_SDRAM_7 0x00300000
00804 #define SH7750_MCR_TPC_SDRAM_8 0x00380000
00805
00806 #define SH7750_MCR_RCD 0x00030000
00807
00808
00809 #define SH7750_MCR_RCD_DRAM_2 0x00000000
00810 #define SH7750_MCR_RCD_DRAM_3 0x00010000
00811 #define SH7750_MCR_RCD_DRAM_4 0x00020000
00812 #define SH7750_MCR_RCD_DRAM_5 0x00030000
00813 #define SH7750_MCR_RCD_SDRAM_2 0x00010000
00814 #define SH7750_MCR_RCD_SDRAM_3 0x00020000
00815 #define SH7750_MCR_RCD_SDRAM_4 0x00030000
00816
00817 #define SH7750_MCR_TRWL 0x0000E000
00818 #define SH7750_MCR_TRWL_1 0x00000000
00819 #define SH7750_MCR_TRWL_2 0x00002000
00820 #define SH7750_MCR_TRWL_3 0x00004000
00821 #define SH7750_MCR_TRWL_4 0x00006000
00822 #define SH7750_MCR_TRWL_5 0x00008000
00823
00824 #define SH7750_MCR_TRAS 0x00001C00
00825
00826
00827
00828 #define SH7750_MCR_TRAS_DRAM_2 0x00000000
00829 #define SH7750_MCR_TRAS_DRAM_3 0x00000400
00830 #define SH7750_MCR_TRAS_DRAM_4 0x00000800
00831 #define SH7750_MCR_TRAS_DRAM_5 0x00000C00
00832 #define SH7750_MCR_TRAS_DRAM_6 0x00001000
00833 #define SH7750_MCR_TRAS_DRAM_7 0x00001400
00834 #define SH7750_MCR_TRAS_DRAM_8 0x00001800
00835 #define SH7750_MCR_TRAS_DRAM_9 0x00001C00
00836
00837 #define SH7750_MCR_TRAS_SDRAM_TRC_4 0x00000000
00838 #define SH7750_MCR_TRAS_SDRAM_TRC_5 0x00000400
00839 #define SH7750_MCR_TRAS_SDRAM_TRC_6 0x00000800
00840 #define SH7750_MCR_TRAS_SDRAM_TRC_7 0x00000C00
00841 #define SH7750_MCR_TRAS_SDRAM_TRC_8 0x00001000
00842 #define SH7750_MCR_TRAS_SDRAM_TRC_9 0x00001400
00843 #define SH7750_MCR_TRAS_SDRAM_TRC_10 0x00001800
00844 #define SH7750_MCR_TRAS_SDRAM_TRC_11 0x00001C00
00845
00846 #define SH7750_MCR_BE 0x00000200
00847 #define SH7750_MCR_SZ 0x00000180
00848 #define SH7750_MCR_SZ_64 0x00000000
00849 #define SH7750_MCR_SZ_16 0x00000100
00850 #define SH7750_MCR_SZ_32 0x00000180
00851
00852 #define SH7750_MCR_AMX 0x00000078
00853 #define SH7750_MCR_AMX_S 3
00854 #define SH7750_MCR_AMX_DRAM_8BIT_COL 0x00000000
00855 #define SH7750_MCR_AMX_DRAM_9BIT_COL 0x00000008
00856 #define SH7750_MCR_AMX_DRAM_10BIT_COL 0x00000010
00857 #define SH7750_MCR_AMX_DRAM_11BIT_COL 0x00000018
00858 #define SH7750_MCR_AMX_DRAM_12BIT_COL 0x00000020
00859
00860
00861 #define SH7750_MCR_RFSH 0x00000004
00862 #define SH7750_MCR_RMODE 0x00000002
00863 #define SH7750_MCR_RMODE_NORMAL 0x00000000
00864 #define SH7750_MCR_RMODE_SELF 0x00000002
00865 #define SH7750_MCR_RMODE_EDO 0x00000001
00866
00867
00868 #define SH7750_SDRAM_MODE_A2_BASE 0xFF900000
00869 #define SH7750_SDRAM_MODE_A3_BASE 0xFF940000
00870 #define SH7750_SDRAM_MODE_A2_32BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 2))
00871 #define SH7750_SDRAM_MODE_A3_32BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 2))
00872 #define SH7750_SDRAM_MODE_A2_64BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 3))
00873 #define SH7750_SDRAM_MODE_A3_64BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 3))
00874
00875
00876
00877 #define SH7750_PCR_REGOFS 0x800018
00878 #define SH7750_PCR SH7750_P4_REG32(SH7750_PCR_REGOFS)
00879 #define SH7750_PCR_A7 SH7750_A7_REG32(SH7750_PCR_REGOFS)
00880
00881 #define SH7750_PCR_A5PCW 0xC000
00882
00883
00884
00885 #define SH7750_PCR_A5PCW_0 0x0000
00886 #define SH7750_PCR_A5PCW_15 0x4000
00887 #define SH7750_PCR_A5PCW_30 0x8000
00888 #define SH7750_PCR_A5PCW_50 0xC000
00889
00890 #define SH7750_PCR_A6PCW 0x3000
00891
00892
00893
00894 #define SH7750_PCR_A6PCW_0 0x0000
00895 #define SH7750_PCR_A6PCW_15 0x1000
00896 #define SH7750_PCR_A6PCW_30 0x2000
00897 #define SH7750_PCR_A6PCW_50 0x3000
00898
00899 #define SH7750_PCR_A5TED 0x0E00
00900
00901
00902
00903 #define SH7750_PCR_A5TED_S 9
00904 #define SH7750_PCR_A6TED 0x01C0
00905 #define SH7750_PCR_A6TED_S 6
00906
00907 #define SH7750_PCR_TED_0WS 0
00908 #define SH7750_PCR_TED_1WS 1
00909 #define SH7750_PCR_TED_2WS 2
00910 #define SH7750_PCR_TED_3WS 3
00911 #define SH7750_PCR_TED_6WS 4
00912 #define SH7750_PCR_TED_9WS 5
00913 #define SH7750_PCR_TED_12WS 6
00914 #define SH7750_PCR_TED_15WS 7
00915
00916 #define SH7750_PCR_A5TEH 0x0038
00917
00918
00919
00920 #define SH7750_PCR_A5TEH_S 3
00921
00922 #define SH7750_PCR_A6TEH 0x0007
00923 #define SH7750_PCR_A6TEH_S 0
00924
00925 #define SH7750_PCR_TEH_0WS 0
00926 #define SH7750_PCR_TEH_1WS 1
00927 #define SH7750_PCR_TEH_2WS 2
00928 #define SH7750_PCR_TEH_3WS 3
00929 #define SH7750_PCR_TEH_6WS 4
00930 #define SH7750_PCR_TEH_9WS 5
00931 #define SH7750_PCR_TEH_12WS 6
00932 #define SH7750_PCR_TEH_15WS 7
00933
00934
00935 #define SH7750_RTCSR_REGOFS 0x80001C
00936 #define SH7750_RTCSR SH7750_P4_REG32(SH7750_RTCSR_REGOFS)
00937 #define SH7750_RTCSR_A7 SH7750_A7_REG32(SH7750_RTCSR_REGOFS)
00938
00939 #define SH7750_RTCSR_KEY 0xA500
00940 #define SH7750_RTCSR_CMF 0x0080
00941
00942
00943 #define SH7750_RTCSR_CMIE 0x0040
00944 #define SH7750_RTCSR_CKS 0x0038
00945 #define SH7750_RTCSR_CKS_DIS 0x0000
00946 #define SH7750_RTCSR_CKS_CKIO_DIV4 0x0008
00947 #define SH7750_RTCSR_CKS_CKIO_DIV16 0x0010
00948 #define SH7750_RTCSR_CKS_CKIO_DIV64 0x0018
00949 #define SH7750_RTCSR_CKS_CKIO_DIV256 0x0020
00950 #define SH7750_RTCSR_CKS_CKIO_DIV1024 0x0028
00951 #define SH7750_RTCSR_CKS_CKIO_DIV2048 0x0030
00952 #define SH7750_RTCSR_CKS_CKIO_DIV4096 0x0038
00953
00954 #define SH7750_RTCSR_OVF 0x0004
00955 #define SH7750_RTCSR_OVIE 0x0002
00956
00957 #define SH7750_RTCSR_LMTS 0x0001
00958 #define SH7750_RTCSR_LMTS_1024 0x0000
00959 #define SH7750_RTCSR_LMTS_512 0x0001
00960
00961
00962 #define SH7750_RTCNT_REGOFS 0x800020
00963 #define SH7750_RTCNT SH7750_P4_REG32(SH7750_RTCNT_REGOFS)
00964 #define SH7750_RTCNT_A7 SH7750_A7_REG32(SH7750_RTCNT_REGOFS)
00965
00966 #define SH7750_RTCNT_KEY 0xA500
00967
00968
00969 #define SH7750_RTCOR_REGOFS 0x800024
00970 #define SH7750_RTCOR SH7750_P4_REG32(SH7750_RTCOR_REGOFS)
00971 #define SH7750_RTCOR_A7 SH7750_A7_REG32(SH7750_RTCOR_REGOFS)
00972
00973 #define SH7750_RTCOR_KEY 0xA500
00974
00975
00976 #define SH7750_RFCR_REGOFS 0x800028
00977 #define SH7750_RFCR SH7750_P4_REG32(SH7750_RFCR_REGOFS)
00978 #define SH7750_RFCR_A7 SH7750_A7_REG32(SH7750_RFCR_REGOFS)
00979
00980 #define SH7750_RFCR_KEY 0xA400
00981
00982
00983 #define SH7750_SDMR2_REGOFS 0x900000
00984 #define SH7750_SDMR2_REGNB 0x0FFC
00985 #define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS)
00986 #define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS)
00987
00988 #define SH7750_SDMR3_REGOFS 0x940000
00989 #define SH7750_SDMR3_REGNB 0x0FFC
00990 #define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS)
00991 #define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS)
00992
00993
00994
00995
00996
00997
00998 #define SH7750_SAR_REGOFS(n) (0xA00000 + ((n)*16))
00999 #define SH7750_SAR(n) SH7750_P4_REG32(SH7750_SAR_REGOFS(n))
01000 #define SH7750_SAR_A7(n) SH7750_A7_REG32(SH7750_SAR_REGOFS(n))
01001 #define SH7750_SAR0 SH7750_SAR(0)
01002 #define SH7750_SAR1 SH7750_SAR(1)
01003 #define SH7750_SAR2 SH7750_SAR(2)
01004 #define SH7750_SAR3 SH7750_SAR(3)
01005 #define SH7750_SAR0_A7 SH7750_SAR_A7(0)
01006 #define SH7750_SAR1_A7 SH7750_SAR_A7(1)
01007 #define SH7750_SAR2_A7 SH7750_SAR_A7(2)
01008 #define SH7750_SAR3_A7 SH7750_SAR_A7(3)
01009
01010
01011 #define SH7750_DAR_REGOFS(n) (0xA00004 + ((n)*16))
01012 #define SH7750_DAR(n) SH7750_P4_REG32(SH7750_DAR_REGOFS(n))
01013 #define SH7750_DAR_A7(n) SH7750_A7_REG32(SH7750_DAR_REGOFS(n))
01014 #define SH7750_DAR0 SH7750_DAR(0)
01015 #define SH7750_DAR1 SH7750_DAR(1)
01016 #define SH7750_DAR2 SH7750_DAR(2)
01017 #define SH7750_DAR3 SH7750_DAR(3)
01018 #define SH7750_DAR0_A7 SH7750_DAR_A7(0)
01019 #define SH7750_DAR1_A7 SH7750_DAR_A7(1)
01020 #define SH7750_DAR2_A7 SH7750_DAR_A7(2)
01021 #define SH7750_DAR3_A7 SH7750_DAR_A7(3)
01022
01023
01024 #define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n)*16))
01025 #define SH7750_DMATCR(n) SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n))
01026 #define SH7750_DMATCR_A7(n) SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n))
01027 #define SH7750_DMATCR0_P4 SH7750_DMATCR(0)
01028 #define SH7750_DMATCR1_P4 SH7750_DMATCR(1)
01029 #define SH7750_DMATCR2_P4 SH7750_DMATCR(2)
01030 #define SH7750_DMATCR3_P4 SH7750_DMATCR(3)
01031 #define SH7750_DMATCR0_A7 SH7750_DMATCR_A7(0)
01032 #define SH7750_DMATCR1_A7 SH7750_DMATCR_A7(1)
01033 #define SH7750_DMATCR2_A7 SH7750_DMATCR_A7(2)
01034 #define SH7750_DMATCR3_A7 SH7750_DMATCR_A7(3)
01035
01036
01037 #define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n)*16))
01038 #define SH7750_CHCR(n) SH7750_P4_REG32(SH7750_CHCR_REGOFS(n))
01039 #define SH7750_CHCR_A7(n) SH7750_A7_REG32(SH7750_CHCR_REGOFS(n))
01040 #define SH7750_CHCR0 SH7750_CHCR(0)
01041 #define SH7750_CHCR1 SH7750_CHCR(1)
01042 #define SH7750_CHCR2 SH7750_CHCR(2)
01043 #define SH7750_CHCR3 SH7750_CHCR(3)
01044 #define SH7750_CHCR0_A7 SH7750_CHCR_A7(0)
01045 #define SH7750_CHCR1_A7 SH7750_CHCR_A7(1)
01046 #define SH7750_CHCR2_A7 SH7750_CHCR_A7(2)
01047 #define SH7750_CHCR3_A7 SH7750_CHCR_A7(3)
01048
01049 #define SH7750_CHCR_SSA 0xE0000000
01050 #define SH7750_CHCR_SSA_PCMCIA 0x00000000
01051 #define SH7750_CHCR_SSA_DYNBSZ 0x20000000
01052 #define SH7750_CHCR_SSA_IO8 0x40000000
01053 #define SH7750_CHCR_SSA_IO16 0x60000000
01054 #define SH7750_CHCR_SSA_CMEM8 0x80000000
01055 #define SH7750_CHCR_SSA_CMEM16 0xA0000000
01056 #define SH7750_CHCR_SSA_AMEM8 0xC0000000
01057 #define SH7750_CHCR_SSA_AMEM16 0xE0000000
01058
01059 #define SH7750_CHCR_STC 0x10000000
01060
01061
01062
01063 #define SH7750_CHCR_DSA 0x0E000000
01064 #define SH7750_CHCR_DSA_PCMCIA 0x00000000
01065 #define SH7750_CHCR_DSA_DYNBSZ 0x02000000
01066 #define SH7750_CHCR_DSA_IO8 0x04000000
01067 #define SH7750_CHCR_DSA_IO16 0x06000000
01068 #define SH7750_CHCR_DSA_CMEM8 0x08000000
01069 #define SH7750_CHCR_DSA_CMEM16 0x0A000000
01070 #define SH7750_CHCR_DSA_AMEM8 0x0C000000
01071 #define SH7750_CHCR_DSA_AMEM16 0x0E000000
01072
01073 #define SH7750_CHCR_DTC 0x01000000
01074
01075
01076
01077
01078 #define SH7750_CHCR_DS 0x00080000
01079 #define SH7750_CHCR_DS_LOWLVL 0x00000000
01080 #define SH7750_CHCR_DS_FALL 0x00080000
01081
01082 #define SH7750_CHCR_RL 0x00040000
01083 #define SH7750_CHCR_RL_ACTH 0x00000000
01084 #define SH7750_CHCR_RL_ACTL 0x00040000
01085
01086 #define SH7750_CHCR_AM 0x00020000
01087 #define SH7750_CHCR_AM_RD 0x00000000
01088 #define SH7750_CHCR_AM_WR 0x00020000
01089
01090 #define SH7750_CHCR_AL 0x00010000
01091 #define SH7750_CHCR_AL_ACTH 0x00000000
01092 #define SH7750_CHCR_AL_ACTL 0x00010000
01093
01094 #define SH7750_CHCR_DM 0x0000C000
01095 #define SH7750_CHCR_DM_FIX 0x00000000
01096 #define SH7750_CHCR_DM_INC 0x00004000
01097 #define SH7750_CHCR_DM_DEC 0x00008000
01098
01099 #define SH7750_CHCR_SM 0x00003000
01100 #define SH7750_CHCR_SM_FIX 0x00000000
01101 #define SH7750_CHCR_SM_INC 0x00001000
01102 #define SH7750_CHCR_SM_DEC 0x00002000
01103
01104 #define SH7750_CHCR_RS 0x00000F00
01105 #define SH7750_CHCR_RS_ER_DA_EA_TO_EA 0x000
01106
01107
01108 #define SH7750_CHCR_RS_ER_SA_EA_TO_ED 0x200
01109
01110
01111 #define SH7750_CHCR_RS_ER_SA_ED_TO_EA 0x300
01112
01113
01114
01115 #define SH7750_CHCR_RS_AR_EA_TO_EA 0x400
01116
01117
01118 #define SH7750_CHCR_RS_AR_EA_TO_OCP 0x500
01119
01120
01121 #define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600
01122
01123
01124 #define SH7750_CHCR_RS_SCITX_EA_TO_SC 0x800
01125
01126
01127 #define SH7750_CHCR_RS_SCIRX_SC_TO_EA 0x900
01128
01129
01130 #define SH7750_CHCR_RS_SCIFTX_EA_TO_SC 0xA00
01131
01132
01133 #define SH7750_CHCR_RS_SCIFRX_SC_TO_EA 0xB00
01134
01135
01136 #define SH7750_CHCR_RS_TMU2_EA_TO_EA 0xC00
01137
01138
01139
01140 #define SH7750_CHCR_RS_TMU2_EA_TO_OCP 0xD00
01141
01142
01143
01144 #define SH7750_CHCR_RS_TMU2_OCP_TO_EA 0xE00
01145
01146
01147
01148
01149 #define SH7750_CHCR_TM 0x00000080
01150 #define SH7750_CHCR_TM_CSTEAL 0x00000000
01151 #define SH7750_CHCR_TM_BURST 0x00000080
01152
01153 #define SH7750_CHCR_TS 0x00000070
01154 #define SH7750_CHCR_TS_QUAD 0x00000000
01155 #define SH7750_CHCR_TS_BYTE 0x00000010
01156 #define SH7750_CHCR_TS_WORD 0x00000020
01157 #define SH7750_CHCR_TS_LONG 0x00000030
01158 #define SH7750_CHCR_TS_BLOCK 0x00000040
01159
01160 #define SH7750_CHCR_IE 0x00000004
01161 #define SH7750_CHCR_TE 0x00000002
01162 #define SH7750_CHCR_DE 0x00000001
01163
01164
01165 #define SH7750_DMAOR_REGOFS 0xA00040
01166 #define SH7750_DMAOR SH7750_P4_REG32(SH7750_DMAOR_REGOFS)
01167 #define SH7750_DMAOR_A7 SH7750_A7_REG32(SH7750_DMAOR_REGOFS)
01168
01169 #define SH7750_DMAOR_DDT 0x00008000
01170
01171 #define SH7750_DMAOR_PR 0x00000300
01172 #define SH7750_DMAOR_PR_0123 0x00000000
01173 #define SH7750_DMAOR_PR_0231 0x00000100
01174 #define SH7750_DMAOR_PR_2013 0x00000200
01175 #define SH7750_DMAOR_PR_RR 0x00000300
01176
01177 #define SH7750_DMAOR_COD 0x00000010
01178 #define SH7750_DMAOR_AE 0x00000004
01179 #define SH7750_DMAOR_NMIF 0x00000002
01180 #define SH7750_DMAOR_DME 0x00000001
01181
01182
01183
01184
01185
01186 #define SH7750_PCTRA_REGOFS 0x80002C
01187 #define SH7750_PCTRA SH7750_P4_REG32(SH7750_PCTRA_REGOFS)
01188 #define SH7750_PCTRA_A7 SH7750_A7_REG32(SH7750_PCTRA_REGOFS)
01189
01190 #define SH7750_PCTRA_PBPUP(n) 0
01191 #define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1))
01192 #define SH7750_PCTRA_PBINP(n) 0
01193 #define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2))
01194
01195
01196 #define SH7750_PDTRA_REGOFS 0x800030
01197 #define SH7750_PDTRA SH7750_P4_REG32(SH7750_PDTRA_REGOFS)
01198 #define SH7750_PDTRA_A7 SH7750_A7_REG32(SH7750_PDTRA_REGOFS)
01199
01200 #define SH7750_PDTRA_BIT(n) (1 << (n))
01201
01202
01203 #define SH7750_PCTRB_REGOFS 0x800040
01204 #define SH7750_PCTRB SH7750_P4_REG32(SH7750_PCTRB_REGOFS)
01205 #define SH7750_PCTRB_A7 SH7750_A7_REG32(SH7750_PCTRB_REGOFS)
01206
01207 #define SH7750_PCTRB_PBPUP(n) 0
01208 #define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1))
01209 #define SH7750_PCTRB_PBINP(n) 0
01210 #define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2))
01211
01212
01213 #define SH7750_PDTRB_REGOFS 0x800044
01214 #define SH7750_PDTRB SH7750_P4_REG32(SH7750_PDTRB_REGOFS)
01215 #define SH7750_PDTRB_A7 SH7750_A7_REG32(SH7750_PDTRB_REGOFS)
01216
01217 #define SH7750_PDTRB_BIT(n) (1 << ((n)-16))
01218
01219
01220 #define SH7750_GPIOIC_REGOFS 0x800048
01221 #define SH7750_GPIOIC SH7750_P4_REG32(SH7750_GPIOIC_REGOFS)
01222 #define SH7750_GPIOIC_A7 SH7750_A7_REG32(SH7750_GPIOIC_REGOFS)
01223
01224 #define SH7750_GPIOIC_PTIREN(n) (1 << (n))
01225
01226
01227
01228
01229
01230 #define SH7750_ICR_REGOFS 0xD00000
01231 #define SH7750_ICR SH7750_P4_REG32(SH7750_ICR_REGOFS)
01232 #define SH7750_ICR_A7 SH7750_A7_REG32(SH7750_ICR_REGOFS)
01233
01234 #define SH7750_ICR_NMIL 0x8000
01235 #define SH7750_ICR_MAI 0x4000
01236
01237 #define SH7750_ICR_NMIB 0x0200
01238 #define SH7750_ICR_NMIB_BLK 0x0000
01239
01240 #define SH7750_ICR_NMIB_NBLK 0x0200
01241
01242
01243 #define SH7750_ICR_NMIE 0x0100
01244 #define SH7750_ICR_NMIE_FALL 0x0000
01245
01246 #define SH7750_ICR_NMIE_RISE 0x0100
01247
01248
01249 #define SH7750_ICR_IRLM 0x0080
01250 #define SH7750_ICR_IRLM_ENC 0x0000
01251
01252 #define SH7750_ICR_IRLM_RAW 0x0080
01253
01254
01255
01256
01257
01258 #define SH7750_BARA 0x200000
01259 #define SH7750_BAMRA 0x200004
01260 #define SH7750_BBRA 0x200008
01261 #define SH7750_BARB 0x20000c
01262 #define SH7750_BAMRB 0x200010
01263 #define SH7750_BBRB 0x200014
01264 #define SH7750_BASRB 0x000018
01265 #define SH7750_BDRB 0x200018
01266 #define SH7750_BDMRB 0x20001c
01267 #define SH7750_BRCR 0x200020
01268
01269 #define SH7750_BRCR_UDBE 0x0001
01270
01271
01272
01273
01274 #define SH7750_BCR3_A7 0x1f800050
01275 #define SH7750_BCR4_A7 0x1e0a00f0
01276
01277 #endif