00001 // Copyright 2009-2010 Sandia Corporation. Under the terms 00002 // of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S. 00003 // Government retains certain rights in this software. 00004 // 00005 // Copyright (c) 2009-2010, Sandia Corporation 00006 // All rights reserved. 00007 // 00008 // This file is part of the SST software package. For license 00009 // information, see the LICENSE file in the top level directory of the 00010 // distribution. 00011 00012 #ifndef SSB_RUU_H 00013 #define SSB_RUU_H 00014 00015 #include "instruction.h" 00016 #include "ssb_bpred.h" 00017 #include "ssb_machine.h" 00018 00019 /* total input dependencies possible */ 00020 #define MAX_IDEPS 5 00021 00022 /* total output dependencies possible */ 00023 #define MAX_ODEPS 5 00024 00025 //: register update unit (RUU) station 00026 // 00027 // A register update unit (RUU) station, this record is contained in 00028 // the processors RUU, which serves as a collection of ordered 00029 // reservations stations. The reservation stations capture register 00030 // results and await the time when all operands are ready, at which 00031 // time the instruction is issued to the functional units; the RUU is 00032 // an order circular queue, in which instructions are inserted in 00033 // fetch (program) order, results are stored in the RUU buffers, and 00034 // later when an RUU entry is the oldest entry in the machines, it and 00035 // its instruction's value is retired to the architectural register 00036 // file in program order, NOTE: the RUU and LSQ share the same 00037 // structure, this is useful because loads and stores are split into 00038 // two operations: an effective address add and a load/store, the add 00039 // is inserted into the RUU and the load/store inserted into the LSQ, 00040 // allowing the add to wake up the load/store when effective address 00041 // computation has finished 00042 // 00043 //!SEC:ssBack 00044 struct RUU_station { 00045 /* inst info */ 00046 instruction *IR; /* instruction bits */ 00047 instType op; 00048 md_addr_t PC, next_PC, pred_PC; /* inst PC, next PC, predicted PC */ 00049 int in_LSQ; /* non-zero if op is in LSQ */ 00050 int ea_comp; /* non-zero if op is an addr comp */ 00051 int recover_inst; /* start of mis-speculation? */ 00052 int stack_recover_idx; /* non-speculative TOS for RSB pred */ 00053 struct bpred_update_t dir_update; /* bpred direction update info */ 00054 int spec_mode; /* non-zero if issued in spec_mode */ 00055 md_addr_t addr; /* effective address for ld/st's */ 00056 INST_TAG_TYPE tag; /* RUU slot tag, increment to 00057 squash operation */ 00058 INST_SEQ_TYPE seq; /* instruction sequence, used to 00059 sort the ready list and tag inst */ 00060 unsigned int ptrace_seq; /* pipetrace sequence number */ 00061 00062 /* instruction status */ 00063 int queued; /* operands ready and queued */ 00064 int issued; /* operation is/was executing */ 00065 int completed; /* operation has completed execution */ 00066 00067 //: ouput dependency list 00068 // output operand dependency list, these lists are used to limit the 00069 // number of associative searches into the RUU when instructions 00070 // complete and need to wake up dependent insts 00071 int onames[MAX_ODEPS]; /* output logical names (NA=unused) */ 00072 struct RS_link *odep_list[MAX_ODEPS]; /* chains to consuming operations */ 00073 00074 //: input dep list 00075 // 00076 // input dependent links, the output chains rooted above use these 00077 // fields to mark input operands as ready, when all these fields 00078 // have been set non-zero, the RUU operation has all of its register 00079 // operands, it may commence execution as soon as all of its memory 00080 // operands are known to be read (see lsq_refresh() for details on 00081 // enforcing memory dependencies) 00082 int idep_ready[MAX_IDEPS]; /* input operand ready? */ 00083 00084 int lsq_count; /* Number of memory ops */ 00085 }; 00086 00087 #endif