00001 #if !defined(__OPENPIC_H__) 00002 #define __OPENPIC_H__ 00003 00004 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */ 00005 enum { 00006 OPENPIC_OUTPUT_INT = 0, /* IRQ */ 00007 OPENPIC_OUTPUT_CINT, /* critical IRQ */ 00008 OPENPIC_OUTPUT_MCK, /* Machine check event */ 00009 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */ 00010 OPENPIC_OUTPUT_RESET, /* Core reset event */ 00011 OPENPIC_OUTPUT_NB, 00012 }; 00013 00014 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, 00015 qemu_irq **irqs, qemu_irq irq_out); 00016 qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus, 00017 qemu_irq **irqs, qemu_irq irq_out); 00018 #endif /* __OPENPIC_H__ */