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00050 #ifndef CORE_H_
00051 #define CORE_H_
00052
00053 #include "XML_Parse.h"
00054 #include "logic.h"
00055 #include "parameter.h"
00056 #include "array.h"
00057 #include "interconnect.h"
00058 #include "basic_components.h"
00059 #include "sharedcache.h"
00060
00061 class BranchPredictor :public McPATComponent {
00062 public:
00063
00064 ParseXML *XML;
00065 int ithCore;
00066 InputParameter interface_ip;
00067 CoreDynParam coredynp;
00068 double clockRate,executionTime;
00069 double scktRatio, chip_PR_overhead, macro_PR_overhead;
00070 ArrayST * globalBPT;
00071 ArrayST * localBPT;
00072 ArrayST * L1_localBPT;
00073 ArrayST * L2_localBPT;
00074 ArrayST * chooser;
00075 ArrayST * RAS;
00076 bool exist;
00077
00078 BranchPredictor(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exsit=true);
00079 void computeEnergy(bool is_tdp=true);
00080 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00081 ~BranchPredictor();
00082
00083
00084 void SSTcomputeEnergy(bool is_tdp=true, double branch_read=0, double branch_write=0, double RAS_read=0, double RAS_write=0);
00085 ArrayST* SSTreturnGlobalBPT(){return globalBPT;}
00086 ArrayST* SSTreturnL1BPT(){return L1_localBPT;}
00087 ArrayST* SSTreturnL2BPT(){return L2_localBPT;}
00088 ArrayST* SSTreturnChooser(){return chooser;}
00089 ArrayST* SSTreturnRAS(){return RAS;}
00090 void SSTleakage_feedback(double temperature);
00091
00092
00093 };
00094
00095
00096 class InstFetchU :public McPATComponent {
00097 public:
00098
00099 ParseXML *XML;
00100 int ithCore;
00101 InputParameter interface_ip;
00102 CoreDynParam coredynp;
00103 double clockRate,executionTime;
00104 double scktRatio, chip_PR_overhead, macro_PR_overhead;
00105 enum Cache_policy cache_p;
00106 InstCache icache;
00107 ArrayST * IB;
00108 ArrayST * BTB;
00109 BranchPredictor * BPT;
00110 inst_decoder * ID_inst;
00111 inst_decoder * ID_operand;
00112 inst_decoder * ID_misc;
00113 bool exist;
00114
00115 InstFetchU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exsit=true);
00116 void computeEnergy(bool is_tdp=true);
00117 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00118 ~InstFetchU();
00119
00120
00121 void SSTcomputeEnergy(bool is_tdp=true, double il1_read_accesses=0, double il1_read_misses=0, double IB_read=0, double IB_write=0, double BTB_read=0, double BTB_write=0, double ID_inst_read=0, double ID_operand_read=0, double ID_misc_read=0);
00122 InstCache SSTreturnIcache(){return icache;}
00123 ArrayST* SSTreturnIB(){return IB;}
00124 ArrayST* SSTreturnBTB(){return BTB;}
00125 BranchPredictor* SSTreturnBPT(){return BPT;}
00126 inst_decoder* SSTreturnIDinst(){return ID_inst;}
00127 inst_decoder* SSTreturnIDoperand(){return ID_operand;}
00128 inst_decoder* SSTreturnIDmisc(){return ID_misc;}
00129
00130 };
00131
00132
00133 class SchedulerU :public McPATComponent {
00134 public:
00135
00136 ParseXML *XML;
00137 int ithCore;
00138 InputParameter interface_ip;
00139 CoreDynParam coredynp;
00140 double clockRate,executionTime;
00141 double scktRatio, chip_PR_overhead, macro_PR_overhead;
00142 double Iw_height, fp_Iw_height,ROB_height;
00143 ArrayST * int_inst_window;
00144 ArrayST * fp_inst_window;
00145 ArrayST * ROB;
00146 selection_logic * instruction_selection;
00147 bool exist;
00148
00149 SchedulerU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
00150 void computeEnergy(bool is_tdp=true);
00151 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00152 ~SchedulerU();
00153
00154
00155 void SSTcomputeEnergy(bool is_tdp=true, double int_win_read=0, double int_win_write=0, double int_win_search=0, double fp_win_read=0, double fp_win_write=0, double fp_win_search=0, double ROB_read=0, double ROB_write=0);
00156 ArrayST* SSTreturnIntWindow(){return int_inst_window;}
00157 ArrayST* SSTreturnFpWindow(){return fp_inst_window;}
00158 ArrayST* SSTreturnROB(){return ROB;}
00159 selection_logic* SSTreturnInstSelection(){return instruction_selection;}
00160
00161 };
00162
00163 class RENAMINGU :public McPATComponent {
00164 public:
00165
00166 ParseXML *XML;
00167 int ithCore;
00168 InputParameter interface_ip;
00169 double clockRate,executionTime;
00170 CoreDynParam coredynp;
00171 ArrayST * iFRAT;
00172 ArrayST * fFRAT;
00173 ArrayST * iRRAT;
00174 ArrayST * fRRAT;
00175 ArrayST * ifreeL;
00176 ArrayST * ffreeL;
00177 dep_resource_conflict_check * idcl;
00178 dep_resource_conflict_check * fdcl;
00179 ArrayST * RAHT;
00180 bool exist;
00181
00182
00183 RENAMINGU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_, const CoreDynParam & dyn_p_, bool exist_=true);
00184 void computeEnergy(bool is_tdp=true);
00185 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00186 ~RENAMINGU();
00187
00188
00189 void SSTcomputeEnergy(bool is_tdp=true, double iFRAT_read=0, double iFRAT_write=0, double iFRAT_search=0, double fFRAT_read=0, double fFRAT_write=0, double fFRAT_search=0, double iRRAT_read=0, double iRRAT_write=0, double fRRAT_read=0, double fRRAT_write=0, double ifreeL_read=0, double ifreeL_write=0, double ffreeL_read=0, double ffreeL_write=0, double idcl_read=0, double fdcl_read=0);
00190 ArrayST* SSTreturnIFRAT(){return iFRAT;}
00191 ArrayST* SSTreturnFFRAT(){return fFRAT;}
00192 ArrayST* SSTreturnIRRAT(){return iRRAT;}
00193 ArrayST* SSTreturnFRRAT(){return fRRAT;}
00194 ArrayST* SSTreturnIfreeL(){return ifreeL;}
00195 ArrayST* SSTreturnFfreeL(){return ffreeL;}
00196 dep_resource_conflict_check* SSTreturnIDCL(){return idcl;}
00197 dep_resource_conflict_check* SSTreturnFDCL(){return fdcl;}
00198 };
00199
00200 class LoadStoreU :public McPATComponent {
00201 public:
00202
00203 ParseXML *XML;
00204 int ithCore;
00205 InputParameter interface_ip;
00206 CoreDynParam coredynp;
00207 enum Cache_policy cache_p;
00208 double clockRate,executionTime;
00209 double scktRatio, chip_PR_overhead, macro_PR_overhead;
00210 double lsq_height;
00211 DataCache dcache;
00212 ArrayST * LSQ;
00213 ArrayST * LoadQ;
00214 bool exist;
00215
00216 LoadStoreU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
00217 void computeEnergy(bool is_tdp=true);
00218 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00219 ~LoadStoreU();
00220
00221
00222 void SSTcomputeEnergy(bool is_tdp=true, double dl1_read=0, double dl1_readmiss=0, double dl1_write=0, double dl1_writemiss=0, double LSQ_read=0, double LSQ_write=0, double loadQ_read=0, double loadQ_write=0);
00223 DataCache SSTreturnDcache(){return dcache;}
00224 ArrayST* SSTreturnLSQ(){return LSQ;}
00225 ArrayST* SSTreturnLoadQ(){return LoadQ;}
00226 };
00227
00228 class MemManU :public McPATComponent {
00229 public:
00230
00231 ParseXML *XML;
00232 int ithCore;
00233 InputParameter interface_ip;
00234 CoreDynParam coredynp;
00235 double clockRate,executionTime;
00236 double scktRatio, chip_PR_overhead, macro_PR_overhead;
00237 ArrayST * itlb;
00238 ArrayST * dtlb;
00239 bool exist;
00240
00241 MemManU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
00242 void computeEnergy(bool is_tdp=true);
00243 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00244 ~MemManU();
00245
00246
00247 void SSTcomputeEnergy(bool is_tdp=true, double itlb_read=0, double itlb_readmiss=0, double dtlb_read=0, double dtlb_readmiss=0);
00248 ArrayST* SSTreturnITLB(){return itlb;}
00249 ArrayST* SSTreturnDTLB(){return dtlb;}
00250
00251 };
00252
00253 class RegFU :public McPATComponent {
00254 public:
00255
00256 ParseXML *XML;
00257 int ithCore;
00258 InputParameter interface_ip;
00259 CoreDynParam coredynp;
00260 double clockRate,executionTime;
00261 double scktRatio, chip_PR_overhead, macro_PR_overhead;
00262 double int_regfile_height, fp_regfile_height;
00263 ArrayST * IRF;
00264 ArrayST * FRF;
00265 ArrayST * RFWIN;
00266 bool exist;
00267
00268 RegFU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
00269 void computeEnergy(bool is_tdp=true);
00270 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00271 ~RegFU();
00272
00273
00274 void SSTcomputeEnergy(bool is_tdp=true, double int_regfile_reads=0, double int_regfile_writes=0, double float_regfile_reads=0, double float_regfile_writes=0, double RFWIN_read=0, double RFWIN_write=0);
00275 ArrayST* SSTreturnIRF(){return IRF;}
00276 ArrayST* SSTreturnFRF(){return FRF;}
00277 ArrayST* SSTreturnRFWIN(){return RFWIN;}
00278 void SSTleakage_feedback(double temperature);
00279
00280 };
00281
00282 class EXECU :public McPATComponent {
00283 public:
00284
00285 ParseXML *XML;
00286 int ithCore;
00287 InputParameter interface_ip;
00288 double clockRate,executionTime;
00289 double scktRatio, chip_PR_overhead, macro_PR_overhead;
00290 double lsq_height;
00291 CoreDynParam coredynp;
00292 RegFU * rfu;
00293 SchedulerU * scheu;
00294 FunctionalUnit * fp_u;
00295 FunctionalUnit * exeu;
00296 FunctionalUnit * mul;
00297 interconnect * int_bypass;
00298 interconnect * intTagBypass;
00299 interconnect * int_mul_bypass;
00300 interconnect * intTag_mul_Bypass;
00301 interconnect * fp_bypass;
00302 interconnect * fpTagBypass;
00303
00304 McPATComponent bypass;
00305 bool exist;
00306
00307 EXECU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_, double lsq_height_,const CoreDynParam & dyn_p_, bool exist_=true);
00308 void computeEnergy(bool is_tdp=true);
00309 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00310 ~EXECU();
00311
00312
00313 void SSTcomputeEnergy(bool is_tdp=true, double alu_access=0, double mul_access=0, double fpu_access=0);
00314 RegFU* SSTreturnRFU(){return rfu;}
00315 SchedulerU* SSTreturnSCHEU(){return scheu;}
00316 FunctionalUnit* SSTreturnFPU(){return fp_u;}
00317 FunctionalUnit* SSTreturnEXEU(){return exeu;}
00318 interconnect* SSTreturnIntBy(){return int_bypass;}
00319 interconnect* SSTreturnIntTagBy(){return intTagBypass;}
00320 interconnect* SSTreturnFpBy(){return fp_bypass;}
00321 interconnect* SSTreturnFpTagBy(){return fpTagBypass;}
00322 McPATComponent SSTreturnBy(){return bypass;}
00323
00324 };
00325
00326
00327 class Core :public McPATComponent {
00328 public:
00329
00330 ParseXML *XML;
00331 int ithCore;
00332 InputParameter interface_ip;
00333 double clockRate,executionTime;
00334 double scktRatio, chip_PR_overhead, macro_PR_overhead;
00335 InstFetchU * ifu;
00336 LoadStoreU * lsu;
00337 MemManU * mmu;
00338 EXECU * exu;
00339 RENAMINGU * rnu;
00340 Pipeline * corepipe;
00341 UndiffCore * undiffCore;
00342 SharedCache * l2cache;
00343 CoreDynParam coredynp;
00344
00345
00346 Core(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_);
00347 void set_core_param();
00348 void computeEnergy(bool is_tdp=true);
00349 void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00350 ~Core();
00351
00352
00353 InstFetchU* SSTreturnIFU(){return ifu;}
00354 LoadStoreU* SSTreturnLSU(){return lsu;}
00355 MemManU* SSTreturnMMU(){return mmu;}
00356 EXECU* SSTreturnEXU(){return exu;}
00357 RENAMINGU* SSTreturnRNU(){return rnu;}
00358 Pipeline* SSTreturnPIPE(){return corepipe;}
00359
00360 };
00361
00362 #endif