00001 #ifndef FIRMWARE_ABI_H
00002 #define FIRMWARE_ABI_H
00003
00004 #ifndef __ASSEMBLY__
00005
00006
00007
00008 typedef struct ohwcfg_v3_t ohwcfg_v3_t;
00009 struct ohwcfg_v3_t {
00010
00011 uint8_t struct_ident[0x10];
00012
00013 uint32_t struct_version;
00014 uint16_t nvram_size;
00015 uint16_t pad0;
00016 uint16_t nvram_arch_ptr;
00017 uint16_t nvram_arch_size;
00018 uint16_t nvram_arch_crc;
00019 uint8_t pad1[0x02];
00020
00021 uint8_t arch[0x10];
00022
00023 uint64_t RAM0_base;
00024 uint64_t RAM0_size;
00025 uint64_t RAM1_base;
00026 uint64_t RAM1_size;
00027 uint64_t RAM2_base;
00028 uint64_t RAM2_size;
00029 uint64_t RAM3_base;
00030 uint64_t RAM3_size;
00031 uint64_t ROM_base;
00032 uint64_t ROM_size;
00033
00034 uint64_t kernel_image;
00035 uint64_t kernel_size;
00036
00037 uint64_t cmdline;
00038 uint64_t cmdline_size;
00039
00040 uint64_t initrd_image;
00041 uint64_t initrd_size;
00042
00043 uint64_t NVRAM_image;
00044 uint8_t pad2[8];
00045
00046 uint16_t width;
00047 uint16_t height;
00048 uint16_t depth;
00049 uint16_t graphic_flags;
00050
00051 uint8_t nb_cpus;
00052 uint8_t boot_cpu;
00053 uint8_t nboot_devices;
00054 uint8_t pad3[5];
00055
00056 uint8_t boot_devices[0x10];
00057
00058 uint8_t pad4[0x1C];
00059
00060 uint16_t crc;
00061 uint8_t pad5[0x02];
00062 } __attribute__ (( packed ));
00063
00064 #define OHW_GF_NOGRAPHICS 0x0001
00065
00066 static inline uint16_t
00067 OHW_crc_update (uint16_t prev, uint16_t value)
00068 {
00069 uint16_t tmp;
00070 uint16_t pd, pd1, pd2;
00071
00072 tmp = prev >> 8;
00073 pd = prev ^ value;
00074 pd1 = pd & 0x000F;
00075 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
00076 tmp ^= (pd1 << 3) | (pd1 << 8);
00077 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
00078
00079 return tmp;
00080 }
00081
00082 static inline uint16_t
00083 OHW_compute_crc (ohwcfg_v3_t *header, uint32_t start, uint32_t count)
00084 {
00085 uint32_t i;
00086 uint16_t crc = 0xFFFF;
00087 uint8_t *ptr = (uint8_t *)header;
00088 int odd;
00089
00090 odd = count & 1;
00091 count &= ~1;
00092 for (i = 0; i != count; i++) {
00093 crc = OHW_crc_update(crc, (ptr[start + i] << 8) | ptr[start + i + 1]);
00094 }
00095 if (odd) {
00096 crc = OHW_crc_update(crc, ptr[start + i] << 8);
00097 }
00098
00099 return crc;
00100 }
00101
00102
00103 struct sparc_arch_cfg {
00104 uint32_t smp_ctx;
00105 uint32_t smp_ctxtbl;
00106 uint32_t smp_entry;
00107 uint8_t valid;
00108 uint8_t unused[51];
00109 };
00110
00111
00112 struct OpenBIOS_nvpart_v1 {
00113 uint8_t signature;
00114 uint8_t checksum;
00115 uint16_t len;
00116 char name[12];
00117 };
00118
00119 #define OPENBIOS_PART_SYSTEM 0x70
00120 #define OPENBIOS_PART_FREE 0x7f
00121
00122 static inline void
00123 OpenBIOS_finish_partition(struct OpenBIOS_nvpart_v1 *header, uint32_t size)
00124 {
00125 unsigned int i, sum;
00126 uint8_t *tmpptr;
00127
00128
00129 header->len = cpu_to_be16(size >> 4);
00130
00131
00132 tmpptr = (uint8_t *)header;
00133 sum = *tmpptr;
00134 for (i = 0; i < 14; i++) {
00135 sum += tmpptr[2 + i];
00136 sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
00137 }
00138 header->checksum = sum & 0xff;
00139 }
00140
00141 static inline uint32_t
00142 OpenBIOS_set_var(uint8_t *nvram, uint32_t addr, const char *str)
00143 {
00144 uint32_t len;
00145
00146 len = strlen(str) + 1;
00147 memcpy(&nvram[addr], str, len);
00148
00149 return addr + len;
00150 }
00151
00152
00153 struct Sun_nvram {
00154 uint8_t type;
00155 uint8_t machine_id;
00156 uint8_t macaddr[6];
00157 uint8_t unused[7];
00158 uint8_t checksum;
00159 };
00160
00161 static inline void
00162 Sun_init_header(struct Sun_nvram *header, const uint8_t *macaddr, int machine_id)
00163 {
00164 uint8_t tmp, *tmpptr;
00165 unsigned int i;
00166
00167 header->type = 1;
00168 header->machine_id = machine_id & 0xff;
00169 memcpy(&header->macaddr, macaddr, 6);
00170
00171 tmp = 0;
00172 tmpptr = (uint8_t *)header;
00173 for (i = 0; i < 15; i++)
00174 tmp ^= tmpptr[i];
00175
00176 header->checksum = tmp;
00177 }
00178
00179 #else
00180
00181
00182
00183
00184 #define OHW_ARCH_PTR 0x18
00185 #define OHW_RAM_SIZE 0x38
00186 #define OHW_BOOT_CPU 0xC9
00187
00188
00189 #define SPARC_SMP_CTX 0x0
00190 #define SPARC_SMP_CTXTBL 0x4
00191 #define SPARC_SMP_ENTRY 0x8
00192 #define SPARC_SMP_VALID 0xc
00193
00194
00195 #define SPARC_MACHINE_ID 0x1fd9
00196
00197 #endif
00198 #endif