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00013 #ifndef _PREFETCH_H_
00014 #define _PREFETCH_H_
00015
00016 #include "sst_config.h"
00017 #include <string>
00018 #include <queue>
00019 #include <set>
00020 #include <map>
00021 #ifdef HAVE_UNORDERED_SET
00022 # include <unordered_set>
00023 #elif defined(HAVE_TR1_UNORDERED_SET)
00024 # include <tr1/unordered_set>
00025 #else
00026 # ifdef __GNUC__
00027 # if __GNUC__ < 3
00028 # include <hash_set.h>
00029 namespace extension { using ::hash_set; };
00030 # else
00031 # include <ext/hash_set>
00032
00033 # if __GNUC__ == 3 && __GNUC_MINOR__ == 0
00034 namespace extension = std;
00035 # else
00036 namespace extension = ::__gnu_cxx;
00037 # endif
00038 # endif
00039 # else
00040 # include <hash_set>
00041 # endif
00042 #endif
00043 #include <list>
00044 #include "FE/pool.h"
00045 #include "ssb_DMA_fakeInst.h"
00046 #include "instruction.h"
00047
00048 using namespace std;
00049
00050
00051 class prefetchMC {
00052 public:
00053 virtual ~prefetchMC() {;}
00054
00055
00056
00057 virtual int load()=0;
00058 };
00059
00060
00061
00062
00063 class prefetchProc {
00064 public:
00065 virtual ~prefetchProc() {;}
00066
00067 virtual bool checkCache(const simAddress)=0;
00068
00069 virtual void insertCache(const simAddress)=0;
00070
00071 virtual void sendToMem(instruction *p)=0;
00072
00073 virtual void wakeUpPrefetched(instruction*)=0;
00074
00075 virtual uint64_t getCurrentCycle()=0;
00076 };
00077
00078
00079
00080
00081 class prefetcher {
00082 typedef map<string,string> paramMap_t;
00083
00084 paramMap_t params;
00085 int getValue(string s) {
00086 paramMap_t::iterator i = params.find(s);
00087 if (i != params.end()) {
00088 printf("getValue %s: %s (%d)\n", s.c_str(), i->second.c_str(), atoi(i->second.c_str()));
00089 return atoi(i->second.c_str());
00090 } else {
00091 return -1;
00092 }
00093 }
00094 string getStrValue(string s) {
00095 paramMap_t::iterator i = params.find(s);
00096 if (i != params.end()) {
00097 printf("getStrValue %s: %s\n", s.c_str(), i->second.c_str());
00098 return i->second;
00099 } else {
00100 return "";
00101 }
00102 }
00103
00104 int cacheShift;
00105
00106
00107 prefetchProc *proc;
00108
00109 int tagged;
00110
00111
00112
00113 int degree;
00114
00115 int adaptive;
00116
00117 unsigned long long adaptQuantaMask;
00118
00119
00120
00121 int adaptMax;
00122
00123
00124
00125 int decDeg;
00126
00127
00128
00129 int incDeg;
00130
00131
00132 int pageShift;
00133
00134
00135
00136 set<fakeDMAInstruction*> fakes;
00137
00138 set<simAddress> addrs;
00139
00140 #ifdef HAVE_UNORDERED_SET
00141 typedef std::unordered_set<simAddress> inCacheSet;
00142 #elif defined(HAVE_TR1_UNORDERED_SET)
00143 typedef std::tr1::unordered_set<simAddress> inCacheSet;
00144 #else
00145 # ifdef __GNUC__
00146 # if __GNUC__ < 3
00147 typedef hash_set<simAddress> inCacheSet;
00148 # elif __GNUC__ == 3 && __GNUC_MINOR__ == 0
00149 typedef std::hash_set<simAddress> inCacheSet;
00150 # else
00151 typedef __gnu_cxx::hash_set<simAddress> inCacheSet;
00152 # endif
00153 # else
00154 typedef std::hash_set<simAddress> inCacheSet;
00155 # endif
00156 #endif
00157
00158
00159
00160
00161 inCacheSet reqInCache;
00162
00163 static pool<fakeDMAInstruction> fakeInst;
00164
00165 unsigned long long requestsIssued;
00166
00167 unsigned long long requestsHit;
00168
00169 unsigned long long totalReq;
00170
00171
00172
00173
00174 unsigned long long overPage;
00175 unsigned long long tooLate;
00176
00177 int adaptions;
00178
00179
00180
00181 int subTotalReq;
00182
00183
00184
00185 int subRequestsHit;
00186
00187
00188 unsigned long long streamReq;
00189
00190 unsigned long long streamsDetected;
00191
00192
00193 int loadAware;
00194
00195 typedef list<instruction *> wakeUpList_t;
00196 typedef map<simAddress, wakeUpList_t > wakeUpMap_t;
00197
00198
00199
00200
00201 wakeUpMap_t wakeUpMap;
00202
00203 prefetchMC *mc;
00204
00205
00206
00207
00208 set<simAddress> streamIssued;
00209
00210 inCacheSet reqInSCache;
00211
00212 unsigned long long streamRequestsHit;
00213
00214
00215 int streams;
00216
00217 int windowL;
00218
00219 int detLeng;
00220
00221 int rr;
00222
00223
00224
00225 set<simAddress> streamSet;
00226
00227 int inWin;
00228
00229 std::queue<simAddress> window;
00230
00231 deque<simAddress> recentStreams;
00232
00233
00234
00235 inCacheSet contigCount;
00236
00237
00238
00239 simAddress lastBlock;
00240 void detectStream(const simAddress);
00241
00242
00243
00244
00245 int stats;
00246
00247 bool memReq(const simAddress, bool &);
00248 public:
00249 prefetcher(paramMap_t, prefetchProc *, prefetchMC *);
00250 typedef enum {INST, DATA} memAccType;
00251 typedef enum {READ,WRITE} memAccDir;
00252 void memRef(const simAddress, const memAccType, const memAccDir, bool hit);
00253 void reportCacheEject(const simAddress);
00254 bool handleParcel(instruction *p);
00255 bool isPreFetching(const simAddress);
00256 void setWakeUp(instruction *, simAddress);
00257 void finish();
00258 void preTic();
00259 };
00260
00261 #endif
00262
00263