00001 #ifndef QEMU_PCI_H
00002 #define QEMU_PCI_H
00003
00004
00005 #include "isa.h"
00006
00007
00008
00009 extern target_phys_addr_t pci_mem_base;
00010
00011 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
00012 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
00013 #define PCI_FUNC(devfn) ((devfn) & 0x07)
00014
00015
00016
00017 #define PCI_BASE_CLASS_STORAGE 0x01
00018 #define PCI_BASE_CLASS_NETWORK 0x02
00019
00020 #define PCI_CLASS_STORAGE_SCSI 0x0100
00021 #define PCI_CLASS_STORAGE_IDE 0x0101
00022 #define PCI_CLASS_STORAGE_OTHER 0x0180
00023
00024 #define PCI_CLASS_NETWORK_ETHERNET 0x0200
00025
00026 #define PCI_CLASS_DISPLAY_VGA 0x0300
00027 #define PCI_CLASS_DISPLAY_OTHER 0x0380
00028
00029 #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
00030
00031 #define PCI_CLASS_MEMORY_RAM 0x0500
00032
00033 #define PCI_CLASS_SYSTEM_OTHER 0x0880
00034
00035 #define PCI_CLASS_SERIAL_USB 0x0c03
00036
00037 #define PCI_CLASS_BRIDGE_HOST 0x0600
00038 #define PCI_CLASS_BRIDGE_ISA 0x0601
00039 #define PCI_CLASS_BRIDGE_PCI 0x0604
00040 #define PCI_CLASS_BRIDGE_OTHER 0x0680
00041
00042 #define PCI_CLASS_PROCESSOR_CO 0x0b40
00043 #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
00044
00045 #define PCI_CLASS_OTHERS 0xff
00046
00047
00048
00049 #define PCI_VENDOR_ID_LSI_LOGIC 0x1000
00050 #define PCI_DEVICE_ID_LSI_53C895A 0x0012
00051
00052 #define PCI_VENDOR_ID_DEC 0x1011
00053 #define PCI_DEVICE_ID_DEC_21154 0x0026
00054
00055 #define PCI_VENDOR_ID_CIRRUS 0x1013
00056
00057 #define PCI_VENDOR_ID_IBM 0x1014
00058 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
00059
00060 #define PCI_VENDOR_ID_AMD 0x1022
00061 #define PCI_DEVICE_ID_AMD_LANCE 0x2000
00062
00063 #define PCI_VENDOR_ID_HITACHI 0x1054
00064
00065 #define PCI_VENDOR_ID_MOTOROLA 0x1057
00066 #define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002
00067 #define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801
00068
00069 #define PCI_VENDOR_ID_APPLE 0x106b
00070 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
00071 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
00072 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
00073 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020
00074 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
00075
00076 #define PCI_VENDOR_ID_SUN 0x108e
00077 #define PCI_DEVICE_ID_SUN_EBUS 0x1000
00078 #define PCI_DEVICE_ID_SUN_SIMBA 0x5000
00079 #define PCI_DEVICE_ID_SUN_SABRE 0xa000
00080
00081 #define PCI_VENDOR_ID_CMD 0x1095
00082 #define PCI_DEVICE_ID_CMD_646 0x0646
00083
00084 #define PCI_VENDOR_ID_REALTEK 0x10ec
00085 #define PCI_DEVICE_ID_REALTEK_RTL8029 0x8029
00086 #define PCI_DEVICE_ID_REALTEK_8139 0x8139
00087
00088 #define PCI_VENDOR_ID_XILINX 0x10ee
00089
00090 #define PCI_VENDOR_ID_MARVELL 0x11ab
00091
00092 #define PCI_VENDOR_ID_QEMU 0x1234
00093 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
00094
00095 #define PCI_VENDOR_ID_ENSONIQ 0x1274
00096 #define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000
00097
00098 #define PCI_VENDOR_ID_VMWARE 0x15ad
00099 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
00100 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
00101 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
00102 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
00103 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
00104
00105 #define PCI_VENDOR_ID_INTEL 0x8086
00106 #define PCI_DEVICE_ID_INTEL_82441 0x1237
00107 #define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415
00108 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
00109 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
00110 #define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020
00111 #define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
00112 #define PCI_DEVICE_ID_INTEL_82371AB 0x7111
00113 #define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112
00114 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
00115
00116 #define PCI_VENDOR_ID_FSL 0x1957
00117 #define PCI_DEVICE_ID_FSL_E500 0x0030
00118
00119
00120 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
00121 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
00122 #define PCI_SUBDEVICE_ID_QEMU 0x1100
00123
00124 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
00125 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
00126 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
00127 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
00128
00129 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
00130 uint32_t address, uint32_t data, int len);
00131 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
00132 uint32_t address, int len);
00133 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
00134 uint32_t addr, uint32_t size, int type);
00135 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
00136
00137 #define PCI_ADDRESS_SPACE_MEM 0x00
00138 #define PCI_ADDRESS_SPACE_IO 0x01
00139 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
00140
00141 typedef struct PCIIORegion {
00142 uint32_t addr;
00143 uint32_t size;
00144 uint8_t type;
00145 PCIMapIORegionFunc *map_func;
00146 } PCIIORegion;
00147
00148 #define PCI_ROM_SLOT 6
00149 #define PCI_NUM_REGIONS 7
00150
00151 #define PCI_DEVICES_MAX 64
00152
00153 #define PCI_VENDOR_ID 0x00
00154 #define PCI_DEVICE_ID 0x02
00155 #define PCI_COMMAND 0x04
00156 #define PCI_COMMAND_IO 0x1
00157 #define PCI_COMMAND_MEMORY 0x2
00158 #define PCI_REVISION 0x08
00159 #define PCI_CLASS_DEVICE 0x0a
00160 #define PCI_SUBVENDOR_ID 0x2c
00161 #define PCI_SUBDEVICE_ID 0x2e
00162 #define PCI_INTERRUPT_LINE 0x3c
00163 #define PCI_INTERRUPT_PIN 0x3d
00164 #define PCI_MIN_GNT 0x3e
00165 #define PCI_MAX_LAT 0x3f
00166
00167
00168 #define PCI_STATUS_RESERVED1 0x007
00169 #define PCI_STATUS_INT_STATUS 0x008
00170 #define PCI_STATUS_CAPABILITIES 0x010
00171 #define PCI_STATUS_66MHZ 0x020
00172 #define PCI_STATUS_RESERVED2 0x040
00173 #define PCI_STATUS_FAST_BACK 0x080
00174 #define PCI_STATUS_DEVSEL 0x600
00175
00176 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
00177 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
00178 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
00179
00180 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
00181
00182
00183 #define PCI_COMMAND_RESERVED 0xf800
00184
00185 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
00186
00187 struct PCIDevice {
00188
00189 uint8_t config[256];
00190
00191
00192 PCIBus *bus;
00193 int devfn;
00194 char name[64];
00195 PCIIORegion io_regions[PCI_NUM_REGIONS];
00196
00197
00198 PCIConfigReadFunc *config_read;
00199 PCIConfigWriteFunc *config_write;
00200 PCIUnregisterFunc *unregister;
00201
00202 int irq_index;
00203
00204
00205 qemu_irq *irq;
00206
00207
00208 int irq_state[4];
00209 };
00210
00211 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
00212 int instance_size, int devfn,
00213 PCIConfigReadFunc *config_read,
00214 PCIConfigWriteFunc *config_write);
00215 int pci_unregister_device(PCIDevice *pci_dev);
00216
00217 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
00218 uint32_t size, int type,
00219 PCIMapIORegionFunc *map_func);
00220
00221 uint32_t pci_default_read_config(PCIDevice *d,
00222 uint32_t address, int len);
00223 void pci_default_write_config(PCIDevice *d,
00224 uint32_t address, uint32_t val, int len);
00225 void pci_device_save(PCIDevice *s, QEMUFile *f);
00226 int pci_device_load(PCIDevice *s, QEMUFile *f);
00227
00228 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
00229 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
00230 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
00231 qemu_irq *pic, int devfn_min, int nirq);
00232
00233 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
00234 const char *default_model);
00235 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
00236 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
00237 int pci_bus_num(PCIBus *s);
00238 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
00239 PCIBus *pci_find_bus(int bus_num);
00240 PCIDevice *pci_find_device(int bus_num, int slot, int function);
00241
00242 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp);
00243 int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp);
00244
00245 void pci_info(void);
00246 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
00247 pci_map_irq_fn map_irq, const char *name);
00248
00249 static inline void
00250 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
00251 {
00252 cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val);
00253 }
00254
00255 static inline void
00256 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
00257 {
00258 cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val);
00259 }
00260
00261 static inline void
00262 pci_config_set_class(uint8_t *pci_config, uint16_t val)
00263 {
00264 cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val);
00265 }
00266
00267
00268 #define LSI_MAX_DEVS 7
00269 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
00270 void *lsi_scsi_init(PCIBus *bus, int devfn);
00271
00272
00273 void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
00274 unsigned long vga_ram_offset, int vga_ram_size);
00275
00276
00277 void usb_uhci_piix3_init(PCIBus *bus, int devfn);
00278 void usb_uhci_piix4_init(PCIBus *bus, int devfn);
00279
00280
00281 void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
00282
00283
00284
00285 PCIDevice *pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
00286 PCIDevice *pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
00287 PCIDevice *pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
00288
00289
00290
00291 PCIDevice *pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
00292
00293
00294
00295 PCIDevice *pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
00296
00297
00298 PCIDevice *pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn);
00299
00300
00301 PCIDevice *pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
00302
00303
00304 PCIBus *pci_prep_init(qemu_irq *pic);
00305
00306
00307 PCIBus *pci_apb_init(target_phys_addr_t special_base,
00308 target_phys_addr_t mem_base,
00309 qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
00310
00311
00312 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
00313 qemu_irq *pic, int devfn_min, int nirq);
00314
00315 #endif