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00012 #ifndef SSB_SIM_OUTORDER_H
00013 #define SSB_SIM_OUTORDER_H
00014
00015 #include <set>
00016 #include "ssb_memory.h"
00017 #include "ssb_ruu.h"
00018 #include "ssb_cv_link.h"
00019 #include "ssb_rs_link.h"
00020 #include "ssb_bitmap.h"
00021 #include "ssb_cache.h"
00022 #include "prefetch.h"
00023 #include "sst/core/event.h"
00024
00025 #define GET_IMIX 1
00026
00027 class thread;
00028
00029
00030
00031
00032
00033
00034
00035 class convProc : public prefetchProc
00036 {
00037 friend struct CV_link;
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047 long tickCount;
00048 processor *myProc;
00049 int myCoreID;
00050 public:
00051 long long TimeStamp() const {
00052 return tickCount;
00053 }
00054
00055
00056
00057
00058 virtual bool checkCache(const simAddress addr) {
00059 return cache_probe(cache_dl2, addr);
00060 };
00061
00062
00063
00064 virtual void insertCache(const simAddress mem) {
00065 bool dc; md_addr_t bumped = 0;
00066 cache_access(cache_dl2, Inject, (mem&~3), NULL, 0, TimeStamp(),
00067 NULL, NULL, dc, &bumped);
00068 if (dc == 1) {
00069 printf("need to handle main mem access in %s\n", __FILE__);
00070 }
00071 if (bumped != 0) {
00072 if (pref) pref->reportCacheEject(bumped);
00073 }
00074 }
00075 void wakeUpMM(map<instruction*, RUU_station*>::iterator &mi);
00076 void wakeUpPrefetched(instruction *inst);
00077
00078
00079
00080 virtual void sendToMem(instruction *i) {
00081 mmSendParcel(i);
00082 }
00083 protected:
00084
00085
00086
00087 bool simpleFetch;
00088
00089
00090
00091
00092 int maxMMStores;
00093
00094
00095
00096
00097
00098
00099 int portLimitedCommit;
00100 int regPortAvail;
00101
00102
00103
00104
00105 int waciLoadExtra;
00106
00107 unsigned long long lsqCompares;
00108
00109
00110
00111
00112
00113 bool clearPipe;
00114
00115
00116
00117
00118
00119
00120
00121 bool isSyncing;
00122
00123
00124 int clockRatio;
00125
00126
00127
00128 map<frameID, simRegister*> allocatedFrames;
00129
00130
00131
00132
00133
00134
00135 set<instruction*> mainMemStores;
00136
00137
00138
00139
00140
00141
00142 deque<instruction*> retireList;
00143
00144
00145
00146
00147 set<instruction*> OOOStores;
00148
00149 set<instruction*> condemnedRemotes;
00150
00151
00152
00153
00154
00155
00156 map<instruction*, RUU_station*> mainMemLoads;
00157
00158
00159
00160
00161
00162
00163 instruction *iFetchBlocker;
00164
00165
00166
00167
00168
00169
00170 prefetcher *pref;
00171
00172
00173 thread *thr;
00174
00175
00176
00177
00178 int instructionSize;
00179
00180
00181
00182
00183
00184
00185
00186 int simpleMemory;
00187
00188 RS_link_list rs_free_list;
00189
00190
00191
00192
00193
00194 struct RS_link last_op;
00195
00196
00197 md_addr_t pred_PC;
00198
00199
00200 md_addr_t recover_PC;
00201
00202
00203 md_addr_t fetch_regs_PC;
00204
00205
00206 md_addr_t fetch_pred_PC;
00207
00208
00209 struct fetch_rec *fetch_data;
00210
00211 int fetch_num;
00212
00213 int fetch_tail;
00214
00215 int fetch_head;
00216
00217
00218 int last_inst_missed;
00219 int last_inst_tmissed;
00220
00221
00222
00223
00224
00225 struct RUU_station *RUU;
00226
00227 int RUU_head;
00228
00229 int RUU_tail;
00230
00231 int RUU_num;
00232
00233
00234
00235
00236
00237
00238
00239
00240
00241
00242
00243
00244
00245
00246
00247
00248
00249
00250
00251
00252
00253
00254
00255
00256
00257
00258
00259
00260
00261
00262
00263
00264
00265
00266
00267
00268
00269
00270
00271
00272
00273 struct RUU_station *LSQ;
00274
00275 int LSQ_head;
00276
00277 int LSQ_tail;
00278
00279 int LSQ_num;
00280
00281
00282
00283
00284
00285
00286 struct RS_link *event_queue;
00287
00288
00289 struct RS_link *ready_queue;
00290
00291 unsigned int use_spec_cv[CV_BMAP_SZ];
00292
00293
00294
00295
00296
00297
00298
00299
00300
00301 struct CV_link create_vector[MD_TOTAL_REGS+2];
00302
00303
00304
00305 struct CV_link spec_create_vector[MD_TOTAL_REGS+2];
00306
00307
00308 tick_t create_vector_rt[MD_TOTAL_REGS+2];
00309
00310 tick_t spec_create_vector_rt[MD_TOTAL_REGS+2];
00311
00312
00313
00314
00315 #include "ssb_sim-outorder-options.h"
00316
00317
00318
00319 struct opt_odb_t *sim_odb;
00320
00321
00322
00323
00324
00325 struct stat_sdb_t *sim_sdb;
00326
00327 #if GET_IMIX == 1
00328
00329 unsigned long long iMix[LASTINST];
00330 #endif
00331
00332 counter_t sim_num_insn;
00333
00334 counter_t sim_total_insn;
00335
00336 counter_t sim_num_refs;
00337
00338 counter_t sim_total_refs;
00339
00340 counter_t sim_num_loads;
00341
00342 counter_t sim_total_loads;
00343
00344 counter_t sim_num_branches;
00345
00346 counter_t sim_total_branches;
00347
00348 counter_t IFQ_count;
00349
00350 counter_t IFQ_fcount;
00351
00352 counter_t RUU_count;
00353
00354 counter_t RUU_fcount;
00355
00356 counter_t LSQ_count;
00357 #define WANT_LSQ_HIST 1
00358 #if WANT_LSQ_HIST == 1
00359 map<int, counter_t> LSQ_hist;
00360 #endif
00361
00362 counter_t LSQ_fcount;
00363
00364
00365 counter_t sim_invalid_addrs;
00366
00367
00368
00369
00370
00371 time_t sim_start_time;
00372
00373 time_t sim_end_time;
00374
00375 int sim_elapsed_time;
00376
00377
00378
00379
00380 unsigned int inst_seq;
00381
00382 unsigned int ptrace_seq;
00383
00384
00385
00386
00387
00388
00389 bool spec_mode;
00390
00391 int lsq_mult;
00392
00393
00394 unsigned ruu_fetch_issue_delay;
00395
00396
00397 unsigned ruu_dispatch_delay;
00398 virtual unsigned getFEBDelay() {return 0;}
00399
00400 int pred_perfect;
00401
00402 char *bpred_spec_opt;
00403
00404 enum { spec_ID, spec_WB, spec_CT } bpred_spec_update;
00405
00406
00407 struct cache_t *cache_il1;
00408
00409
00410 struct cache_t *cache_il2;
00411
00412
00413 struct cache_t *cache_dl1;
00414
00415
00416 struct cache_t *cache_dl2;
00417
00418 struct cache_t *itlb;
00419
00420 struct cache_t *dtlb;
00421
00422 struct bpred_t *pred;
00423
00424 struct res_pool *fu_pool;
00425
00426 struct stat_stat_t *pcstat_stats[MAX_PCSTAT_VARS];
00427
00428 counter_t pcstat_lastvals[MAX_PCSTAT_VARS];
00429
00430 struct stat_stat_t *pcstat_sdists[MAX_PCSTAT_VARS];
00431
00432 typedef map<instruction*, int> latencyMap;
00433 latencyMap extraInstLat;
00434 instruction *committingInst;
00435
00436
00437
00438
00439 public:
00440 convProc(string configFile, processor *p, int maxMMOut, int coreNum,
00441 map<string,string> prefetchInit);
00442
00443 protected:
00444
00445
00446
00447
00448
00449 void mmSendParcel(instruction *inst);
00450 void mainMemAccess(instruction*);
00451 unsigned int mem_access_latency(int blk_sz);
00452 virtual unsigned int cplx_mem_access_latency(const enum mem_cmd cmd,
00453 const md_addr_t baddr,
00454 const int bsize,
00455 bool &);
00456
00457
00458
00459 virtual void noteWrite(const simAddress a) = 0;
00460 virtual void handleCoher(const simAddress, const enum mem_cmd cmd) = 0;
00461 uint dl1_access_fn(enum mem_cmd cmd, md_addr_t baddr, int bsize,
00462 struct cache_blk_t *blk, tick_t now, bool&);
00463 uint dl2_access_fn(enum mem_cmd cmd, md_addr_t baddr, int bsize,
00464 cache_blk_t *blk, tick_t now, bool&);
00465 uint il1_access_fn(enum mem_cmd cmd, md_addr_t baddr, int bsize,
00466 struct cache_blk_t *blk, tick_t now, bool&);
00467 uint il2_access_fn(enum mem_cmd cmd, md_addr_t baddr, int bsize,
00468 struct cache_blk_t *blk, tick_t now, bool&);
00469 uint itlb_access_fn(enum mem_cmd cmd, md_addr_t baddr, int bsize,
00470 struct cache_blk_t *blk, tick_t now, bool&);
00471 uint dtlb_access_fn(enum mem_cmd cmd, md_addr_t baddr, int bsize,
00472 struct cache_blk_t *blk, tick_t now, bool&);
00473
00474
00475
00476
00477 void sim_print_stats(FILE *fd);
00478 int ss_main(const char*);
00479
00480
00481
00482
00483 void sim_reg_options(struct opt_odb_t *odb);
00484 void sim_check_options(struct opt_odb_t *odb);
00485 void sim_reg_stats(struct stat_sdb_t *sdb);
00486
00487
00488
00489
00490 void sim_init(void);
00491
00492 void sim_load_prog(const string fuConfStr);
00493 void ruu_init(void);
00494 void lsq_init(void);
00495 void fetch_init(void);
00496
00497
00498
00499
00500 static void ruu_dumpent(struct RUU_station *rs, int index, FILE *stream,
00501 int header);
00502 void ruu_dump(FILE *stream);
00503 void lsq_dump(FILE *stream);
00504 void rspec_dump(FILE *stream);
00505 void mspec_dump(FILE *stream);
00506 void fetch_dump(FILE *stream);
00507 void eventq_dump(FILE *stream);
00508 void readyq_dump(FILE *stream);
00509
00510
00511
00512
00513 static char *simoo_reg_obj(struct regs_t *regs, int is_write,
00514 enum md_reg_type rt, int reg,
00515 struct eval_value_t *val);
00516 static char *simoo_mem_obj(struct mem_t *mem, int is_write,
00517 md_addr_t addr, char *p, int nbytes);
00518 static char *simoo_mstate_obj(FILE *stream, char *cmd, struct regs_t *regs,
00519 struct mem_t *mem);
00520
00521
00522
00523
00524 struct RUU_station *eventq_next_event(void);
00525 void eventq_queue_event(struct RUU_station *rs, tick_t when);
00526 void eventq_init(void);
00527
00528
00529
00530
00531 void readyq_init(void);
00532 void readyq_enqueue(struct RUU_station *rs);
00533
00534
00535
00536
00537 void tracer_recover(void);
00538 void tracer_init(void);
00539 void ruu_recover(int branch_index);
00540
00541
00542
00543
00544 void ruu_link_idep(struct RUU_station * const rs, const int idep_num, const int idep_name);
00545 void ruu_install_odep(struct RUU_station *rs, int odep_num, int odep_name);
00546
00547
00548
00549
00550 void sim_loop(void);
00551 void ruu_release_fu(void);
00552 void ruu_commit(void);
00553 void ruu_writeback(void);
00554 void lsq_refresh(void);
00555 void ruu_issue(void);
00556 void ruu_dispatch(void);
00557 void ruu_fetch(void);
00558 public:
00559
00560
00561
00562
00563
00564
00565 bool pipeClear() {return (RUU_num == 0 && fetch_num == 0 &&
00566 retireList.empty());}
00567 protected:
00568
00569
00570
00571
00572 bool pipeDispatchClear() {return (RUU_num == 0 && retireList.empty());}
00573
00574
00575
00576
00577 virtual void setup()=0;
00578 virtual void finish();
00579 public:
00580 virtual void handleMemEvent(instruction* inst );
00581 protected:
00582 virtual void preTic()=0;
00583 virtual void postTic()=0;
00584 void handleReturningStore(instruction *inst);
00585
00586
00587
00588
00589 frameID requestFrame(int size);
00590 simRegister* getFrame(frameID);
00591 void returnFrame(frameID);
00592 virtual bool insertThread(thread*);
00593
00594 void dataCacheInvalidate( simAddress addr );
00595
00596 };
00597
00598
00599 #define CREATE_VECTOR_P(P,N) (BITMAP_SET_P(P->use_spec_cv, CV_BMAP_SZ, (N)) \
00600 ? P->spec_create_vector[N] \
00601 : P->create_vector[N])
00602 #define CREATE_VECTOR(N) (BITMAP_SET_P(use_spec_cv, CV_BMAP_SZ, (N))\
00603 ? spec_create_vector[N] \
00604 : create_vector[N])
00605
00606
00607 #define CREATE_VECTOR_RT(N) (BITMAP_SET_P(use_spec_cv, CV_BMAP_SZ, (N))\
00608 ? spec_create_vector_rt[N] \
00609 : create_vector_rt[N])
00610
00611
00612 #define SET_CREATE_VECTOR(N, L) (spec_mode \
00613 ? (BITMAP_SET(use_spec_cv, CV_BMAP_SZ, (N)),\
00614 spec_create_vector[N] = (L)) \
00615 : (create_vector[N] = (L)))
00616
00617
00618 #ifdef TARGET_PPC
00619
00620 #define IS_MULT_LSQ(op) 0
00621 #else
00622 #define IS_MULT_LSQ(op) FALSE
00623 #endif
00624
00625 #endif