00001 // Copyright 2009-2010 Sandia Corporation. Under the terms 00002 // of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S. 00003 // Government retains certain rights in this software. 00004 // 00005 // Copyright (c) 2009-2010, Sandia Corporation 00006 // All rights reserved. 00007 // 00008 // This file is part of the SST software package. For license 00009 // information, see the LICENSE file in the top level directory of the 00010 // distribution. 00011 00012 #ifndef SSB_SIM_OUTORDER_OPTIONS_H 00013 #define SSB_SIM_OUTORDER_OPTIONS_H 00014 00015 /* 00016 * simulator options 00017 */ 00018 //: maximum number of inst's to execute 00019 unsigned int max_insts; 00020 //: number of insts skipped before timing starts 00021 int fastfwd_count; 00022 //: Stop fast fwding instructions until this PC is encountered 00023 word_t stop_PC; 00024 //: pipeline trace range and output filename 00025 int ptrace_nelt; 00026 char *ptrace_opts[2]; 00027 //: instruction fetch queue size (in insts) 00028 int ruu_ifq_size; 00029 //: extra branch mis-prediction latency 00030 int ruu_branch_penalty; 00031 //: speed of front-end of machine relative to execution core 00032 int fetch_speed; 00033 //: branch predictor type 00034 // nottaken,taken, perfect, bimod, or 2lev 00035 char *pred_type; 00036 //: bimodal predictor config (<table_size>) 00037 int bimod_nelt; 00038 int bimod_config[1]; 00039 //: 2-level predictor config (<l1size> <l2size> <hist_size> <xor>) 00040 int twolev_nelt; 00041 int twolev_config[4]; 00042 //: combining predictor config (<meta_table_size> 00043 int comb_nelt; 00044 int comb_config[1]; 00045 00046 //: return address stack (RAS) size 00047 int ras_size; 00048 00049 //: BTB predictor config (<num_sets> <associativity>) 00050 int btb_nelt; 00051 int btb_config[2]; 00052 00053 //: instruction decode B/W (insts/cycle) 00054 int ruu_decode_width; 00055 00056 //: instruction issue B/W (insts/cycle) 00057 int ruu_issue_width; 00058 00059 //: run pipeline with in-order issue 00060 int ruu_inorder_issue; 00061 00062 //: issue instructions down wrong execution paths 00063 int ruu_include_spec; 00064 00065 //: instruction commit B/W (insts/cycle) 00066 int ruu_commit_width; 00067 00068 //: register update unit (RUU) size 00069 int RUU_size; 00070 00071 //: load/store queue (LSQ) size 00072 int LSQ_size; 00073 00074 //: l1 data cache config 00075 // i.e., <config>|none} 00076 char *cache_dl1_opt; 00077 00078 //: l1 data cache hit latency (in cycles) 00079 int cache_dl1_lat; 00080 00081 //: l2 data cache config 00082 //i.e., <config>|none 00083 char *cache_dl2_opt; 00084 00085 //: l2 data cache hit latency (in cycles) 00086 int cache_dl2_lat; 00087 00088 //: l1 instruction cache config 00089 // i.e., <config>|dl1|dl2|none 00090 char *cache_il1_opt; 00091 00092 //: l1 instruction cache hit latency (in cycles) 00093 int cache_il1_lat; 00094 00095 //: l2 instruction cache config, 00096 // i.e., <config>|dl1|dl2|none 00097 char *cache_il2_opt; 00098 00099 //: l2 instruction cache hit latency (in cycles) 00100 int cache_il2_lat; 00101 00102 //: flush caches on system calls 00103 int flush_on_syscalls; 00104 00105 //: convert 64-bit inst addresses to 32-bit inst equivalents 00106 int compress_icache_addrs; 00107 00108 //: memory access latency (<first_chunk> <inter_chunk>) 00109 int mem_nelt; 00110 int mem_lat[2]; 00111 00112 //: memory access bus width (in bytes) 00113 int mem_bus_width; 00114 00115 //: instruction TLB config 00116 // i.e., <config>|none 00117 char *itlb_opt; 00118 00119 //: data TLB config, 00120 // i.e., <config>|none 00121 char *dtlb_opt; 00122 00123 //: inst/data TLB miss latency (in cycles) 00124 int tlb_miss_lat; 00125 00126 //: total number of integer ALU's available 00127 int res_ialu; 00128 00129 //: total number of integer multiplier/dividers available 00130 int res_imult; 00131 00132 //: total number of memory system ports available (to CPU) 00133 int res_memport; 00134 00135 //: total number of floating point ALU's available 00136 int res_fpalu; 00137 00138 //: total number of floating point multiplier/dividers available 00139 int res_fpmult; 00140 00141 //: text-based stat profiles 00142 #define MAX_PCSTAT_VARS 8 00143 int pcstat_nelt; 00144 char *pcstat_vars[MAX_PCSTAT_VARS]; 00145 00146 #endif