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sst/core/techModels/libORION/SIM_array.h

00001 /*-------------------------------------------------------------------------
00002  *                             ORION 2.0 
00003  *
00004  *                                              Copyright 2009 
00005  *      Princeton University, and Regents of the University of California 
00006  *                         All Rights Reserved
00007  *
00008  *                         
00009  *  ORION 2.0 was developed by Bin Li at Princeton University and Kambiz Samadi at
00010  *  University of California, San Diego. ORION 2.0 was built on top of ORION 1.0. 
00011  *  ORION 1.0 was developed by Hangsheng Wang, Xinping Zhu and Xuning Chen at 
00012  *  Princeton University.
00013  *
00014  *  If your use of this software contributes to a published paper, we
00015  *  request that you cite our paper that appears on our website 
00016  *  http://www.princeton.edu/~peh/orion.html
00017  *
00018  *  Permission to use, copy, and modify this software and its documentation is
00019  *  granted only under the following terms and conditions.  Both the
00020  *  above copyright notice and this permission notice must appear in all copies
00021  *  of the software, derivative works or modified versions, and any portions
00022  *  thereof, and both notices must appear in supporting documentation.
00023  *
00024  *  This software may be distributed (but not offered for sale or transferred
00025  *  for compensation) to third parties, provided such third parties agree to
00026  *  abide by the terms and conditions of this notice.
00027  *
00028  *  This software is distributed in the hope that it will be useful to the
00029  *  community, but WITHOUT ANY WARRANTY; without even the implied warranty of
00030  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
00031  *
00032  *-----------------------------------------------------------------------*/
00033 
00034 #ifndef _SIM_POWER_ARRAY_H
00035 #define _SIM_POWER_ARRAY_H
00036 
00037 #include <sys/types.h>
00038 
00039 #include "SIM_parameter.h"
00040 #include "SIM_array_internal.h"
00041 #include "SIM_misc.h"
00042 
00043 typedef struct {
00044         SIM_array_dec_t row_dec;
00045         SIM_array_dec_t col_dec;
00046         SIM_array_wordline_t data_wordline;
00047         SIM_array_wordline_t tag_wordline;
00048         SIM_array_bitline_t data_bitline;
00049         SIM_array_bitline_t tag_bitline;
00050         SIM_array_mem_t data_mem;
00051         /* tag address memory cells */
00052         SIM_array_mem_t tag_mem;
00053         /* tag various bits memory cells, different with tag_mem for fully-associative cache */
00054         SIM_array_mem_t tag_attach_mem;
00055         SIM_array_amp_t data_amp;
00056         SIM_array_amp_t tag_amp;
00057         SIM_array_comp_t comp;
00058         SIM_array_mux_t mux;
00059         SIM_array_out_t outdrv;
00060         SIM_array_pre_t row_dec_pre;
00061         SIM_array_pre_t col_dec_pre;
00062         SIM_array_pre_t data_bitline_pre;
00063         SIM_array_pre_t tag_bitline_pre;
00064         SIM_array_pre_t data_colsel_pre;
00065         SIM_array_pre_t tag_colsel_pre;
00066         SIM_array_pre_t comp_pre;
00067         SIM_ff_t ff;
00068         double I_static;
00069 } SIM_array_t;
00070 
00071 typedef struct {
00072         /*array type parameter*/
00073         int arr_buf_type;
00074         /* parameters shared by data array and tag array */
00075         int share_rw;
00076         u_int read_ports;
00077         u_int write_ports;
00078         u_int n_set;
00079         u_int blk_bits;
00080         u_int assoc;
00081         int row_dec_model;
00082         /* parameters specific to data array */
00083         u_int data_width;
00084         int col_dec_model;
00085         int mux_model;
00086         int outdrv_model;
00087         /* parameters specific to tag array */
00088         u_int tag_addr_width;
00089         u_int tag_line_width;
00090         int comp_model;
00091         /* data set of common parameters */
00092         u_int data_ndwl;
00093         u_int data_ndbl;
00094         u_int data_nspd;
00095         u_int data_n_share_amp;
00096         u_int data_end;
00097         int data_wordline_model;
00098         int data_bitline_model;
00099         int data_amp_model;
00100         int data_mem_model;
00101         /* tag set of common parameters */
00102         u_int tag_ndwl;
00103         u_int tag_ndbl;
00104         u_int tag_nspd;
00105         u_int tag_n_share_amp;
00106         u_int tag_end;
00107         int tag_wordline_model;
00108         int tag_bitline_model;
00109         int tag_amp_model;
00110         int tag_mem_model;
00111         int tag_attach_mem_model;
00112         /* parameters for precharging */
00113         int row_dec_pre_model;
00114         int col_dec_pre_model;
00115         int data_bitline_pre_model;
00116         int tag_bitline_pre_model;
00117         int data_colsel_pre_model;
00118         int tag_colsel_pre_model;
00119         int comp_pre_model;
00120         /* some redundant fields */
00121         u_int n_item;           /* # of items in a block */
00122         u_int eff_data_cols;    /* # of data columns driven by one wordline */
00123         u_int eff_tag_cols;     /* # of tag columns driven by one wordline */
00124         /* flags used by prototype array model */
00125         u_int use_bit_width;
00126         u_int valid_bit_width;
00127         int write_policy;       /* 1 if write back (have dirty bits), 0 otherwise */
00128         /* call back functions */
00129         /* these fields have no physical counterparts, they are
00130          * here just because this is the most convenient place */
00131         u_int (*get_entry_valid_bit)( void* );
00132         u_int (*get_entry_dirty_bit)( void* );
00133         u_int (*get_set_use_bit)( void*, int );
00134         LIB_Type_max_uint (*get_entry_tag)( void* );
00135         LIB_Type_max_uint (*get_set_tag)( void*, int );
00136         /* fields which will be filled by initialization */
00137         double data_arr_width;
00138         double tag_arr_width;
00139         double data_arr_height;
00140         double tag_arr_height;
00141 } SIM_array_info_t;
00142 
00143 /*@
00144  * data type: array port state
00145  * 
00146  *  - row_addr       -- input to row decoder
00147  *    col_addr       -- input to column decoder, if any
00148  *    tag_addr       -- input to tag comparator
00149  * $+ tag_line       -- value of tag bitline
00150  *  # data_line_size -- size of data_line in char
00151  *  # data_line      -- value of data bitline
00152  *
00153  * legend:
00154  *   -: only used by non-fully-associative array
00155  *   +: only used by fully-associative array
00156  *   #: only used by fully-associative array or RF array
00157  *   $: only used by write-through array
00158  *
00159  * NOTE:
00160  *   (1) *_addr may not necessarily be an address
00161  *   (2) data_line_size is the allocated size of data_line in simulator,
00162  *       which must be no less than the physical size of data line
00163  *   (3) each instance of module should define an instance-specific data
00164  *       type with non-zero-length data_line and cast it to this type
00165  */
00166 typedef struct {
00167         LIB_Type_max_uint row_addr;
00168         LIB_Type_max_uint col_addr;
00169         LIB_Type_max_uint tag_addr;
00170         LIB_Type_max_uint tag_line;
00171         u_int data_line_size;
00172         char data_line[0];
00173 } SIM_array_port_state_t;
00174 
00175 /*@
00176  * data type: array set state
00177  * 
00178  *   entry           -- pointer to some entry structure if an entry is selected for
00179  *                      r/w, NULL otherwise
00180  *   entry_set       -- pointer to corresponding set structure
00181  * + write_flag      -- 1 if entry is already written once, 0 otherwise
00182  * + write_back_flag -- 1 if entry is already written back, 0 otherwise
00183  *   valid_bak       -- valid bit of selected entry before operation
00184  *   dirty_bak       -- dirty bit of selected entry, if any, before operation
00185  *   tag_bak         -- tag of selected entry before operation
00186  *   use_bak         -- use bits of all entries before operation
00187  *
00188  * legend:
00189  *   +: only used by fully-associative array
00190  *
00191  * NOTE:
00192  *   (1) entry is interpreted by modules, if some module has no "entry structure",
00193  *       then make sure this field is non-zero if some entry is selected
00194  *   (2) tag_addr may not necessarily be an address
00195  *   (3) each instance of module should define an instance-specific data
00196  *       type with non-zero-length use_bit and cast it to this type
00197  */
00198 typedef struct {
00199         void *entry;
00200         void *entry_set;
00201         int write_flag;
00202         int write_back_flag;
00203         u_int valid_bak;
00204         u_int dirty_bak;
00205         LIB_Type_max_uint tag_bak;
00206         u_int use_bak[0];
00207 } SIM_array_set_state_t;
00208 
00209 
00210 /* ==================== function prototypes ==================== */
00211 /* prototype-level record functions */
00212 extern int SIM_array_dec(SIM_array_info_t *info, SIM_array_t *arr, SIM_array_port_state_t *port, LIB_Type_max_uint row_addr, int rw );
00213 extern int SIM_array_data_read(SIM_array_info_t *info, SIM_array_t *arr, LIB_Type_max_uint data );
00214 extern int SIM_array_data_write(SIM_array_info_t *info, SIM_array_t *arr, SIM_array_set_state_t *set, u_int n_item, u_char *data_line, u_char *old_data, u_char *new_data );
00215 extern int SIM_array_tag_read(SIM_array_info_t *info, SIM_array_t *arr, SIM_array_set_state_t *set );
00216 extern int SIM_array_tag_update(SIM_array_info_t *info, SIM_array_t *arr, SIM_array_port_state_t *port, SIM_array_set_state_t *set );
00217 extern int SIM_array_tag_compare(SIM_array_info_t *info, SIM_array_t *arr, SIM_array_port_state_t *port, LIB_Type_max_uint tag_input, LIB_Type_max_uint col_addr, SIM_array_set_state_t *set );
00218 extern int SIM_array_output(SIM_array_info_t *info, SIM_array_t *arr, u_int data_size, u_int length, void *data_out, void *data_all );
00219 
00220 /* state manupilation functions */
00221 extern int SIM_array_port_state_init(SIM_array_info_t *info, SIM_array_port_state_t *port );
00222 extern int SIM_array_set_state_init(SIM_array_info_t *info, SIM_array_set_state_t *set );
00223 
00224 extern int SIM_array_init(SIM_array_info_t *info, int is_fifo, u_int n_read_port, u_int n_write_port, u_int n_entry, u_int line_width, int outdrv, int arr_buf_type);
00225 
00226 extern int SIM_array_power_init(SIM_array_info_t *info, SIM_array_t *arr );
00227 extern double SIM_array_power_report(SIM_array_info_t *info, SIM_array_t *arr );
00228 extern int SIM_array_clear_stat(SIM_array_t *arr);
00229 
00230 extern double SIM_array_stat_energy(SIM_array_info_t *info, SIM_array_t *arr, double n_read, double n_write, int print_depth, char *path, int max_avg);
00231 
00232 #endif  /* _SIM_POWER_ARRAY_H */

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