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00049 #ifndef BASIC_COMPONENTS_H_
00050 #define BASIC_COMPONENTS_H_
00051
00052 #include "XML_Parse.h"
00053 #include "parameter.h"
00054 #include <vector>
00055
00056 const double cdb_overhead = 1.1;
00057
00058 enum FU_type {
00059 FPU,
00060 ALU,
00061 MUL
00062 };
00063
00064 enum Core_type {
00065 OOO,
00066 Inorder
00067 };
00068
00069 enum Renaming_type {
00070 RAMbased,
00071 CAMbased
00072 };
00073
00074 enum Scheduler_type {
00075 PhysicalRegFile,
00076 ReservationStation
00077 };
00078
00079 enum cache_level {
00080 L2,
00081 L3,
00082 L1Directory,
00083 L2Directory
00084 };
00085
00086 enum Dir_type {
00087 ST,
00088 DC,
00089 NonDir
00090
00091 };
00092
00093 enum Cache_policy {
00094 Write_through,
00095 Write_back
00096 };
00097
00098 enum Device_ty {
00099 Core_device,
00100 Uncore_device,
00101 LLC_device
00102 };
00103
00104 class statsComponents
00105 {
00106 public:
00107 double access;
00108 double hit;
00109 double miss;
00110
00111 statsComponents() : access(0), hit(0), miss(0) {}
00112 statsComponents(const statsComponents & obj) { *this = obj; }
00113 statsComponents & operator=(const statsComponents & rhs)
00114 {
00115 access = rhs.access;
00116 hit = rhs.hit;
00117 miss = rhs.miss;
00118 return *this;
00119 }
00120 void reset() { access = 0; hit = 0; miss = 0;}
00121
00122 friend statsComponents operator+(const statsComponents & x, const statsComponents & y);
00123 friend statsComponents operator*(const statsComponents & x, double const * const y);
00124 };
00125
00126 class statsDef
00127 {
00128 public:
00129 statsComponents readAc;
00130 statsComponents writeAc;
00131 statsComponents searchAc;
00132
00133 statsDef() : readAc(), writeAc(),searchAc() { }
00134 void reset() { readAc.reset(); writeAc.reset();searchAc.reset();}
00135
00136 friend statsDef operator+(const statsDef & x, const statsDef & y);
00137 friend statsDef operator*(const statsDef & x, double const * const y);
00138 };
00139
00140 double longer_channel_device_reduction(
00141 enum Device_ty device_ty=Core_device,
00142 enum Core_type core_ty=Inorder);
00143
00144 class CoreDynParam {
00145 public:
00146 CoreDynParam(){};
00147 CoreDynParam(ParseXML *XML_interface, int ithCore_);
00148
00149
00150
00151
00152
00153
00154
00155
00156
00157
00158
00159
00160
00161
00162 bool opt_local;
00163 bool x86;
00164 enum Core_type core_ty;
00165 enum Renaming_type rm_ty;
00166 enum Scheduler_type scheu_ty;
00167 double clockRate,executionTime;
00168 int arch_ireg_width, arch_freg_width, phy_ireg_width, phy_freg_width;
00169 int num_IRF_entry, num_FRF_entry, num_ifreelist_entries, num_ffreelist_entries;
00170 int fetchW, decodeW,issueW,peak_issueW, commitW,peak_commitW, predictionW, fp_issueW, fp_decodeW;
00171 int perThreadState, globalCheckpoint, instruction_length, pc_width, opcode_length, micro_opcode_length;
00172 int num_hthreads, pipeline_stages, fp_pipeline_stages, num_pipelines, num_fp_pipelines;
00173 int num_alus, num_muls;
00174 double num_fpus;
00175 int int_data_width, fp_data_width,v_address_width, p_address_width;
00176 double pipeline_duty_cycle, total_cycles, busy_cycles, idle_cycles;
00177 bool regWindowing,multithreaded;
00178 double pppm_lkg_multhread[4];
00179 double IFU_duty_cycle,LSU_duty_cycle,MemManU_I_duty_cycle,
00180 MemManU_D_duty_cycle, ALU_duty_cycle,MUL_duty_cycle,
00181 FPU_duty_cycle, ALU_cdb_duty_cycle,MUL_cdb_duty_cycle,
00182 FPU_cdb_duty_cycle;
00183 ~CoreDynParam(){};
00184 };
00185
00186 class CacheDynParam {
00187 public:
00188 CacheDynParam(){};
00189 CacheDynParam(ParseXML *XML_interface, int ithCache_);
00190 string name;
00191 enum Dir_type dir_ty;
00192 double clockRate,executionTime;
00193 double capacity, blockW, assoc, nbanks;
00194 double throughput, latency;
00195
00196 double duty_cycle;
00197 int missb_size, fu_size, prefetchb_size, wbb_size;
00198 ~CacheDynParam(){};
00199 };
00200
00201 class MCParam {
00202 public:
00203 MCParam(){};
00204 MCParam(ParseXML *XML_interface, int ithCache_);
00205 string name;
00206 double clockRate;
00207
00208
00209
00210 int llcBlockSize, dataBusWidth, addressBusWidth;
00211 int opcodeW;
00212 int peakDataTransferRate,memAccesses;
00213 int memRank,num_channels, num_mcs;
00214 double frontend_duty_cycle;
00215 double executionTime, reads, writes;
00216
00217 ~MCParam(){};
00218 };
00219
00220 class NoCParam {
00221 public:
00222 NoCParam(){};
00223 NoCParam(ParseXML *XML_interface, int ithCache_);
00224 string name;
00225 double clockRate;
00226 int flit_size;
00227 int input_ports, output_ports, min_ports, global_linked_ports;
00228 int virtual_channel_per_port,input_buffer_entries_per_vc;
00229 int horizontal_nodes,vertical_nodes, total_nodes;
00230 double executionTime, total_access, link_throughput,link_latency,
00231 duty_cycle, chip_coverage, route_over_perc;
00232
00233 double link_length;
00234
00235 bool has_global_link, type;
00236
00237 ~NoCParam(){};
00238 };
00239
00240 class ProcParam {
00241 public:
00242 ProcParam(){};
00243 ProcParam(ParseXML *XML_interface, int ithCache_);
00244 string name;
00245 int numCore, numL2, numL3, numNOC, numL1Dir, numL2Dir,numMC, numMCChannel;
00246 bool homoCore, homoL2, homoL3, homoNOC, homoL1Dir, homoL2Dir;
00247
00248 ~ProcParam(){};
00249 };
00250
00251 #endif