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sst/core/techModels/libsim-panalyzer/armemu.h

00001 /*  armemu.h -- ARMulator emulation macros:  ARM6 Instruction Emulator.
00002     Copyright (C) 1994 Advanced RISC Machines Ltd.
00003  
00004     This program is free software; you can redistribute it and/or modify
00005     it under the terms of the GNU General Public License as published by
00006     the Free Software Foundation; either version 2 of the License, or
00007     (at your option) any later version.
00008  
00009     This program is distributed in the hope that it will be useful,
00010     but WITHOUT ANY WARRANTY; without even the implied warranty of
00011     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012     GNU General Public License for more details.
00013  
00014     You should have received a copy of the GNU General Public License
00015     along with this program; if not, write to the Free Software
00016     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
00017 
00018 extern ARMword isize;
00019 
00020 /***************************************************************************\
00021 *                           Condition code values                           *
00022 \***************************************************************************/
00023 
00024 #define EQ 0
00025 #define NE 1
00026 #define CS 2
00027 #define CC 3
00028 #define MI 4
00029 #define PL 5
00030 #define VS 6
00031 #define VC 7
00032 #define HI 8
00033 #define LS 9
00034 #define GE 10
00035 #define LT 11
00036 #define GT 12
00037 #define LE 13
00038 #define AL 14
00039 #define NV 15
00040 
00041 /***************************************************************************\
00042 *                               Shift Opcodes                               *
00043 \***************************************************************************/
00044 
00045 #define LSL 0
00046 #define LSR 1
00047 #define ASR 2
00048 #define ROR 3
00049 
00050 /***************************************************************************\
00051 *               Macros to twiddle the status flags and mode                 *
00052 \***************************************************************************/
00053 
00054 #define NBIT ((unsigned)1L << 31)
00055 #define ZBIT (1L << 30)
00056 #define CBIT (1L << 29)
00057 #define VBIT (1L << 28)
00058 #define IBIT (1L << 7)
00059 #define FBIT (1L << 6)
00060 #define IFBITS (3L << 6)
00061 #define R15IBIT (1L << 27)
00062 #define R15FBIT (1L << 26)
00063 #define R15IFBITS (3L << 26)
00064 
00065 #define POS(i) ( (~(i)) >> 31 )
00066 #define NEG(i) ( (i) >> 31 )
00067 
00068 #ifdef MODET                    /* Thumb support */
00069 /* ??? This bit is actually in the low order bit of the PC in the hardware.
00070    It isn't clear if the simulator needs to model that or not.  */
00071 #define TBIT (1L << 5)
00072 #define TFLAG state->TFlag
00073 #define SETT state->TFlag = 1
00074 #define CLEART state->TFlag = 0
00075 #define ASSIGNT(res) state->TFlag = res
00076 #endif
00077 
00078 #define NFLAG state->NFlag
00079 #define SETN state->NFlag = 1
00080 #define CLEARN state->NFlag = 0
00081 #define ASSIGNN(res) state->NFlag = res
00082 
00083 #define ZFLAG state->ZFlag
00084 #define SETZ state->ZFlag = 1
00085 #define CLEARZ state->ZFlag = 0
00086 #define ASSIGNZ(res) state->ZFlag = res
00087 
00088 #define CFLAG state->CFlag
00089 #define SETC state->CFlag = 1
00090 #define CLEARC state->CFlag = 0
00091 #define ASSIGNC(res) state->CFlag = res
00092 
00093 #define VFLAG state->VFlag
00094 #define SETV state->VFlag = 1
00095 #define CLEARV state->VFlag = 0
00096 #define ASSIGNV(res) state->VFlag = res
00097 
00098 
00099 #define IFLAG (state->IFFlags >> 1)
00100 #define FFLAG (state->IFFlags & 1)
00101 #define IFFLAGS state->IFFlags
00102 #define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
00103 #define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
00104 
00105 #define CCBITS (0xf0000000L)
00106 #define INTBITS (0xc0L)
00107 
00108 #if defined MODET && defined MODE32
00109 #define PCBITS (0xffffffffL)
00110 #else
00111 #define PCBITS (0xfffffffcL)
00112 #endif
00113 
00114 #define MODEBITS (0x1fL)
00115 #define R15INTBITS (3L << 26)
00116 
00117 #if defined MODET && defined MODE32
00118 #define R15PCBITS (0x03ffffffL)
00119 #else
00120 #define R15PCBITS (0x03fffffcL)
00121 #endif
00122 
00123 #define R15PCMODEBITS (0x03ffffffL)
00124 #define R15MODEBITS (0x3L)
00125 
00126 #ifdef MODE32
00127 #define PCMASK PCBITS
00128 #define PCWRAP(pc) (pc)
00129 #else
00130 #define PCMASK R15PCBITS
00131 #define PCWRAP(pc) ((pc) & R15PCBITS)
00132 #endif
00133 
00134 #define PC (state->Reg[15] & PCMASK)
00135 #define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
00136 #define R15INT (state->Reg[15] & R15INTBITS)
00137 #define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
00138 #define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
00139 #define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
00140 #define R15PC (state->Reg[15] & R15PCBITS)
00141 #define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
00142 #define R15MODE (state->Reg[15] & R15MODEBITS)
00143 
00144 #define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28))
00145 #define EINT (IFFLAGS << 6)
00146 #define ER15INT (IFFLAGS << 26)
00147 #define EMODE (state->Mode)
00148 
00149 #ifdef MODET
00150 #define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
00151 #else
00152 #define CPSR (ECC | EINT | EMODE)
00153 #endif
00154 
00155 #ifdef MODE32
00156 #define PATCHR15
00157 #else
00158 #define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
00159 #endif
00160 
00161 #define GETSPSR(bank) bank>0?state->Spsr[bank]:ECC | EINT | EMODE ;
00162 #define SETPSR(d,s) d = (s) & (ARMword)(CCBITS | INTBITS | MODEBITS)
00163 #define SETINTMODE(d,s) d = ((d) & CCBITS) | ((s) & (INTBITS | MODEBITS))
00164 #define SETCC(d,s) d = ((d) & (INTBITS | MODEBITS)) | ((s) & CCBITS)
00165 #define SETR15PSR(s) if (state->Mode == USER26MODE) { \
00166                         state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE ; \
00167                         ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
00168                         ASSIGNZ((state->Reg[15] & ZBIT) != 0) ; \
00169                         ASSIGNC((state->Reg[15] & CBIT) != 0) ; \
00170                         ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
00171                         } \
00172                      else { \
00173                         state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)) ; \
00174                         ARMul_R15Altered (state) ; \
00175                         }
00176 #define SETABORT(i,m) state->Cpsr = ECC | EINT | (i) | (m)
00177 
00178 #ifndef MODE32
00179 #define VECTORS 0x20
00180 #define LEGALADDR 0x03ffffff
00181 #define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
00182 #define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
00183 #endif
00184 
00185 #define INTERNALABORT(address) if (address < VECTORS) \
00186                                   state->Aborted = ARMul_DataAbortV ; \
00187                                else \
00188                                   state->Aborted = ARMul_AddrExceptnV ;
00189 
00190 #ifdef MODE32
00191 #define TAKEABORT ARMul_Abort(state,ARMul_DataAbortV)
00192 #else
00193 #define TAKEABORT if (state->Aborted == ARMul_AddrExceptnV) \
00194                      ARMul_Abort(state,ARMul_AddrExceptnV) ; \
00195                   else \
00196                      ARMul_Abort(state,ARMul_DataAbortV)
00197 #endif
00198 #define CPTAKEABORT if (!state->Aborted) \
00199                        ARMul_Abort(state,ARMul_UndefinedInstrV) ; \
00200                     else if (state->Aborted == ARMul_AddrExceptnV) \
00201                        ARMul_Abort(state,ARMul_AddrExceptnV) ; \
00202                     else \
00203                        ARMul_Abort(state,ARMul_DataAbortV)
00204 
00205 
00206 /***************************************************************************\
00207 *               Different ways to start the next instruction                *
00208 \***************************************************************************/
00209 
00210 #define SEQ 0
00211 #define NONSEQ 1
00212 #define PCINCEDSEQ 2
00213 #define PCINCEDNONSEQ 3
00214 #define PRIMEPIPE 4
00215 #define RESUME 8
00216 
00217 #define NORMALCYCLE state->NextInstr = 0
00218 #define BUSUSEDN state->NextInstr |= 1  /* the next fetch will be an N cycle */
00219 #define BUSUSEDINCPCS state->Reg[15] += isize ; /* a standard PC inc and an S cycle */ \
00220                       state->NextInstr = (state->NextInstr & 0xff) | 2
00221 #define BUSUSEDINCPCN state->Reg[15] += isize ; /* a standard PC inc and an N cycle */ \
00222                       state->NextInstr |= 3
00223 #define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
00224               state->NextInstr |= 2
00225 #define FLUSHPIPE state->NextInstr |= PRIMEPIPE
00226 
00227 /***************************************************************************\
00228 *                          Cycle based emulation                            *
00229 \***************************************************************************/
00230 
00231 #define OUTPUTCP(i,a,b)
00232 #define NCYCLE
00233 #define SCYCLE
00234 #define ICYCLE
00235 #define CCYCLE
00236 #define NEXTCYCLE(c)
00237 
00238 /***************************************************************************\
00239 *                 States of the cycle based state machine                   *
00240 \***************************************************************************/
00241 
00242 
00243 /***************************************************************************\
00244 *                 Macros to extract parts of instructions                   *
00245 \***************************************************************************/
00246 
00247 #define DESTReg (BITS(12,15))
00248 #define LHSReg (BITS(16,19))
00249 #define RHSReg (BITS(0,3))
00250 
00251 #define DEST (state->Reg[DESTReg])
00252 
00253 #ifdef MODE32
00254 #ifdef MODET
00255 #define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
00256 #else
00257 #define LHS (state->Reg[LHSReg])
00258 #endif
00259 #else
00260 #define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]) )
00261 #endif
00262 
00263 #define MULDESTReg (BITS(16,19))
00264 #define MULLHSReg (BITS(0,3))
00265 #define MULRHSReg (BITS(8,11))
00266 #define MULACCReg (BITS(12,15))
00267 
00268 #define DPImmRHS (ARMul_ImmedTable[BITS(0,11)])
00269 #define DPSImmRHS temp = BITS(0,11) ; \
00270                   rhs = ARMul_ImmedTable[temp] ; \
00271                   if (temp > 255) /* there was a shift */ \
00272                      ASSIGNC(rhs >> 31) ;
00273 
00274 #ifdef MODE32
00275 #define DPRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
00276                                   : GetDPRegRHS(state, instr))
00277 #define DPSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
00278                                    : GetDPSRegRHS(state, instr))
00279 #else
00280 #define DPRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
00281                                   : GetDPRegRHS(state, instr))
00282 #define DPSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
00283                                    : GetDPSRegRHS(state, instr))
00284 #endif
00285 
00286 #define LSBase state->Reg[LHSReg]
00287 #define LSImmRHS (BITS(0,11))
00288 
00289 #ifdef MODE32
00290 #define LSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
00291                                   : GetLSRegRHS(state, instr))
00292 #else
00293 #define LSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
00294                                   : GetLSRegRHS(state, instr))
00295 #endif
00296 
00297 #define LSMNumRegs ((ARMword)ARMul_BitList[BITS(0,7)] + \
00298                     (ARMword)ARMul_BitList[BITS(8,15)] )
00299 #define LSMBaseFirst ((LHSReg == 0 && BIT(0)) || \
00300                       (BIT(LHSReg) && BITS(0,LHSReg-1) == 0))
00301 
00302 #define SWAPSRC (state->Reg[RHSReg])
00303 
00304 #define LSCOff (BITS(0,7) << 2)
00305 #define CPNum BITS(8,11)
00306 
00307 /***************************************************************************\
00308 *                    Macro to rotate n right by b bits                      *
00309 \***************************************************************************/
00310 
00311 #define ROTATER(n,b) (((n)>>(b))|((n)<<(32-(b))))
00312 
00313 /***************************************************************************\
00314 *                 Macros to store results of instructions                   *
00315 \***************************************************************************/
00316 
00317 #define WRITEDEST(d) if (DESTReg==15) \
00318                         WriteR15(state, d) ; \
00319                      else \
00320                           DEST = d
00321 
00322 #define WRITESDEST(d) if (DESTReg == 15) \
00323                          { return 0; WriteSR15(state, d); } \
00324                       else { \
00325                          DEST = d ; \
00326                          ARMul_NegZero(state, d) ; \
00327                          }
00328 
00329 #define BYTETOBUS(data) ((data & 0xff) | \
00330                         ((data & 0xff) << 8) | \
00331                         ((data & 0xff) << 16) | \
00332                         ((data & 0xff) << 24))
00333 #define BUSTOBYTE(address,data) \
00334            if (state->bigendSig) \
00335               temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff ; \
00336            else \
00337               temp = (data >> ((address & 3) << 3)) & 0xff
00338 
00339 #define LOADMULT(instr,address,wb) LoadMult(state,instr,address,wb)
00340 #define LOADSMULT(instr,address,wb) LoadSMult(state,instr,address,wb)
00341 #define STOREMULT(instr,address,wb) StoreMult(state,instr,address,wb)
00342 #define STORESMULT(instr,address,wb) StoreSMult(state,instr,address,wb)
00343 
00344 #define POSBRANCH ((instr & 0x7fffff) << 2)
00345 #define NEGBRANCH (0xfc000000 | ((instr & 0xffffff) << 2))
00346 
00347 /***************************************************************************\
00348 *                          Values for Emulate                               *
00349 \***************************************************************************/
00350 
00351 #define STOP            0       /* stop */
00352 #define CHANGEMODE      1       /* change mode */
00353 #define ONCE            2       /* execute just one interation */
00354 #define RUN             3       /* continuous execution */
00355 
00356 /***************************************************************************\
00357 *                      Stuff that is shared across modes                    *
00358 \***************************************************************************/
00359 
00360 extern ARMword ARMul_Emulate26 (ARMul_State * state);
00361 extern int ARMul_Emulate32 (ARMword pc, ARMword instr, ARMul_State * state);
00362 extern unsigned ARMul_MultTable[];      /* Number of I cycles for a mult */
00363 extern ARMword ARMul_ImmedTable[];      /* immediate DP LHS values */
00364 extern char ARMul_BitList[];    /* number of bits in a byte table */
00365 extern void ARMul_Abort26 (ARMul_State * state, ARMword);
00366 extern void ARMul_Abort32 (ARMul_State * state, ARMword);
00367 extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
00368 extern void ARMul_MSRCpsr (ARMul_State * state, ARMword instr, ARMword rhs);
00369 extern void ARMul_NegZero (ARMul_State * state, ARMword result);
00370 extern void ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b,
00371                             ARMword result);
00372 extern int AddOverflow (ARMword a, ARMword b, ARMword result);
00373 extern int SubOverflow (ARMword a, ARMword b, ARMword result);
00374 extern void ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b,
00375                                ARMword result);
00376 extern void ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b,
00377                             ARMword result);
00378 extern void ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b,
00379                                ARMword result);
00380 extern void ARMul_CPSRAltered (ARMul_State * state);
00381 extern void ARMul_R15Altered (ARMul_State * state);
00382 extern ARMword ARMul_SwitchMode (ARMul_State * state, ARMword oldmode,
00383                                  ARMword newmode);
00384 extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
00385 extern void ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address);
00386 extern void ARMul_STC (ARMul_State * state, ARMword instr, ARMword address);
00387 extern void ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source);
00388 extern ARMword ARMul_MRC (ARMul_State * state, ARMword instr);
00389 extern void ARMul_CDP (ARMul_State * state, ARMword instr);
00390 extern unsigned IntPending (ARMul_State * state);
00391 extern ARMword ARMul_Align (ARMul_State * state, ARMword address,
00392                             ARMword data);
00393 #define EVENTLISTSIZE 1024L
00394 
00395 /* Thumb support: */
00396 
00397 typedef enum
00398 {
00399   t_undefined,                  /* undefined Thumb instruction */
00400   t_decoded,                    /* instruction decoded to ARM equivalent */
00401   t_branch                      /* Thumb branch (already processed) */
00402 }
00403 tdstate;
00404 
00405 extern tdstate ARMul_ThumbDecode (ARMul_State * state, ARMword pc,
00406                                   ARMword tinstr, ARMword * ainstr);
00407 
00408 /***************************************************************************\
00409 *                      Macros to scrutinize instructions                    *
00410 \***************************************************************************/
00411 
00412 
00413 #define UNDEF_Test
00414 #define UNDEF_Shift
00415 #define UNDEF_MSRPC
00416 #define UNDEF_MRSPC
00417 #define UNDEF_MULPCDest
00418 #define UNDEF_MULDestEQOp1
00419 #define UNDEF_LSRBPC
00420 #define UNDEF_LSRBaseEQOffWb
00421 #define UNDEF_LSRBaseEQDestWb
00422 #define UNDEF_LSRPCBaseWb
00423 #define UNDEF_LSRPCOffWb
00424 #define UNDEF_LSMNoRegs
00425 #define UNDEF_LSMPCBase
00426 #define UNDEF_LSMUserBankWb
00427 #define UNDEF_LSMBaseInListWb
00428 #define UNDEF_SWPPC
00429 #define UNDEF_CoProHS
00430 #define UNDEF_MCRPC
00431 #define UNDEF_LSCPCBaseWb
00432 #define UNDEF_UndefNotBounced
00433 #define UNDEF_ShortInt
00434 #define UNDEF_IllegalMode
00435 #define UNDEF_Prog32SigChange
00436 #define UNDEF_Data32SigChange

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