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00013 #ifndef _DRAMSIMC_H
00014 #define _DRAMSIMC_H
00015
00016 #include <sst/core/log.h>
00017 #include <sst/core/eventFunctor.h>
00018 #include <sst/core/component.h>
00019 #include <memoryChannel.h>
00020 #include <MemorySystem.h>
00021
00022 using namespace std;
00023 using namespace SST;
00024
00025 #ifndef DRAMSIMC_DBG
00026 #define DRAMSIMC_DBG 0
00027 #endif
00028
00029 class DRAMSimC : public Component {
00030
00031 public:
00032
00033 DRAMSimC( ComponentId_t id, Params_t& params );
00034 int Finish();
00035
00036 private:
00037
00038 typedef MemoryChannel<uint64_t> memChan_t;
00039
00040 private:
00041
00042 DRAMSimC( const DRAMSimC& c );
00043 bool clock( Cycle_t );
00044
00045 inline DRAMSim::TransactionType
00046 convertType( memChan_t::event_t::reqType_t type );
00047
00048 void readData(uint id, uint64_t addr, uint64_t clockcycle);
00049 void writeData(uint id, uint64_t addr, uint64_t clockcycle);
00050
00051 std::deque<Transaction> m_transQ;
00052 MemorySystem* m_memorySystem;
00053 memChan_t* m_memChan;
00054 std::string m_printStats;
00055 Log< DRAMSIMC_DBG >& m_dbg;
00056 Log<>& m_log;
00057
00058 #if WANT_CHECKPOINT_SUPPORT
00059 BOOST_SERIALIZE {
00060 _AR_DBG(DRAMSimC,"start\n");
00061 BOOST_VOID_CAST_REGISTER( DRAMSimC*, Component* );
00062 ar & BOOST_SERIALIZATION_BASE_OBJECT_NVP( Component );
00063 ar & BOOST_SERIALIZATION_NVP( bus );
00064 _AR_DBG(DRAMSimC,"done\n");
00065 }
00066 SAVE_CONSTRUCT_DATA( DRAMSimC ) {
00067 _AR_DBG(DRAMSimC,"\n");
00068 ComponentId_t id = t->_id;
00069 Clock* clock = t->_clock;
00070 Params_t params = t->params;
00071 ar << BOOST_SERIALIZATION_NVP( id );
00072 ar << BOOST_SERIALIZATION_NVP( clock );
00073 ar << BOOST_SERIALIZATION_NVP( params );
00074 }
00075 LOAD_CONSTRUCT_DATA( DRAMSimC ) {
00076 _AR_DBG(DRAMSimC,"\n");
00077 ComponentId_t id;
00078 Clock* clock;
00079 Params_t params;
00080 ar >> BOOST_SERIALIZATION_NVP( id );
00081 ar >> BOOST_SERIALIZATION_NVP( clock );
00082 ar >> BOOST_SERIALIZATION_NVP( params );
00083 ::new(t)DRAMSimC( id, clock, params );
00084 }
00085 #endif
00086 };
00087
00088 inline DRAMSim::TransactionType
00089 DRAMSimC::convertType( memChan_t::event_t::reqType_t type )
00090 {
00091 switch( type ) {
00092 case memChan_t::event_t::READ:
00093 return DRAMSim::DATA_READ;
00094 case memChan_t::event_t::WRITE:
00095 return DRAMSim::DATA_WRITE;
00096 default: ;
00097 }
00098 return (DRAMSim::TransactionType)-1;
00099 }
00100
00101 #endif