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sst/core/techModels/libIntSim/parameters.h

00001 /*
00002         This simulator is C/C++ version of IntSim.
00003 
00004         Original copy was developed by D. Sekar, R. Venkatesan, R. Sarvari, K. Shakeri,
00005         J. Davis, and Prof. J. Meindl from Microelectronics Research Center,
00006         Georgia Tech, Atlanta, GA.
00007         
00008         Reference: D. Sekar, "Optimal Signal, Power, Clock, and Thermal Interconnect
00009         Networks for High-Performance 2D and 3D Integrated Circuits," Ph.D. Dissertation,
00010         School of ECE, Georgia Tech, Atlanta, GA, 2008.
00011 
00012         Copyright 2009
00013         William Song, Prof. Sudhakar Yalamanchili, and Prof. Saibal Mukhopadhyay
00014         Georgia Tech Research Corporation, Atlanta, GA 30332
00015 */
00016 
00017 #ifndef PARAM_T
00018 #define PARAM_T
00019 
00020 class intsim_param_t {
00021 public:
00022   intsim_param_t() {}
00023   ~intsim_param_t() {}
00024 
00025   double calc_cg(double W, double T, double H, double S, double er);
00026   double calc_cm(double W, double T, double H, double S, double er);
00027   double calc_co(double tox, double F);
00028   double calc_ro(double Vdd, double Vt, double Vdd_spec, double Vt_spec, double Idsat_spec, double alpha);
00029   void setup(void);
00030 
00031   // Default system parameters
00032   double Vdd;                           // Supply voltage
00033   double Vt;                            // Threshold voltage
00034   double f;                             // Clock frequency
00035   double ncp;                           // Number of gates on a critical path
00036   double k;                             // Rent's constant k
00037   double p;                             // Rent's constant p
00038   double a;                             // Activity factor
00039   double A;                             // Die area
00040   double ngates;                        // Number of gates
00041   double pgates;                        // Percentage of chip area taken by logic gates for a given wgate
00042   double nsockets;                      // ngates/pgates
00043 
00044   // Default device parameters
00045   double F;                             // Minimum feature size
00046   double Idsat_spec;                    // Saturation drain current for a minimum-size NFET
00047   double Ileak_spec;                    // Leakage current of a minimum-size NFET
00048   double Vdd_spec;                      // Vdd at which Idsat and Ileak are specified
00049   double Vt_spec;                       // Vt at which Idsat and Ileak are specified
00050   double tox;                           // Effective oxide thickness
00051   double alpha;                         // Alpha value of the power-law MOSFET model
00052   double drive_p_div_n;                 // Ratio of drive current of pMOS and nMOS
00053   double subvtslope_spec;               // Subthreshold slope at 85 degrees Celsius
00054   double F1;                            // Minimum wire pitch
00055   double s;                             // Design rule for vias
00056   double device_width;                  // wgate
00057 
00058   // Default interconnect package parameters
00059   double er;                            // Dielectric permitivity
00060   double rho;                           // Resistivity of copper
00061   double ar;                            // Aspect ratio of wiring levels
00062   double R_coeff;                       // Reflectivity coefficient at grain boundaries for copper
00063   double p_size;                        // Specularity parameter
00064   double npower_pads;                   // Number of power pads
00065   double pad_to_pad_distance;           // Average distance from one power pad to the next
00066   double pad_length;                    // Length of a pad
00067   double ir_drop_limit;                 // IR drop limit in percentage, half for each global and local
00068 
00069   // Default design parameters
00070   double router_eff;                    // Router efficiency
00071   double rep_eff;                       // Repeaters efficiency
00072   double fo;                            // Average fan-out of logic gates
00073   double margin;                        // Percentage of clock cycle lost due to the process variation and clock skew
00074   double D;                             // Max span of H tree that needs to be driven
00075   double latches_per_buffer;            // Latches per buffer
00076   double clock_factor;                  // Clock factor (number of latches = clock factor x total number of gates / number of gates on a critical path)
00077   double clock_gating_factor;           // Percentage of local clock power saved by clock gating
00078   double kai;                           // Point-to-point to net length correction factor
00079   double alpha_wire;                    // Alpha wire
00080   double ro;                            // Output resistance of a minimum-size inverter
00081   double co;                            // Input capacitance of a minimum-size inverter
00082 
00083   // Other parameters assumed
00084   double ew_power_ground;
00085   double H;                             // ILD thickness
00086   double W;                             // Wire width
00087   double T;                             // Wire thickness
00088   double S;                             // Spacing between wires
00089   double cg;                            // Ground capacitance per unit length of a wire
00090   double cm;                            // Ground capacitance per unit length of a wire
00091   double kp;                            // Ratio of widths of power and signal wires
00092   double kc;                            // Ratio of widths of clock and signal wires
00093   double ew;                            // Wiring efficiency considering only via blockage and router efficiency
00094   double beta_clock;                    // Max slew allowable on clock wire
00095   double c_clock;                       // Capacitance per unit length of clock wire
00096   int max_tier;                         // Limit of tiers for iteration
00097 
00098   // Dimensions of wires
00099   double W_global;
00100   double T_global;
00101   double H_global;
00102   double S_global;
00103 };
00104 
00105 #endif

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