• Main Page
  • Related Pages
  • Modules
  • Data Structures
  • Files
  • File List
  • Globals

sst/core/techModels/libsim-panalyzer/target-alpha/alpha.h

00001 /*
00002  * alpha.h - Alpha ISA definitions
00003  *
00004  * This file is a part of the SimpleScalar tool suite written by
00005  * Todd M. Austin as a part of the Multiscalar Research Project.
00006  *  
00007  * The tool suite is currently maintained by Doug Burger and Todd M. Austin.
00008  * 
00009  * Copyright (C) 1994, 1995, 1996, 1997, 1998 by Todd M. Austin
00010  *
00011  * This source file is distributed "as is" in the hope that it will be
00012  * useful.  The tool set comes with no warranty, and no author or
00013  * distributor accepts any responsibility for the consequences of its
00014  * use. 
00015  * 
00016  * Everyone is granted permission to copy, modify and redistribute
00017  * this tool set under the following conditions:
00018  * 
00019  *    This source code is distributed for non-commercial use only. 
00020  *    Please contact the maintainer for restrictions applying to 
00021  *    commercial use.
00022  *
00023  *    Permission is granted to anyone to make or distribute copies
00024  *    of this source code, either as received or modified, in any
00025  *    medium, provided that all copyright notices, permission and
00026  *    nonwarranty notices are preserved, and that the distributor
00027  *    grants the recipient permission for further redistribution as
00028  *    permitted by this document.
00029  *
00030  *    Permission is granted to distribute this file in compiled
00031  *    or executable form under the same conditions that apply for
00032  *    source code, provided that either:
00033  *
00034  *    A. it is accompanied by the corresponding machine-readable
00035  *       source code,
00036  *    B. it is accompanied by a written offer, with no time limit,
00037  *       to give anyone a machine-readable copy of the corresponding
00038  *       source code in return for reimbursement of the cost of
00039  *       distribution.  This written offer must permit verbatim
00040  *       duplication by anyone, or
00041  *    C. it is distributed by someone who received only the
00042  *       executable form, and is accompanied by a copy of the
00043  *       written offer of source code that they received concurrently.
00044  *
00045  * In other words, you are welcome to use, share and improve this
00046  * source file.  You are forbidden to forbid anyone else to use, share
00047  * and improve what you give them.
00048  *
00049  * INTERNET: dburger@cs.wisc.edu
00050  * US Mail:  1210 W. Dayton Street, Madison, WI 53706
00051  *
00052  * $Id: alpha.h,v 1.1.1.1 2003/09/18 00:57:55 panalyzer Exp $
00053  *
00054  * $Log: alpha.h,v $
00055  * Revision 1.1.1.1  2003/09/18 00:57:55  panalyzer
00056  *
00057  *
00058  * Revision 1.1.1.1  2003/09/18 00:18:45  panalyzer
00059  *
00060  *
00061  * Revision 1.1.1.1  2003/09/16 18:48:14  gdm
00062  *
00063  *
00064  * Revision 1.1.1.1  2000/05/26 15:22:27  taustin
00065  * SimpleScalar Tool Set
00066  *
00067  *
00068  * Revision 1.4  1999/12/31 18:58:15  taustin
00069  * quad_t naming conflicts removed
00070  * MD_FETCH_INST() macro fixed
00071  * Alpha instruction set extensions (MVI, BWX, AMASK, IMPLVER, etc...)
00072  *
00073  * Revision 1.3  1999/12/13 18:59:40  taustin
00074  * cross endian execution support added
00075  *
00076  * Revision 1.2  1998/08/31 17:15:23  taustin
00077  * fixed non-portable SEXT definitions
00078  *
00079  * Revision 1.1  1998/08/27 16:53:36  taustin
00080  * Initial revision
00081  *
00082  * Revision 1.1  1998/05/06  01:09:18  calder
00083  * Initial revision
00084  *
00085  * Revision 1.5  1997/03/11  01:38:10  taustin
00086  * updated copyrights
00087  * long/int tweaks made for ALPHA target support
00088  * IFAIL() hook now allows simulators to declare instruction faults
00089  * IDIV()/IMOD()/FDIV() hooks now support simulator fault masking
00090  * supported added for non-GNU C compilers
00091  *
00092  * Revision 1.4  1997/01/06  16:08:10  taustin
00093  * comments updated
00094  * functional unit definitions moved from ss.def
00095  *
00096  * Revision 1.3  1996/12/27  15:55:37  taustin
00097  * fixed system header collision with MAXINT
00098  *
00099  * Revision 1.1  1996/12/05  18:50:23  taustin
00100  * Initial revision
00101  *
00102  */
00103 
00104 #ifndef ALPHA_H
00105 #define ALPHA_H
00106 
00107 #include <stdio.h>
00108 
00109 #include "host.h"
00110 #include "misc.h"
00111 #include "config.h"
00112 #include "endian.h"
00113 
00114 
00115 /*
00116  * This file contains various definitions needed to decode, disassemble, and
00117  * execute Alpha AXP instructions.
00118  */
00119 
00120 /* build for Alpha AXP target */
00121 #define TARGET_ALPHA
00122 
00123 /* probe cross-endian execution */
00124 #if defined(BYTES_BIG_ENDIAN)
00125 #define MD_CROSS_ENDIAN
00126 #endif
00127 
00128 /* not applicable/available, usable in most definition contexts */
00129 #define NA              0
00130 
00131 /*
00132  * target-dependent type definitions
00133  */
00134 
00135 /* define MD_QWORD_ADDRS if the target requires 64-bit (qword) addresses */
00136 #define MD_QWORD_ADDRS
00137 
00138 /* address type definition */
00139 typedef qword_t md_addr_t;
00140 
00141 
00142 /*
00143  * target-dependent memory module configuration
00144  */
00145 
00146 /* physical memory page size (must be a power-of-two) */
00147 #define MD_PAGE_SIZE            8192
00148 #define MD_LOG_PAGE_SIZE        13
00149 
00150 
00151 /*
00152  * target-dependent instruction faults
00153  */
00154 
00155 enum md_fault_type {
00156   md_fault_none = 0,            /* no fault */
00157   md_fault_access,              /* storage access fault */
00158   md_fault_alignment,           /* storage alignment fault */
00159   md_fault_overflow,            /* signed arithmetic overflow fault */
00160   md_fault_div0,                /* division by zero fault */
00161   md_fault_invalid,             /* invalid arithmetic operation */ 
00162                                 /* added to allow SQRT{S,T} in FIX exts */
00163   md_fault_break,               /* BREAK instruction fault */
00164   md_fault_unimpl,              /* unimplemented instruction fault */
00165   md_fault_internal             /* internal S/W fault */
00166 };
00167 
00168 
00169 /*
00170  * target-dependent register file definitions, used by regs.[hc]
00171  */
00172 
00173 /* number of integer registers */
00174 #define MD_NUM_IREGS            32
00175 
00176 /* number of floating point registers */
00177 #define MD_NUM_FREGS            32
00178 
00179 /* number of control registers */
00180 #define MD_NUM_CREGS            2
00181 
00182 /* total number of registers, excluding PC and NPC */
00183 #define MD_TOTAL_REGS                                                   \
00184   (/*int*/32 + /*fp*/32 + /*misc*/2 + /*tmp*/1 + /*mem*/1 + /*ctrl*/1)
00185 
00186 /* general purpose (integer) register file entry type */
00187 typedef qword_t md_gpr_t[MD_NUM_IREGS];
00188 
00189 /* floating point register file entry type */
00190 typedef union {
00191   qword_t q[MD_NUM_FREGS];      /* integer qword view */
00192   dfloat_t d[MD_NUM_FREGS];     /* double-precision floating point view */
00193 } md_fpr_t;
00194 
00195 /* control register file contents */
00196 typedef struct {
00197   qword_t fpcr;                 /* floating point condition codes */
00198   qword_t uniq;                 /* process-unique register */
00199 } md_ctrl_t;
00200 
00201 /* well known registers */
00202 enum md_reg_names {
00203   MD_REG_V0 = 0,        /* return value reg */
00204   MD_REG_ERR = 7,
00205   MD_REG_FP = 15,       /* frame pointer */
00206   MD_REG_A0 = 16,       /* argument regs */
00207   MD_REG_A1 = 17,
00208   MD_REG_A2 = 18,
00209   MD_REG_A3 = 19,
00210   MD_REG_A4 = 20,
00211   MD_REG_A5 = 21,
00212   MD_REG_RA = 26,       /* return address reg */
00213   MD_REG_GP = 29,       /* global data section pointer */
00214   MD_REG_SP = 30,       /* stack pointer */
00215   MD_REG_ZERO = 31      /* zero register */
00216 };
00217 
00218 
00219 /*
00220  * target-dependent instruction format definition
00221  */
00222 
00223 /* instruction formats */
00224 typedef word_t md_inst_t;
00225 
00226 /* preferred nop instruction definition */
00227 extern md_inst_t MD_NOP_INST;
00228 
00229 /* target swap support */
00230 #ifdef MD_CROSS_ENDIAN
00231 
00232 #define MD_SWAPH(X)             SWAP_HALF(X)
00233 #define MD_SWAPW(X)             SWAP_WORD(X)
00234 #define MD_SWAPQ(X)             SWAP_QWORD(X)
00235 #define MD_SWAPI(X)             SWAP_WORD(X)
00236 
00237 #else /* !MD_CROSS_ENDIAN */
00238 
00239 #define MD_SWAPH(X)             (X)
00240 #define MD_SWAPW(X)             (X)
00241 #define MD_SWAPQ(X)             (X)
00242 #define MD_SWAPD(X)             (X)
00243 #define MD_SWAPI(X)             (X)
00244 
00245 #endif
00246 
00247 /* fetch an instruction */
00248 #define MD_FETCH_INST(INST, MEM, PC)                                    \
00249   { (INST) = MEM_READ_WORD((MEM), (PC)); }
00250 
00251 /*
00252  * target-dependent loader module configuration
00253  */
00254 
00255 /* maximum size of argc+argv+envp environment */
00256 #define MD_MAX_ENVIRON          16384
00257 
00258 
00259 /*
00260  * machine.def specific definitions
00261  */
00262 
00263 /* inst -> enum md_opcode mapping, use this macro to decode insts */
00264 #define MD_TOP_OP(INST)         (((INST) >> 26) & 0x3f)
00265 #define MD_SET_OPCODE(OP, INST)                                         \
00266   { OP = md_mask2op[MD_TOP_OP(INST)];                                   \
00267     while (md_opmask[OP])                                               \
00268       OP = md_mask2op[((INST >> md_opshift[OP]) & md_opmask[OP])        \
00269                       + md_opoffset[OP]]; }
00270 
00271 /* largest opcode field value (currently upper 8-bit are used for pre/post-
00272     incr/decr operation specifiers */
00273 #define MD_MAX_MASK             2048
00274 
00275 /* internal decoder state */
00276 extern enum md_opcode md_mask2op[];
00277 extern unsigned int md_opoffset[];
00278 extern unsigned int md_opmask[];
00279 extern unsigned int md_opshift[];
00280 
00281 /* global opcode names, these are returned by the decoder (MD_OP_ENUM()) */
00282 enum md_opcode {
00283   OP_NA = 0,    /* NA */
00284 #define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) OP,
00285 #define DEFLINK(OP,MSK,NAME,MASK,SHIFT) OP,
00286 #define CONNECT(OP)
00287 #include "machine.def"
00288   OP_MAX        /* number of opcodes + NA */
00289 };
00290 
00291 /* enum md_opcode -> description string */
00292 #define MD_OP_NAME(OP)          (md_op2name[OP])
00293 extern char *md_op2name[];
00294 
00295 /* enum md_opcode -> opcode operand format, used by disassembler */
00296 #define MD_OP_FORMAT(OP)        (md_op2format[OP])
00297 extern char *md_op2format[];
00298 
00299 /* function unit classes, update md_fu2name if you update this definition */
00300 enum md_fu_class {
00301   FUClamd_NA = 0,       /* inst does not use a functional unit */
00302   IntALU,               /* integer ALU */
00303   IntMULT,              /* integer multiplier */
00304   IntDIV,               /* integer divider */
00305   FloatADD,             /* floating point adder/subtractor */
00306   FloatCMP,             /* floating point comparator */
00307   FloatCVT,             /* floating point<->integer converter */
00308   FloatMULT,            /* floating point multiplier */
00309   FloatDIV,             /* floating point divider */
00310   FloatSQRT,            /* floating point square root */
00311   RdPort,               /* memory read port */
00312   WrPort,               /* memory write port */
00313   NUM_FU_CLASSES        /* total functional unit classes */
00314 };
00315 
00316 /* enum md_opcode -> enum md_fu_class, used by performance simulators */
00317 #define MD_OP_FUCLASS(OP)       (md_op2fu[OP])
00318 extern enum md_fu_class md_op2fu[];
00319 
00320 /* enum md_fu_class -> description string */
00321 #define MD_FU_NAME(FU)          (md_fu2name[FU])
00322 extern char *md_fu2name[];
00323 
00324 /* instruction flags */
00325 #define F_ICOMP         0x00000001      /* integer computation */
00326 #define F_FCOMP         0x00000002      /* FP computation */
00327 #define F_CTRL          0x00000004      /* control inst */
00328 #define F_UNCOND        0x00000008      /*   unconditional change */
00329 #define F_COND          0x00000010      /*   conditional change */
00330 #define F_MEM           0x00000020      /* memory access inst */
00331 #define F_LOAD          0x00000040      /*   load inst */
00332 #define F_STORE         0x00000080      /*   store inst */
00333 #define F_DISP          0x00000100      /*   displaced (R+C) addr mode */
00334 #define F_RR            0x00000200      /*   R+R addr mode */
00335 #define F_DIRECT        0x00000400      /*   direct addressing mode */
00336 #define F_TRAP          0x00000800      /* traping inst */
00337 #define F_LONGLAT       0x00001000      /* long latency inst (for sched) */
00338 #define F_DIRJMP        0x00002000      /* direct jump */
00339 #define F_INDIRJMP      0x00004000      /* indirect jump */
00340 #define F_CALL          0x00008000      /* function call */
00341 #define F_FPCOND        0x00010000      /* FP conditional branch */
00342 #define F_IMM           0x00020000      /* instruction has immediate operand */
00343 
00344 /* enum md_opcode -> opcode flags, used by simulators */
00345 #define MD_OP_FLAGS(OP)         (md_op2flags[OP])
00346 extern unsigned int md_op2flags[];
00347 
00348 
00349 /* integer register specifiers */
00350 #define RA              ((inst >> 21) & 0x1f)           /* reg source #1 */
00351 #define RB              ((inst >> 16) & 0x1f)           /* reg source #2 */
00352 #define RC              (inst & 0x1f)                   /* reg dest */
00353 
00354 /* returns 8-bit unsigned immediate field value */
00355 #define IMM             ((qword_t)((inst >> 13) & 0xff))
00356 
00357 /* returns 21-bit unsigned absolute jump target field value */
00358 #define TARG            (inst & 0x1fffff)
00359 
00360 /* load/store 16-bit unsigned offset field value */
00361 #define OFS             (inst & 0xffff)
00362 
00363 /* sign-extend operands */
00364 #define SEXT(X)                                                         \
00365   (((X) & 0x8000) ? ((sqword_t)(X) | LL(0xffffffffffff0000)) : (sqword_t)(X))
00366 
00367 #define SEXT21(X)                                                       \
00368   (((X) & 0x100000) ? ((sqword_t)(X) | LL(0xffffffffffe00000)) : (sqword_t)(X))
00369 
00370 #define SEXT32(X)                                                       \
00371   (((X) & 0x80000000) ? ((sqword_t)(X)|LL(0xffffffff00000000)) : (sqword_t)(X))
00372 
00373 /* test for arithmetic overflow */
00374 #define ARITH_OVFL(RESULT, OP1, OP2) ((RESULT) < (OP1) || (RESULT) < (OP2))
00375 
00376 /* test for NaN */
00377 #define IEEEFP_DBL_SIGN(Q)      ((Q) >> 63)
00378 #define IEEEFP_DBL_EXPONENT(Q)  (((Q) >> 52) & 0x7ff)
00379 #define IEEEFP_DBL_FRACTION(Q)  ((Q) & ULL(0xfffffffffffff))
00380 #define IS_IEEEFP_DBL_NAN(Q)                                            \
00381   ((IEEEFP_DBL_EXPONENT(Q) == 0x7ff) && (IEEEFP_DBL_FRACTION(Q)))
00382 
00383 /* default target PC handling */
00384 #ifndef SET_TPC
00385 #define SET_TPC(PC)     (void)0
00386 #endif /* SET_TPC */
00387 
00388 
00389 /*
00390  * various other helper macros/functions
00391  */
00392 
00393 /* non-zero if system call is an exit() */
00394 #define OSF_SYS_exit                    1
00395 #define MD_EXIT_SYSCALL(REGS)                                           \
00396   ((REGS)->regs_R[MD_REG_V0] == OSF_SYS_exit)
00397 
00398 /* non-zero if system call is a write to stdout/stderr */
00399 #define OSF_SYS_write                   4
00400 #define MD_OUTPUT_SYSCALL(REGS)                                         \
00401   ((REGS)->regs_R[MD_REG_V0] == OSF_SYS_write                           \
00402    && ((REGS)->regs_R[MD_REG_A0] == /* stdout */1                       \
00403        || (REGS)->regs_R[MD_REG_A0] == /* stderr */2))
00404 
00405 /* returns stream of an output system call, translated to host */
00406 #define MD_STREAM_FILENO(REGS)          ((REGS)->regs_R[MD_REG_A0])
00407 
00408 /* returns non-zero if instruction is a function call */
00409 #define MD_IS_CALL(OP)                  ((OP) == JSR || (OP) == BSR)
00410 
00411 /* returns non-zero if instruction is a function return */
00412 #define MD_IS_RETURN(OP)                ((OP) == RETN)
00413 
00414 /* returns non-zero if instruction is an indirect jump */
00415 #define MD_IS_INDIR(OP)                                                 \
00416   ((OP) == JMP || (OP) == JSR || (OP) == RETN || (OP) == JSR_COROUTINE)
00417 
00418 /* addressing mode probe, enums and strings */
00419 enum md_amode_type {
00420   md_amode_imm,         /* immediate addressing mode */
00421   md_amode_gp,          /* global data access through global pointer */
00422   md_amode_sp,          /* stack access through stack pointer */
00423   md_amode_fp,          /* stack access through frame pointer */
00424   md_amode_disp,        /* (reg + const) addressing */
00425   md_amode_rr,          /* (reg + reg) addressing */
00426   md_amode_NUM
00427 };
00428 extern char *md_amode_str[md_amode_NUM];
00429 
00430 /* addressing mode pre-probe FSM, must see all instructions */
00431 #define MD_AMODE_PREPROBE(OP, FSM)              { (FSM) = 0; }
00432 
00433 /* compute addressing mode, only for loads/stores */
00434 #define MD_AMODE_PROBE(AM, OP, FSM)                                     \
00435   {                                                                     \
00436     if (MD_OP_FLAGS(OP) & F_DISP)                                       \
00437       {                                                                 \
00438         if ((RB) == MD_REG_GP)                                          \
00439           (AM) = md_amode_gp;                                           \
00440         else if ((RB) == MD_REG_SP)                                     \
00441           (AM) = md_amode_sp;                                           \
00442         else if ((RB) == MD_REG_FP) /* && bind_to_seg(addr) == seg_stack */\
00443           (AM) = md_amode_fp;                                           \
00444         else                                                            \
00445           (AM) = md_amode_disp;                                         \
00446       }                                                                 \
00447     else if (MD_OP_FLAGS(OP) & F_RR)                                    \
00448       (AM) = md_amode_rr;                                               \
00449     else                                                                \
00450       panic("cannot decode addressing mode");                           \
00451   }
00452 
00453 /* addressing mode pre-probe FSM, after all loads and stores */
00454 #define MD_AMODE_POSTPROBE(FSM)                 /* nada... */
00455 
00456 
00457 /*
00458  * EIO package configuration/macros
00459  */
00460 
00461 /* expected EIO file format */
00462 #define MD_EIO_FILE_FORMAT              EIO_ALPHA_FORMAT
00463 
00464 #define MD_MISC_REGS_TO_EXO(REGS)                                       \
00465   exo_new(ec_list,                                                      \
00466           /*icnt*/exo_new(ec_integer, (exo_integer_t)sim_num_insn),     \
00467           /*PC*/exo_new(ec_address, (exo_integer_t)(REGS)->regs_PC),    \
00468           /*NPC*/exo_new(ec_address, (exo_integer_t)(REGS)->regs_NPC),  \
00469           /*FPCR*/exo_new(ec_integer, (exo_integer_t)(REGS)->regs_C.fpcr),\
00470           /*UNIQ*/exo_new(ec_integer, (exo_integer_t)(REGS)->regs_C.uniq),\
00471           NULL)
00472 
00473 #define MD_IREG_TO_EXO(REGS, IDX)                                       \
00474   exo_new(ec_address, (exo_integer_t)(REGS)->regs_R[IDX])
00475 
00476 #define MD_FREG_TO_EXO(REGS, IDX)                                       \
00477   exo_new(ec_address, (exo_integer_t)(REGS)->regs_F.q[IDX])
00478 
00479 #define MD_EXO_TO_MISC_REGS(EXO, ICNT, REGS)                            \
00480   /* check EXO format for errors... */                                  \
00481   if (!exo                                                              \
00482       || exo->ec != ec_list                                             \
00483       || !exo->as_list.head                                             \
00484       || exo->as_list.head->ec != ec_integer                            \
00485       || !exo->as_list.head->next                                       \
00486       || exo->as_list.head->next->ec != ec_address                      \
00487       || !exo->as_list.head->next->next                                 \
00488       || exo->as_list.head->next->next->ec != ec_address                \
00489       || !exo->as_list.head->next->next->next                           \
00490       || exo->as_list.head->next->next->next->ec != ec_integer          \
00491       || !exo->as_list.head->next->next->next->next                     \
00492       || exo->as_list.head->next->next->next->next->ec != ec_integer    \
00493       || exo->as_list.head->next->next->next->next->next != NULL)       \
00494     fatal("could not read EIO misc regs");                              \
00495   (ICNT) = (counter_t)exo->as_list.head->as_integer.val;                \
00496   (REGS)->regs_PC = (md_addr_t)exo->as_list.head->next->as_integer.val; \
00497   (REGS)->regs_NPC =                                                    \
00498     (md_addr_t)exo->as_list.head->next->next->as_integer.val;           \
00499   (REGS)->regs_C.fpcr =                                                 \
00500     (qword_t)exo->as_list.head->next->next->next->as_integer.val;       \
00501   (REGS)->regs_C.uniq =                                                 \
00502     (qword_t)exo->as_list.head->next->next->next->next->as_integer.val;
00503 
00504 #define MD_EXO_TO_IREG(EXO, REGS, IDX)                                  \
00505   ((REGS)->regs_R[IDX] = (qword_t)(EXO)->as_integer.val)
00506 
00507 #define MD_EXO_TO_FREG(EXO, REGS, IDX)                                  \
00508   ((REGS)->regs_F.q[IDX] = (qword_t)(EXO)->as_integer.val)
00509 
00510 #define MD_EXO_CMP_IREG(EXO, REGS, IDX)                                 \
00511   ((REGS)->regs_R[IDX] != (qword_t)(EXO)->as_integer.val)
00512 
00513 #define MD_FIRST_IN_REG                 0
00514 #define MD_LAST_IN_REG                  21
00515 
00516 #define MD_FIRST_OUT_REG                0
00517 #define MD_LAST_OUT_REG                 21
00518 
00519 
00520 /*
00521  * configure the EXO package
00522  */
00523 
00524 /* EXO pointer class */
00525 typedef qword_t exo_address_t;
00526 
00527 /* EXO integer class, 64-bit encoding */
00528 typedef qword_t exo_integer_t;
00529 
00530 /* EXO floating point class, 64-bit encoding */
00531 typedef double exo_float_t;
00532 
00533 
00534 /*
00535  * configure the stats package
00536  */
00537 
00538 /* counter stats */
00539 #define stat_reg_counter                stat_reg_sqword
00540 #define sc_counter                      sc_sqword
00541 #define for_counter                     for_sqword
00542 
00543 /* address stats */
00544 #define stat_reg_addr                   stat_reg_qword
00545 
00546 
00547 /*
00548  * configure the DLite! debugger
00549  */
00550 
00551 /* register bank specifier */
00552 enum md_reg_type {
00553   rt_gpr,               /* general purpose register */
00554   rt_lpr,               /* integer-precision floating pointer register */
00555   rt_fpr,               /* single-precision floating pointer register */
00556   rt_dpr,               /* double-precision floating pointer register */
00557   rt_ctrl,              /* control register */
00558   rt_PC,                /* program counter */
00559   rt_NPC,               /* next program counter */
00560   rt_NUM
00561 };
00562 
00563 /* register name specifier */
00564 struct md_reg_names_t {
00565   char *str;                    /* register name */
00566   enum md_reg_type file;        /* register file */
00567   int reg;                      /* register index */
00568 };
00569 
00570 /* symbolic register names, parser is case-insensitive */
00571 extern struct md_reg_names_t md_reg_names[];
00572 
00573 /* returns a register name string */
00574 char *md_reg_name(enum md_reg_type rt, int reg);
00575 
00576 /* default register accessor object */
00577 struct eval_value_t;
00578 struct regs_t;
00579 char *                                          /* err str, NULL for no err */
00580 md_reg_obj(struct regs_t *regs,                 /* registers to access */
00581            int is_write,                        /* access type */
00582            enum md_reg_type rt,                 /* reg bank to probe */
00583            int reg,                             /* register number */
00584            struct eval_value_t *val);           /* input, output */
00585 
00586 /* print integer REG(S) to STREAM */
00587 void md_print_ireg(md_gpr_t regs, int reg, FILE *stream);
00588 void md_print_iregs(md_gpr_t regs, FILE *stream);
00589 
00590 /* print floating point REG(S) to STREAM */
00591 void md_print_fpreg(md_fpr_t regs, int reg, FILE *stream);
00592 void md_print_fpregs(md_fpr_t regs, FILE *stream);
00593 
00594 /* print control REG(S) to STREAM */
00595 void md_print_creg(md_ctrl_t regs, int reg, FILE *stream);
00596 void md_print_cregs(md_ctrl_t regs, FILE *stream);
00597 
00598 /* xor checksum registers */
00599 word_t md_xor_regs(struct regs_t *regs);
00600 
00601 
00602 /*
00603  * configure sim-outorder specifics
00604  */
00605 
00606 /* primitive operation used to compute addresses within pipeline */
00607 #define MD_AGEN_OP              ADDQ
00608 
00609 /* NOP operation when injected into the pipeline */
00610 #define MD_NOP_OP               OP_NA
00611 
00612 /* non-zero for a valid address, used to determine if speculative accesses
00613    should access the DL1 data cache */
00614 #define MD_VALID_ADDR(ADDR)                                             \
00615   (((ADDR) >= ld_text_base && (ADDR) < (ld_text_base + ld_text_size))   \
00616    || ((ADDR) >= ld_data_base && (ADDR) < ld_brk_point)                 \
00617    || ((ADDR) >= (ld_stack_base - 16*1024*1024) && (ADDR) < ld_stack_base))
00618 
00619 /*
00620  * configure branch predictors
00621  */
00622 
00623 /* shift used to ignore branch address least significant bits, usually
00624    log2(sizeof(md_inst_t)) */
00625 #define MD_BR_SHIFT             2       /* log2(4) */
00626 
00627 
00628 /*
00629  * target-dependent routines
00630  */
00631 
00632 /* intialize the inst decoder, this function builds the ISA decode tables */
00633 void md_init_decoder(void);
00634 
00635 /* disassemble a SimpleScalar instruction */
00636 void
00637 md_print_insn(md_inst_t inst,           /* instruction to disassemble */
00638               md_addr_t pc,             /* addr of inst, used for PC-rels */
00639               FILE *stream);            /* output stream */
00640 
00641 #endif /* ALPHA_H */
00642 
00643 
00644 
00645 
00646 
00647 
00648 
00649 #if 0
00650 
00651 /* instruction/address formats */
00652 typedef qword_t MD_ADDR_TYPE;
00653 typedef qword_t MD_PTR_TYPE;
00654 typedef word_t MD_INST_TYPE;
00655 #define MD_INST_SIZE            sizeof(MD_INST_TYPE)
00656 
00657 /* virtual memory segment limits */
00658 #define MD_TEXT_BASE            0x20000000ULL
00659 #define MD_STACK_BASE           (MD_TEXT_BASE - (409600+4096))
00660 
00661 /* well known registers */
00662 enum { REG_V0, REG_A0=16, REG_A1, REG_A2, REG_A3, REG_A4, REG_A5, REG_ERR=7,
00663        REG_GP=29, REG_SP, REG_ZERO, REG_RA=26 };
00664 
00665 /* total number of register in processor 32I+32F+HI+LO+FCC+TMP+MEM+CTRL */
00666 #define MD_TOTAL_REGS                                                   \
00667   (MD_NUM_REGS+MD_NUM_REGS+/*FPCR*/1+/*UNIQ*/1+/*MEM*/1+/*CTRL*/1)
00668 
00669 /* inst check macros, activated if NO_ICHECKS is not defined (default) */
00670 #ifndef NO_ICHECKS
00671 
00672 /* instruction failure notification macro, this can be defined by the
00673    target simulator if, for example, the simulator wants to handle the
00674    instruction fault in a machine specific fashion; a string describing
00675    the instruction fault is passed to the IFAIL() macro */
00676 #ifndef IFAIL
00677 #define IFAIL(S)        fatal(S)
00678 #endif /* IFAIL */
00679 
00680 /* check for overflow in X+Y, both signed */
00681 #define OVER(X,Y)       (((((X) > 0) && ((Y) > 0)                       \
00682                            && (MAXINT_VAL - (X) < (Y)))                 \
00683                           ? IFAIL("+ overflow") : (void)0),             \
00684                          ((((X) < 0) && ((Y) < 0)                       \
00685                            && (-MAXINT_VAL - (X) > (Y)))                \
00686                           ? IFAIL("+ underflow") : (void)0))
00687 
00688 /* check for underflow in X-Y, both signed */
00689 #define UNDER(X,Y)      (((((X) > 0) && ((Y) < 0)                       \
00690                            && (MAXINT_VAL + (Y) < (X)))                 \
00691                           ? IFAIL("- overflow") : (void)0),             \
00692                          ((((X) < 0) && ((Y) > 0)                       \
00693                            && (-MAXINT_VAL + (Y) > (X)))                \
00694                           ? IFAIL("- underflow") : (void)0))
00695 
00696 /* check for divide by zero error, N is denom */
00697 #define DIV0(N)         (((N) == 0) ? IFAIL("divide by 0") : (void)0)
00698 
00699 /* check reg specifier N for required double integer word alignment */
00700 #define INTALIGN(N)     (((N) & 01)                                     \
00701                          ? IFAIL("bad INT register alignment") : (void)0)
00702 
00703 /* check reg specifier N for required double FP word alignment */
00704 #define FPALIGN(N)      (((N) & 01)                                     \
00705                          ? IFAIL("bad FP register alignment") : (void)0)
00706 
00707 /* check target address TARG for required jump target alignment */
00708 #define TALIGN(TARG)    (((TARG) & 0x7)                                 \
00709                          ? IFAIL("bad jump alignment") : (void)0)
00710 
00711 #else /* NO_ICHECKS */
00712 
00713 /* inst checks disables, change all checks to NOP expressions */
00714 #define OVER(X,Y)       ((void)0)
00715 #define UNDER(X,Y)      ((void)0)
00716 #define DIV0(N)         ((void)0)
00717 #define INTALIGN(N)     ((void)0)
00718 #define FPALIGN(N)      ((void)0)
00719 #define TALIGN(TARG)    ((void)0)
00720 
00721 #endif /* NO_ICHECKS */
00722 
00723 /* default division operator semantics, this operation is accessed through a
00724    macro because some simulators need to check for divide by zero faults
00725    before executing this operation */
00726 #define IDIV(A, B)      ((A) / (B))
00727 #define IMOD(A, B)      ((A) % (B))
00728 #define FDIV(A, B)      ((A) / (B))
00729 #define FINT(A)         ((int)A)
00730 
00731 #endif

Generated on Fri Oct 22 2010 11:02:21 for SST by  doxygen 1.7.1