00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012 #ifndef _SST_INTERFACE_H
00013 #define _SST_INTERFACE_H
00014
00015
00016 #include <stdlib.h>
00017 #include <stdio.h>
00018 #include <unistd.h>
00019 #include <math.h>
00020 #include <string>
00021 #include <map>
00022 #include <sst/core/introspectedComponent.h>
00023 #include <sst/core/debug.h>
00024 #include <sst/core/sst_types.h>
00025
00026 #define ENERGY_INTERFACE_DEBUG
00027
00028 #define TEMP_DEGREE_STEPS 101 // 300~400K
00029
00030
00031
00032 namespace SST {
00033 enum interconnect_type_t
00034 {
00035 AGGRESSIVE, CONSERVATIVE, NUM_INTERCONNECT_TYPES
00036 };
00037
00038 enum wiring_type_t
00039 {
00040 Local, Semi_Global, Global, Memory_DRAM, Num_Wiring_Types
00041 };
00042
00043 enum ITRS_device_type_t
00044 {
00045 HP, LSTP, LOP, LP_DRAM, COMM_DRAM, NUM_TECH_TYPES
00046 };
00047
00048 enum clock_option_type_t
00049 {
00050 GLOBAL_CLOCK, LOCAL_CLOCK, TOTAL_CLOCK
00051 };
00052
00053
00054 class feature_t
00055 {
00056 public:
00057 feature_t() :
00058 x_position(0), y_position(0), width(0), length(0), area(0)
00059 {}
00060
00061 double x_position, y_position;
00062 double width, length;
00063 double area;
00064
00065 void reset()
00066 {
00067 x_position = 0; y_position = 0; width = 0; length = 0; area = 0;
00068 }
00069 };
00070
00071
00072
00073
00074
00075
00076
00077
00078 class parameters_tech_t
00079 {
00080 public:
00081 parameters_tech_t() : set(false) {}
00082 ~parameters_tech_t() {}
00083
00084 void set_default(double size, int RAM_tech_type);
00085
00086 bool set;
00087
00088 int RAM_tech;
00089
00090 double temperature;
00091
00092 double clock_frequency;
00093 double feature_size;
00094
00095
00096 double bulk_copper_resistivity;
00097 double copper_resistivity;
00098 double copper_reflectivity;
00099 double Rents_const_k;
00100 double Rents_const_p;
00101 double MOSFET_alpha;
00102 double subvtslope;
00103
00104
00105 int critical_path_depth;
00106 int via_design_rule;
00107 int avg_fanouts;
00108 int avg_latches_per_buffer;
00109 double activity_factor;
00110 double wiring_aspect_ratio;
00111 double specularity_parameter;
00112 double power_pad_distance;
00113 double power_pad_length;
00114 double IR_drop_limit;
00115 double router_efficiency;
00116 double repeater_efficiency;
00117 double clock_lost_ratio;
00118 double max_H_tree_span;
00119 double clock_factor;
00120 double clock_gating_factor;
00121 double power_signal_wire_ratio;
00122 double clock_signal_wire_ratio;
00123 double max_clock_skew;
00124
00125
00126 double sense_amp_delay;
00127 double sense_amp_power;
00128 double Wmemcella_sram;
00129 double Wmemcellpmos_sram;
00130 double Wmemcellnmos_sram;
00131 double area_cell_sram;
00132 double asp_ratio_cell_sram;
00133 double Wmemcella_cam;
00134 double Wmemcellpmos_cam;
00135 double Wmemcellnmos_cam;
00136 double area_cell_cam;
00137 double asp_ratio_cell_cam;
00138 double Wmemcella_dram;
00139 double Wmemcellpmos_dram;
00140 double Wmemcellnmos_dram;
00141 double area_cell_dram;
00142 double asp_ratio_cell_dram;
00143 double logic_scaling_co_eff;
00144 double core_tx_density;
00145 double sckt_co_eff;
00146 double chip_layout_overhead;
00147 double macro_layout_overhead;
00148 double fringe_cap[NUM_INTERCONNECT_TYPES][Num_Wiring_Types];
00149 double miller_value[NUM_INTERCONNECT_TYPES][Num_Wiring_Types];
00150 double ild_thickness[NUM_INTERCONNECT_TYPES][Num_Wiring_Types];
00151 double aspect_ratio[NUM_INTERCONNECT_TYPES][Num_Wiring_Types];
00152 double wire_pitch[NUM_INTERCONNECT_TYPES][Num_Wiring_Types];
00153 double wire_r_per_micron[NUM_INTERCONNECT_TYPES][Num_Wiring_Types];
00154 double wire_c_per_micron[NUM_INTERCONNECT_TYPES][Num_Wiring_Types];
00155 double horiz_dielectric_constant[NUM_INTERCONNECT_TYPES][Num_Wiring_Types];
00156 double vert_dielectric_constant[NUM_INTERCONNECT_TYPES][Num_Wiring_Types];
00157
00158 double Vpp;
00159 double vdd;
00160 double Vdsat;
00161 double Vth;
00162 double Vth_dram;
00163 double L_phy;
00164 double L_elec;
00165 double W_dram;
00166 double t_ox;
00167 double c_ox;
00168 double mobility_eff;
00169 double C_g_ideal;
00170 double C_fringe;
00171 double C_junc;
00172 double C_junc_sidewall;
00173 double C_dram_cell;
00174 double I_on_n;
00175 double I_on_p;
00176 double I_on_dram_cell;
00177 double I_off_dram_cell;
00178 double Rn_channel_on;
00179 double Rp_channel_on;
00180 double np_ratio;
00181 double gmp_to_gmn_multiplier;
00182 double long_channel_leakage_reduction;
00183 double I_off_n[TEMP_DEGREE_STEPS];
00184 double I_g_on_n[TEMP_DEGREE_STEPS];
00185
00186 private:
00187
00188 double wire_resistance(double resistivity, double wire_width, double wire_thickness, double barrier_thickness, double dishing_thickness, double alpha_scatter)
00189 {
00190 return alpha_scatter*resistivity/((wire_thickness-barrier_thickness-dishing_thickness)* (wire_width-2.0*barrier_thickness));
00191 }
00192
00193 double wire_capacitance(double wire_width, double wire_thickness, double wire_spacing,
00194 double ild_thickness, double miller_value, double horiz_dielectric_constant,
00195 double vert_dielectric_constant, double fringe_cap)
00196 {
00197 double vertical_cap, sidewall_cap, total_cap;
00198 vertical_cap = 2.0 * 8.854e-18 * vert_dielectric_constant * wire_width / ild_thickness;
00199 sidewall_cap = 2.0 * 8.854e-18 * miller_value * horiz_dielectric_constant * wire_thickness / wire_spacing;
00200 total_cap = vertical_cap + sidewall_cap + fringe_cap;
00201 return total_cap;
00202 }
00203 };
00204
00205 class parameters_thermal_tile_t
00206 {
00207 public:
00208 int layer;
00209 int id;
00210 std::string name;
00211 double temperature;
00212 };
00213
00214 class parameters_floorplan_t
00215 {
00216 public:
00217 int id;
00218 std::string name;
00219 feature_t feature;
00220 parameters_tech_t device_tech;
00221 std::map<int,double> thermal_correlation;
00222 };
00223
00224 class parameters_chip_t
00225 {
00226 public:
00227 parameters_chip_t() : is_set(false), num_comps(0) {}
00228 ~parameters_chip_t() { floorplan.clear(); }
00229
00230 void insert(parameters_floorplan_t *input) {
00231 floorplan.insert(std::pair<int,parameters_floorplan_t>((*input).id,*input));
00232 *input = parameters_floorplan_t();
00233 }
00234
00235 void insert(parameters_thermal_tile_t *input) {
00236 thermal_tile.insert(std::pair<std::pair<int,int>,parameters_thermal_tile_t>(std::pair<int,int>((*input).layer,(*input).id),(*input)));
00237 *input = parameters_thermal_tile_t();
00238 }
00239
00240
00241 int thermal_library;
00242 bool is_set;
00243 int num_comps;
00244
00245
00246 double thermal_threshold;
00247 double chip_thickness;
00248 double chip_thermal_conduct;
00249 double chip_heat;
00250 double heatsink_convection_cap;
00251 double heatsink_convection_res;
00252 double heatsink_side;
00253 double heatsink_thickness;
00254 double heatsink_thermal_conduct;
00255 double heatsink_heat;
00256 double spreader_side;
00257 double spreader_thickness;
00258 double spreader_thermal_conduct;
00259 double spreader_heat;
00260 double interface_thickness;
00261 double interface_thermal_conduct;
00262 double interface_heat;
00263 int secondary_model;
00264 double secondary_convection_res;
00265 double secondary_convection_cap;
00266 int metal_layers;
00267 double metal_thickness;
00268 double c4_thickness;
00269 double c4_side;
00270 int c4_pads;
00271 double substrate_side;
00272 double substrate_thickness;
00273 double solder_side;
00274 double solder_thickness;
00275 double pcb_side;
00276 double pcb_thickness;
00277
00278 double ambient;
00279 double sampling_interval;
00280 double clock_frequency;
00281 int leakage_used;
00282 int leakage_mode;
00283 int package_model_used;
00284 int block_omit_lateral;
00285 int num_grid_rows;
00286 int num_grid_cols;
00287 int num_floorplans;
00288
00289 std::map<int,parameters_floorplan_t> floorplan;
00290 std::map<std::pair<int,int>,parameters_thermal_tile_t> thermal_tile;
00291
00292 };
00293
00294 class floorplan_t
00295 {
00296 public:
00297 floorplan_t() :
00298 area_estimate(0.0), leakage_feedback(false)
00299 { }
00300 ~floorplan_t() {}
00301
00302 int id;
00303 std::string name;
00304 feature_t feature;
00305 parameters_tech_t device_tech;
00306 double area_estimate;
00307 bool leakage_feedback;
00308
00309 Pdissipation_t p_usage_floorplan;
00310 };
00311
00312 class thermal_library_t
00313 {
00314 public:
00315 thermal_library_t() {}
00316
00317 virtual void compute(std::map<int,floorplan_t> *floorplan) = 0;
00318 };
00319
00320 class thermal_tile_t
00321 {
00322 public:
00323 thermal_tile_t() {}
00324 ~thermal_tile_t() {}
00325
00326 std::string name;
00327 double temperature;
00328 };
00329
00330 class chip_t
00331 {
00332 public:
00333 chip_t() {}
00334 ~chip_t() {}
00335
00336 thermal_library_t *thermal_library;
00337
00338 std::map<int,floorplan_t> floorplan;
00339 };
00340
00341
00342
00343 }
00344 #endif // SST_INTERFACE_H
00345
00346