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00031 #ifdef DEBUG_PCI
00032 #define PCI_DPRINTF(fmt, args...) \
00033 do { printf("pci_host_data: " fmt , ##args); } while (0)
00034 #else
00035 #define PCI_DPRINTF(fmt, args...)
00036 #endif
00037
00038 typedef struct {
00039 uint32_t config_reg;
00040 PCIBus *bus;
00041 } PCIHostState;
00042
00043 static void pci_host_data_writeb(void* opaque, pci_addr_t addr, uint32_t val)
00044 {
00045 PCIHostState *s = opaque;
00046
00047 PCI_DPRINTF("writeb addr " TARGET_FMT_plx " val %x\n",
00048 (target_phys_addr_t)addr, val);
00049 if (s->config_reg & (1u << 31))
00050 pci_data_write(s->bus, s->config_reg | (addr & 3), val, 1);
00051 }
00052
00053 static void pci_host_data_writew(void* opaque, pci_addr_t addr, uint32_t val)
00054 {
00055 PCIHostState *s = opaque;
00056 #ifdef TARGET_WORDS_BIGENDIAN
00057 val = bswap16(val);
00058 #endif
00059 PCI_DPRINTF("writew addr " TARGET_FMT_plx " val %x\n",
00060 (target_phys_addr_t)addr, val);
00061 if (s->config_reg & (1u << 31))
00062 pci_data_write(s->bus, s->config_reg | (addr & 3), val, 2);
00063 }
00064
00065 static void pci_host_data_writel(void* opaque, pci_addr_t addr, uint32_t val)
00066 {
00067 PCIHostState *s = opaque;
00068 #ifdef TARGET_WORDS_BIGENDIAN
00069 val = bswap32(val);
00070 #endif
00071 PCI_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n",
00072 (target_phys_addr_t)addr, val);
00073 if (s->config_reg & (1u << 31))
00074 pci_data_write(s->bus, s->config_reg, val, 4);
00075 }
00076
00077 static uint32_t pci_host_data_readb(void* opaque, pci_addr_t addr)
00078 {
00079 PCIHostState *s = opaque;
00080 uint32_t val;
00081
00082 if (!(s->config_reg & (1 << 31)))
00083 return 0xff;
00084 val = pci_data_read(s->bus, s->config_reg | (addr & 3), 1);
00085 PCI_DPRINTF("readb addr " TARGET_FMT_plx " val %x\n",
00086 (target_phys_addr_t)addr, val);
00087 return val;
00088 }
00089
00090 static uint32_t pci_host_data_readw(void* opaque, pci_addr_t addr)
00091 {
00092 PCIHostState *s = opaque;
00093 uint32_t val;
00094 if (!(s->config_reg & (1 << 31)))
00095 return 0xffff;
00096 val = pci_data_read(s->bus, s->config_reg | (addr & 3), 2);
00097 PCI_DPRINTF("readw addr " TARGET_FMT_plx " val %x\n",
00098 (target_phys_addr_t)addr, val);
00099 #ifdef TARGET_WORDS_BIGENDIAN
00100 val = bswap16(val);
00101 #endif
00102 return val;
00103 }
00104
00105 static uint32_t pci_host_data_readl(void* opaque, pci_addr_t addr)
00106 {
00107 PCIHostState *s = opaque;
00108 uint32_t val;
00109 if (!(s->config_reg & (1 << 31)))
00110 return 0xffffffff;
00111 val = pci_data_read(s->bus, s->config_reg | (addr & 3), 4);
00112 PCI_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n",
00113 (target_phys_addr_t)addr, val);
00114 #ifdef TARGET_WORDS_BIGENDIAN
00115 val = bswap32(val);
00116 #endif
00117 return val;
00118 }