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sst/core/techModels/libMcPATbeta06/const.h

00001 /*****************************************************************************
00002  *                                McPAT
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00048 #ifndef __CONST_H__
00049 #define __CONST_H__
00050 
00051 #include <stdint.h>
00052 #include <stdlib.h>
00053 #include <string.h>
00054 #include <stdio.h>
00055 #include <math.h>
00056 
00057 /*  The following are things you might want to change
00058  *  when compiling
00059  */
00060 
00061 /*
00062  * Address bits in a word, and number of output bits from the cache
00063  */
00064 
00065 /*
00066 was: #define ADDRESS_BITS 32
00067 now: I'm using 42 bits as in the Power4,
00068 since that's bigger then the 36 bits on the Pentium 4
00069 and 40 bits on the Opteron
00070 */
00071 const int ADDRESS_BITS = 42;
00072 
00073 /*dt: In addition to the tag bits, the tags also include 1 valid bit, 1 dirty bit, 2 bits for a 4-state
00074   cache coherency protocoll (MESI), 1 bit for MRU (change this to log(ways) for full LRU).
00075   So in total we have 1 + 1 + 2 + 1 = 5 */
00076 const int EXTRA_TAG_BITS = 5;
00077 
00078 /* limits on the various N parameters */
00079 
00080 const unsigned int MAXDATAN     = 512;      // maximum for Ndwl and Ndbl
00081 const unsigned int MAXSUBARRAYS = 1048576;  // maximum subarrays for data and tag arrays
00082 const unsigned int MAXDATASPD   = 256;      // maximum for Nspd
00083 const unsigned int MAX_COL_MUX  = 256;
00084 
00085 
00086 
00087 #define ROUTER_TYPES 3
00088 #define WIRE_TYPES 6
00089 
00090 const double Cpolywire = 0;
00091 
00092 
00093 /* Threshold voltages (as a proportion of Vdd)
00094    If you don't know them, set all values to 0.5 */
00095 #define VTHFA1         0.452
00096 #define VTHFA2         0.304
00097 #define VTHFA3         0.420
00098 #define VTHFA4         0.413
00099 #define VTHFA5         0.405
00100 #define VTHFA6         0.452
00101 #define VSINV          0.452
00102 #define VTHCOMPINV     0.437
00103 #define VTHMUXNAND     0.548  // TODO : this constant must be revisited
00104 #define VTHEVALINV     0.452
00105 #define VTHSENSEEXTDRV 0.438
00106 
00107 
00108 //WmuxdrvNANDn and WmuxdrvNANDp are no longer being used but it's part of the old
00109 //delay_comparator function which we are using exactly as it used to be, so just setting these to 0
00110 const double WmuxdrvNANDn = 0;
00111 const double WmuxdrvNANDp = 0;
00112 
00113 
00114 /*===================================================================*/
00115 /*
00116  * The following are things you probably wouldn't want to change.
00117  */
00118 
00119 #define BIGNUM 1e30
00120 #define INF 9999999
00121 #ifndef MAX
00122 #define MAX(a,b) (((a)>(b))?(a):(b))
00123 #endif
00124 #ifndef MIN
00125 #define MIN(a,b) (((a)<(b))?(a):(b))
00126 #endif
00127 
00128 /* Used to communicate with the horowitz model */
00129 #define RISE 1
00130 #define FALL 0
00131 #define NCH  1
00132 #define PCH  0
00133 
00134 
00135 #define EPSILON 0.5 //v4.1: This constant is being used in order to fix floating point -> integer
00136 //conversion problems that were occuring within CACTI. Typical problem that was occuring was
00137 //that with different compilers a floating point number like 3.0 would get represented as either
00138 //2.9999....or 3.00000001 and then the integer part of the floating point number (3.0) would
00139 //be computed differently depending on the compiler. What we are doing now is to replace
00140 //int (x) with (int) (x+EPSILON) where EPSILON is 0.5. This would fix such problems. Note that
00141 //this works only when x is an integer >= 0.
00142 
00143 #define EPSILON2 0.1
00144 #define EPSILON3 0.6
00145 
00146 
00147 #define MINSUBARRAYROWS 16 //For simplicity in modeling, for the row decoding structure, we assume
00148 //that each row predecode block is composed of at least one 2-4 decoder. When the outputs from the
00149 //row predecode blocks are combined this means that there are at least 4*4=16 row decode outputs
00150 #define MAXSUBARRAYROWS 262144 //Each row predecode block produces a max of 2^9 outputs. So
00151 //the maximum number of row decode outputs will be 2^9*2^9
00152 #define MINSUBARRAYCOLS 2
00153 #define MAXSUBARRAYCOLS 262144
00154 
00155 
00156 #define INV 0
00157 #define NOR 1
00158 #define NAND 2
00159 
00160 
00161 #define NUMBER_TECH_FLAVORS 4
00162 
00163 #define NUMBER_INTERCONNECT_PROJECTION_TYPES 2 //aggressive and conservative
00164 //0 = Aggressive projections, 1 = Conservative projections
00165 #define NUMBER_WIRE_TYPES 4 //local, semi-global and global
00166 //1 = 'Semi-global' wire type, 2 = 'Global' wire type
00167 
00168 
00169 const int dram_cell_tech_flavor = 3;
00170 
00171 
00172 #define VBITSENSEMIN 0.08 //minimum bitline sense voltage is fixed to be 80 mV.
00173 
00174 #define fopt 4.0
00175 
00176 #define INPUT_WIRE_TO_INPUT_GATE_CAP_RATIO 0
00177 #define BUFFER_SEPARATION_LENGTH_MULTIPLIER 1
00178 #define NUMBER_MATS_PER_REDUNDANT_MAT 8
00179 
00180 #define NUMBER_STACKED_DIE_LAYERS 1
00181 
00182 // this variable can be set to carry out solution optimization for
00183 // a maximum area allocation.
00184 #define STACKED_DIE_LAYER_ALLOTED_AREA_mm2 0 //6.24 //6.21//71.5
00185 
00186 // this variable can also be employed when solution optimization
00187 // with maximum area allocation is carried out.
00188 #define MAX_PERCENT_AWAY_FROM_ALLOTED_AREA 50
00189 
00190 // this variable can also be employed when solution optimization
00191 // with maximum area allocation is carried out.
00192 #define MIN_AREA_EFFICIENCY 20
00193 
00194 // this variable can be employed when solution with a desired
00195 // aspect ratio is required.
00196 #define STACKED_DIE_LAYER_ASPECT_RATIO 1
00197 
00198 // this variable can be employed when solution with a desired
00199 // aspect ratio is required.
00200 #define MAX_PERCENT_AWAY_FROM_ASPECT_RATIO 101
00201 
00202 // this variable can be employed to carry out solution optimization
00203 // for a certain target random cycle time.
00204 #define TARGET_CYCLE_TIME_ns 1000000000
00205 
00206 #define NUMBER_PIPELINE_STAGES 4
00207 
00208 // this can be used to model the length of interconnect
00209 // between a bank and a crossbar
00210 #define LENGTH_INTERCONNECT_FROM_BANK_TO_CROSSBAR 0 //3791 // 2880//micron
00211 
00212 #define IS_CROSSBAR 0
00213 #define NUMBER_INPUT_PORTS_CROSSBAR 8
00214 #define NUMBER_OUTPUT_PORTS_CROSSBAR 8
00215 #define NUMBER_SIGNALS_PER_PORT_CROSSBAR 256
00216 
00217 
00218 #define MAT_LEAKAGE_REDUCTION_DUE_TO_SLEEP_TRANSISTORS_FACTOR 1
00219 #define LEAKAGE_REDUCTION_DUE_TO_LONG_CHANNEL_HP_TRANSISTORS_FACTOR 1
00220 
00221 #define PAGE_MODE 0
00222 
00223 #define MAIN_MEM_PER_CHIP_STANDBY_CURRENT_mA 60
00224 // We are actually not using this variable in the CACTI code. We just want to acknowledge that
00225 // this current should be multiplied by the DDR(n) system VDD value to compute the standby power
00226 // consumed during precharge.
00227 
00228 
00229 const double VDD_STORAGE_LOSS_FRACTION_WORST = 0.125;
00230 const double CU_RESISTIVITY = 0.022; //ohm-micron
00231 const double BULK_CU_RESISTIVITY = 0.018; //ohm-micron
00232 const double PERMITTIVITY_FREE_SPACE = 8.854e-18; //F/micron
00233 
00234 const static uint32_t sram_num_cells_wl_stitching_ = 16;
00235 const static uint32_t dram_num_cells_wl_stitching_ = 64;
00236 const static uint32_t comm_dram_num_cells_wl_stitching_ = 256;
00237 const static double num_bits_per_ecc_b_          = 8.0;
00238 
00239 const double    bit_to_byte  = 8.0;
00240 
00241 #define MAX_NUMBER_GATES_STAGE 20
00242 #define MAX_NUMBER_HTREE_NODES 20
00243 #define NAND2_LEAK_STACK_FACTOR 0.2
00244 #define NAND3_LEAK_STACK_FACTOR 0.2
00245 #define NOR2_LEAK_STACK_FACTOR 0.2
00246 #define INV_LEAK_STACK_FACTOR  0.5
00247 #define MAX_NUMBER_ARRAY_PARTITIONS 1000000
00248 
00249 
00250 // abbreviations used in this project
00251 // ----------------------------------
00252 //
00253 //  num  : number
00254 //  rw   : read/write
00255 //  rd   : read
00256 //  wr   : write
00257 //  se   : single-ended
00258 //  sz   : size
00259 //  F    : feature
00260 //  w    : width
00261 //  h    : height or horizontal
00262 //  v    : vertical or velocity
00263 
00264 
00265 enum ram_cell_tech_type_num
00266 {
00267   itrs_hp   = 0,
00268   itrs_lstp = 1,
00269   itrs_lop  = 2,
00270   lp_dram   = 3,
00271   comm_dram = 4
00272 };
00273 
00274 const double pppm[4]      = {1,1,1,1};
00275 const double pppm_lkg[4]  = {0,1,1,0};
00276 const double pppm_dyn[4]  = {1,0,0,0};
00277 const double pppm_Isub[4] = {0,1,0,0};
00278 const double pppm_Ig[4]   = {0,0,1,0};
00279 const double pppm_sc[4]   = {0,0,0,1};
00280 
00281 
00282 
00283 #endif

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