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00012 #ifndef SSB_SIM_OUTORDER_H
00013 #define SSB_SIM_OUTORDER_H
00014
00015 #include <set>
00016 #include "ssb_memory.h"
00017 #include "ssb_ruu.h"
00018 #include "ssb_cv_link.h"
00019 #include "ssb_rs_link.h"
00020 #include "ssb_bitmap.h"
00021 #include "ssb_cache.h"
00022 #include "prefetch.h"
00023 #include "sst/core/event.h"
00024
00025 #define GET_IMIX 1
00026
00027 class thread;
00028
00029
00030
00031
00032
00033
00034
00035 class convProc : public prefetchProc
00036 {
00037 friend struct CV_link;
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047 unsigned long long tickCount;
00048 processor *myProc;
00049 int myCoreID;
00050 public:
00051 unsigned long long TimeStamp() const {
00052 return tickCount;
00053 }
00054
00055
00056
00057
00058 virtual bool checkCache(const simAddress addr) {
00059 return cache_probe(cache_dl2, addr);
00060 };
00061
00062
00063
00064 virtual void insertCache(const simAddress mem) {
00065 bool dc; md_addr_t bumped = 0;
00066 cache_access(cache_dl2, Inject, (mem&~3), NULL, 0, TimeStamp(),
00067 NULL, NULL, dc, &bumped);
00068 if (dc == 1) {
00069 printf("need to handle main mem access in %s\n", __FILE__);
00070 }
00071 if (bumped != 0) {
00072 if (pref) pref->reportCacheEject(bumped);
00073 }
00074 }
00075 void wakeUpMM(map<instruction*, RUU_station*>::iterator &mi);
00076 void wakeUpPrefetched(instruction *inst);
00077
00078
00079
00080 virtual void sendToMem(instruction *i) {
00081 mmSendParcel(i);
00082 }
00083 protected:
00084
00085
00086
00087 bool simpleFetch;
00088
00089
00090
00091
00092 int maxMMStores;
00093
00094
00095
00096
00097
00098
00099 int portLimitedCommit;
00100 int regPortAvail;
00101
00102
00103
00104
00105 int waciLoadExtra;
00106
00107 unsigned long long lsqCompares;
00108
00109
00110
00111
00112
00113 bool clearPipe;
00114
00115
00116
00117
00118
00119
00120
00121 bool isSyncing;
00122
00123
00124 int clockRatio;
00125
00126
00127
00128 map<frameID, simRegister*> allocatedFrames;
00129
00130
00131
00132
00133
00134
00135 set<instruction*> mainMemStores;
00136
00137
00138
00139
00140
00141
00142 deque<instruction*> retireList;
00143
00144
00145
00146
00147 set<instruction*> OOOStores;
00148
00149 set<instruction*> condemnedRemotes;
00150
00151
00152
00153
00154
00155
00156 map<instruction*, RUU_station*> mainMemLoads;
00157
00158
00159
00160
00161
00162
00163 instruction *iFetchBlocker;
00164
00165
00166
00167
00168
00169
00170 prefetcher *pref;
00171
00172
00173 thread *thr;
00174
00175
00176
00177
00178 int instructionSize;
00179
00180
00181
00182
00183
00184
00185
00186 int simpleMemory;
00187
00188 RS_link_list rs_free_list;
00189
00190
00191
00192
00193
00194 struct RS_link last_op;
00195
00196
00197 md_addr_t pred_PC;
00198
00199
00200 md_addr_t recover_PC;
00201
00202
00203 md_addr_t fetch_regs_PC;
00204
00205
00206 md_addr_t fetch_pred_PC;
00207
00208
00209 struct fetch_rec *fetch_data;
00210
00211 int fetch_num;
00212
00213 int fetch_tail;
00214
00215 int fetch_head;
00216
00217
00218 int last_inst_missed;
00219 int last_inst_tmissed;
00220
00221
00222
00223
00224
00225 struct RUU_station *RUU;
00226
00227 int RUU_head;
00228
00229 int RUU_tail;
00230
00231 int RUU_num;
00232
00233
00234
00235
00236
00237
00238
00239
00240
00241
00242
00243
00244
00245
00246
00247
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00249
00250
00251
00252
00253
00254
00255
00256
00257
00258
00259
00260
00261
00262
00263
00264
00265
00266
00267
00268
00269
00270
00271
00272
00273 struct RUU_station *LSQ;
00274
00275 int LSQ_head;
00276
00277 int LSQ_tail;
00278
00279 int LSQ_num;
00280
00281
00282
00283
00284
00285
00286 struct RS_link *event_queue;
00287
00288
00289 struct RS_link *ready_queue;
00290
00291 unsigned int use_spec_cv[CV_BMAP_SZ];
00292
00293
00294
00295
00296
00297
00298
00299
00300
00301 struct CV_link create_vector[MD_TOTAL_REGS+2];
00302
00303
00304
00305 struct CV_link spec_create_vector[MD_TOTAL_REGS+2];
00306
00307
00308 tick_t create_vector_rt[MD_TOTAL_REGS+2];
00309
00310 tick_t spec_create_vector_rt[MD_TOTAL_REGS+2];
00311
00312
00313
00314
00315 #include "ssb_sim-outorder-options.h"
00316
00317
00318
00319 struct opt_odb_t *sim_odb;
00320
00321
00322
00323
00324
00325 struct stat_sdb_t *sim_sdb;
00326
00327 #if GET_IMIX == 1
00328 public:
00329
00330 unsigned long long iMix[LASTINST];
00331 protected:
00332 #endif
00333
00334 counter_t sim_num_insn;
00335
00336 counter_t sim_total_insn;
00337
00338 counter_t sim_num_refs;
00339
00340 counter_t sim_total_refs;
00341
00342 counter_t sim_num_loads;
00343
00344 counter_t sim_total_loads;
00345
00346 counter_t sim_num_branches;
00347
00348 counter_t sim_total_branches;
00349
00350 counter_t IFQ_count;
00351
00352 counter_t IFQ_fcount;
00353
00354 counter_t RUU_count;
00355
00356 counter_t RUU_fcount;
00357
00358 counter_t LSQ_count;
00359 #define WANT_LSQ_HIST 1
00360 #if WANT_LSQ_HIST == 1
00361 map<int, counter_t> LSQ_hist;
00362 #endif
00363
00364 counter_t LSQ_fcount;
00365
00366
00367 counter_t sim_invalid_addrs;
00368
00369
00370
00371
00372
00373 time_t sim_start_time;
00374
00375 time_t sim_end_time;
00376
00377 int sim_elapsed_time;
00378
00379
00380
00381
00382 unsigned int inst_seq;
00383
00384 unsigned int ptrace_seq;
00385
00386
00387
00388
00389
00390
00391 bool spec_mode;
00392
00393 int lsq_mult;
00394
00395
00396 unsigned ruu_fetch_issue_delay;
00397
00398
00399 unsigned ruu_dispatch_delay;
00400 virtual unsigned getFEBDelay() {return 0;}
00401
00402 int pred_perfect;
00403
00404 char *bpred_spec_opt;
00405
00406 enum { spec_ID, spec_WB, spec_CT } bpred_spec_update;
00407
00408
00409 struct cache_t *cache_il1;
00410
00411
00412 struct cache_t *cache_il2;
00413
00414
00415 struct cache_t *cache_dl1;
00416
00417
00418 struct cache_t *cache_dl2;
00419
00420 struct cache_t *itlb;
00421
00422 struct cache_t *dtlb;
00423
00424 struct bpred_t *pred;
00425
00426 struct res_pool *fu_pool;
00427
00428 struct stat_stat_t *pcstat_stats[MAX_PCSTAT_VARS];
00429
00430 counter_t pcstat_lastvals[MAX_PCSTAT_VARS];
00431
00432 struct stat_stat_t *pcstat_sdists[MAX_PCSTAT_VARS];
00433
00434 typedef map<instruction*, int> latencyMap;
00435 latencyMap extraInstLat;
00436 instruction *committingInst;
00437
00438
00439
00440
00441 public:
00442 convProc(string configFile, processor *p, int maxMMOut, int coreNum,
00443 map<string,string> prefetchInit);
00444
00445 protected:
00446
00447
00448
00449
00450
00451 void mmSendParcel(instruction *inst);
00452 void mainMemAccess(instruction*);
00453 unsigned int mem_access_latency(int blk_sz);
00454 virtual unsigned int cplx_mem_access_latency(const enum mem_cmd cmd,
00455 const md_addr_t baddr,
00456 const int bsize,
00457 bool &);
00458
00459
00460
00461 virtual void noteWrite(const simAddress a) = 0;
00462 virtual void handleCoher(const simAddress, const enum mem_cmd cmd) = 0;
00463 uint dl1_access_fn(enum mem_cmd cmd, md_addr_t baddr, int bsize,
00464 struct cache_blk_t *blk, tick_t now, bool&);
00465 uint dl2_access_fn(enum mem_cmd cmd, md_addr_t baddr, int bsize,
00466 cache_blk_t *blk, tick_t now, bool&);
00467 uint il1_access_fn(enum mem_cmd cmd, md_addr_t baddr, int bsize,
00468 struct cache_blk_t *blk, tick_t now, bool&);
00469 uint il2_access_fn(enum mem_cmd cmd, md_addr_t baddr, int bsize,
00470 struct cache_blk_t *blk, tick_t now, bool&);
00471 uint itlb_access_fn(enum mem_cmd cmd, md_addr_t baddr, int bsize,
00472 struct cache_blk_t *blk, tick_t now, bool&);
00473 uint dtlb_access_fn(enum mem_cmd cmd, md_addr_t baddr, int bsize,
00474 struct cache_blk_t *blk, tick_t now, bool&);
00475
00476
00477
00478
00479 void sim_print_stats(FILE *fd);
00480 int ss_main(const char*);
00481
00482
00483
00484
00485 void sim_reg_options(struct opt_odb_t *odb);
00486 void sim_check_options(struct opt_odb_t *odb);
00487 void sim_reg_stats(struct stat_sdb_t *sdb);
00488
00489
00490
00491
00492 void sim_init(void);
00493
00494 void sim_load_prog(const string fuConfStr);
00495 void ruu_init(void);
00496 void lsq_init(void);
00497 void fetch_init(void);
00498
00499
00500
00501
00502 static void ruu_dumpent(struct RUU_station *rs, int index, FILE *stream,
00503 int header);
00504 void ruu_dump(FILE *stream);
00505 void lsq_dump(FILE *stream);
00506 void rspec_dump(FILE *stream);
00507 void mspec_dump(FILE *stream);
00508 void fetch_dump(FILE *stream);
00509 void eventq_dump(FILE *stream);
00510 void readyq_dump(FILE *stream);
00511
00512
00513
00514
00515 static char *simoo_reg_obj(struct regs_t *regs, int is_write,
00516 enum md_reg_type rt, int reg,
00517 struct eval_value_t *val);
00518 static char *simoo_mem_obj(struct mem_t *mem, int is_write,
00519 md_addr_t addr, char *p, int nbytes);
00520 static char *simoo_mstate_obj(FILE *stream, char *cmd, struct regs_t *regs,
00521 struct mem_t *mem);
00522
00523
00524
00525
00526 struct RUU_station *eventq_next_event(void);
00527 void eventq_queue_event(struct RUU_station *rs, tick_t when);
00528 void eventq_init(void);
00529
00530
00531
00532
00533 void readyq_init(void);
00534 void readyq_enqueue(struct RUU_station *rs);
00535
00536
00537
00538
00539 void tracer_recover(void);
00540 void tracer_init(void);
00541 void ruu_recover(int branch_index);
00542
00543
00544
00545
00546 void ruu_link_idep(struct RUU_station * const rs, const int idep_num, const int idep_name);
00547 void ruu_install_odep(struct RUU_station *rs, int odep_num, int odep_name);
00548
00549
00550
00551
00552 void fast_sim_loop();
00553 void sim_loop(bool);
00554 void ruu_release_fu(void);
00555 void ruu_commit(void);
00556 void ruu_writeback(void);
00557 void lsq_refresh(void);
00558 void ruu_issue(void);
00559 void ruu_dispatch(void);
00560 void ruu_fetch(void);
00561 public:
00562
00563
00564
00565
00566
00567
00568 bool pipeClear() {return (RUU_num == 0 && fetch_num == 0 &&
00569 retireList.empty());}
00570 protected:
00571
00572
00573
00574
00575 bool pipeDispatchClear() {return (RUU_num == 0 && retireList.empty());}
00576
00577
00578
00579
00580 virtual void setup()=0;
00581 virtual void finish();
00582 public:
00583 virtual void handleMemEvent(instruction* inst );
00584 protected:
00585 virtual void postTic()=0;
00586 void handleReturningStore(instruction *inst);
00587
00588
00589
00590
00591 frameID requestFrame(int size);
00592 simRegister* getFrame(frameID);
00593 void returnFrame(frameID);
00594 virtual bool insertThread(thread*);
00595
00596 void dataCacheInvalidate( simAddress addr );
00597
00598 };
00599
00600
00601 #define CREATE_VECTOR_P(P,N) (BITMAP_SET_P(P->use_spec_cv, CV_BMAP_SZ, (N)) \
00602 ? P->spec_create_vector[N] \
00603 : P->create_vector[N])
00604 #define CREATE_VECTOR(N) (BITMAP_SET_P(use_spec_cv, CV_BMAP_SZ, (N))\
00605 ? spec_create_vector[N] \
00606 : create_vector[N])
00607
00608
00609 #define CREATE_VECTOR_RT(N) (BITMAP_SET_P(use_spec_cv, CV_BMAP_SZ, (N))\
00610 ? spec_create_vector_rt[N] \
00611 : create_vector_rt[N])
00612
00613
00614 #define SET_CREATE_VECTOR(N, L) (spec_mode \
00615 ? (BITMAP_SET(use_spec_cv, CV_BMAP_SZ, (N)),\
00616 spec_create_vector[N] = (L)) \
00617 : (create_vector[N] = (L)))
00618
00619
00620 #ifdef TARGET_PPC
00621
00622 #define IS_MULT_LSQ(op) 0
00623 #else
00624 #define IS_MULT_LSQ(op) FALSE
00625 #endif
00626
00627 #endif