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sst/core/techModels/libMcPATbeta/arch_const.h

00001 /*****************************************************************************
00002  *                                McPAT
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00006  *
00007  * Permission to use, copy, and modify this software and its documentation is
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00011  * thereof, and both notices must appear in supporting documentation.
00012  *
00013  * Any User of the software ("User"), by accessing and using it, agrees to the
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00019  * software by User, including but not limited to those affording
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00048 
00049 #ifndef ARCH_CONST_H_
00050 #define ARCH_CONST_H_
00051 
00052 typedef struct{
00053         unsigned int capacity;
00054         unsigned int assoc;//fully
00055         unsigned int blocksize;
00056 } array_inputs;
00057 
00058 //Do Not change, unless you want to bypass the XML interface and do not care about the default values.
00059 //Global parameters
00060 const int                       number_of_cores =       8;
00061 const int                       number_of_L2s   =       1;
00062 const int                       number_of_L3s   =       1;
00063 const int                       number_of_NoCs  =       1;
00064 
00065 const double            archi_F_sz_nm   =       90.0;
00066 const unsigned int      dev_type                =       0;
00067 const double            CLOCKRATE               =       1.2*1e9;
00068 const double            AF                              =       0.5;
00069 //const bool                    inorder                 =       true;
00070 const bool                      embedded                =       false; //NEW
00071 
00072 const bool                      homogeneous_cores       =       true;
00073 const bool                      temperature             =       360;
00074 const int                       number_cache_levels     =       3;
00075 const int                       L1_property             =       0; //private 0; coherent 1, shared 2.
00076 const int                       L2_property             =       2;
00077 const bool              homogeneous_L2s =       true;
00078 const bool                  L3_property         =       2;
00079 const bool                      homogeneous_L3s =       true;
00080 const double            Max_area_deviation      =       50;
00081 const double        Max_dynamic_deviation       =50; //New
00082 const int                       opt_dynamic_power       =       1;
00083 const int                       opt_lakage_power        =       0;
00084 const int                       opt_area                        =       0;
00085 const int                       interconnect_projection_type    =       0;
00086 
00087 //******************************Core Parameters
00088 #if (inorder)
00089 const int opcode_length                 =       8;//Niagara
00090 const int reg_length                    =       5;//Niagara
00091 const int instruction_length    =       32;//Niagara
00092 const int data_width                    =       64;
00093 #else
00094 const int opcode_length                 =       8;//16;//Niagara
00095 const int reg_length                    =       7;//Niagara
00096 const int instruction_length    =       32;//Niagara
00097 const int data_width                    =       64;
00098 #endif
00099 
00100 
00101 //Caches
00102 //itlb
00103 const int itlbsize=512;
00104 const int itlbassoc=0;//fully
00105 const int itlbblocksize=8;
00106 //icache
00107 const int icachesize=32768;
00108 const int icacheassoc=4;
00109 const int icacheblocksize=32;
00110 //dtlb
00111 const int dtlbsize=512;
00112 const int dtlbassoc=0;//fully
00113 const int dtlbblocksize=8;
00114 //dcache
00115 const int dcachesize=32768;
00116 const int dcacheassoc=4;
00117 const int dcacheblocksize=32;
00118 const int dcache_write_buffers=8;
00119 
00120 //cache controllers
00121 //IB,
00122 const int numIBEntries                  =       64;
00123 const int IBsize                                =       64;//2*4*instruction_length/8*2;
00124 const int IBassoc                               =       0;//In Niagara it is still fully associ
00125 const int IBblocksize                   =       4;
00126 
00127 //IFB and MIL should have the same parameters CAM
00128 const int IFBsize=128;//
00129 const int IFBassoc=0;//In Niagara it is still fully associ
00130 const int IFBblocksize=4;
00131 
00132 
00133 
00134 
00135 const int icache_write_buffers=8;
00136 
00137 //register file RAM
00138 const int regfilesize=5760;
00139 const int regfileassoc=1;
00140 const int regfileblocksize=18;
00141 //regwin  RAM
00142 const int regwinsize=256;
00143 const int regwinassoc=1;
00144 const int regwinblocksize=8;
00145 
00146 
00147 
00148 //store buffer, lsq
00149 const int lsqsize=512;
00150 const int lsqassoc=0;
00151 const int lsqblocksize=8;
00152 
00153 //data fill queue RAM
00154 const int dfqsize=1024;
00155 const int dfqassoc=1;
00156 const int dfqblocksize=16;
00157 
00158 //outside the cores
00159 //L2 cache bank
00160 const int l2cachesize=262144;
00161 const int l2cacheassoc=16;
00162 const int l2cacheblocksize=64;
00163 
00164 //L2 directory
00165 const int l2dirsize=1024;
00166 const int l2dirassoc=0;
00167 const int l2dirblocksize=2;
00168 
00169 //crossbar
00170 //PCX
00171 const int PCX_NUMBER_INPUT_PORTS_CROSSBAR = 8;
00172 const int PCX_NUMBER_OUTPUT_PORTS_CROSSBAR = 9;
00173 const int PCX_NUMBER_SIGNALS_PER_PORT_CROSSBAR =144;
00174 //PCX buffer RAM
00175 const int pcx_buffersize=1024;
00176 const int pcx_bufferassoc=1;
00177 const int pcx_bufferblocksize=32;
00178 const int pcx_numbuffer=5;
00179 //pcx arbiter
00180 const int pcx_arbsize=128;
00181 const int pcx_arbassoc=1;
00182 const int pcx_arbblocksize=2;
00183 const int pcx_numarb=5;
00184 
00185 //CPX
00186 const int CPX_NUMBER_INPUT_PORTS_CROSSBAR = 5;
00187 const int CPX_NUMBER_OUTPUT_PORTS_CROSSBAR = 8;
00188 const int CPX_NUMBER_SIGNALS_PER_PORT_CROSSBAR =150;
00189 //CPX buffer RAM
00190 const int cpx_buffersize=1024;
00191 const int cpx_bufferassoc=1;
00192 const int cpx_bufferblocksize=32;
00193 const int cpx_numbuffer=8;
00194 //cpx arbiter
00195 const int cpx_arbsize=128;
00196 const int cpx_arbassoc=1;
00197 const int cpx_arbblocksize=2;
00198 const int cpx_numarb=8;
00199 
00200 
00201 
00202 
00203 
00204 const int numPhysFloatRegs=256;
00205 const int numPhysIntRegs=32;
00206 const int numROBEntries=192;
00207 const int umRobs=1;
00208 
00209 const int BTBEntries=4096;
00210 const int BTBTagSize=16;
00211 const int LFSTSize=1024;
00212 const int LQEntries=32;
00213 const int RASSize=16;
00214 const int SQEntries=32;
00215 const int SSITSize=1024;
00216 const int activity=0;
00217 const int backComSize=5;
00218 const int cachePorts=200;
00219 const int choiceCtrBits=2;
00220 const int choicePredictorSize=8192;
00221 
00222 
00223 const int commitWidth=8;
00224 const int decodeWidth=8;
00225 const int dispatchWidth=8;
00226 const int fetchWidth=8;
00227 const int issueWidth=1;
00228 const int renameWidth=8;
00229 //what is this forwardComSize=5??
00230 
00231 const int globalCtrBits=2;
00232 const int globalHistoryBits=13;
00233 const int globalPredictorSize=8192;
00234 
00235 
00236 
00237 const int localCtrBits=2;
00238 const int localHistoryBits=11;
00239 const int localHistoryTableSize=2048;
00240 const int localPredictorSize=2048;
00241 
00242 const double Woutdrvnandn       =30 *0.09;//(24.0 * LSCALE)
00243 const double Woutdrvnandp       =12.5 *0.09;//(10.0 * LSCALE)
00244 const double Woutdrvnorn        =7.5*0.09;//(6.0 * LSCALE)
00245 const double Woutdrvnorp  =50 * 0.09;// (40.0 * LSCALE)
00246 const double Woutdrivern        =60*0.09;//(48.0 * LSCALE)
00247 const double Woutdriverp        =100 * 0.09;//(80.0 * LSCALE)
00248 
00249 /*
00250 smtCommitPolicy=RoundRobin
00251 smtFetchPolicy=SingleThread
00252 smtIQPolicy=Partitioned
00253 smtIQThreshold=100
00254 smtLSQPolicy=Partitioned
00255 smtLSQThreshold=100
00256 smtNumFetchingThreads=1
00257 smtROBPolicy=Partitioned
00258 smtROBThreshold=100
00259 squashWidth=8
00260 */
00261 
00262 /*
00263 prefetch_access=false
00264 prefetch_cache_check_push=true
00265 prefetch_data_accesses_only=false
00266 prefetch_degree=1
00267 prefetch_latency=10000
00268 prefetch_miss=false
00269 prefetch_past_page=false
00270 prefetch_policy=none
00271 prefetch_serial_squash=false
00272 prefetch_use_cpu_id=true
00273 prefetcher_size=100
00274 prioritizeRequests=false
00275 repl=Null
00276 
00277 
00278 split=false
00279 split_size=0
00280 subblock_size=0
00281 tgts_per_mshr=20
00282 trace_addr=0
00283 two_queue=false
00284 
00285 cpu_side=system.cpu0.dcache_port
00286 mem_side=system.tol2bus.port[2]
00287 */
00288 
00289 //[system.cpu0.dtb]
00290 //type=AlphaDT
00291 
00292 
00293 #endif /* ARCH_CONST_H_ */

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