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sst/core/techModels/libMcPATbeta/parameter.h

00001 /*------------------------------------------------------------
00002  *                              CACTI 6.5
00003  *         Copyright 2008 Hewlett-Packard Development Corporation
00004  *                         All Rights Reserved
00005  *
00006  * Permission to use, copy, and modify this software and its documentation is
00007  * hereby granted only under the following terms and conditions.  Both the
00008  * above copyright notice and this permission notice must appear in all copies
00009  * of the software, derivative works or modified versions, and any portions
00010  * thereof, and both notices must appear in supporting documentation.
00011  *
00012  * Users of this software agree to the terms and conditions set forth herein, and
00013  * hereby grant back to Hewlett-Packard Company and its affiliated companies ("HP")
00014  * a non-exclusive, unrestricted, royalty-free right and license under any changes,
00015  * enhancements or extensions  made to the core functions of the software, including
00016  * but not limited to those affording compatibility with other hardware or software
00017  * environments, but excluding applications which incorporate this software.
00018  * Users further agree to use their best efforts to return to HP any such changes,
00019  * enhancements or extensions that they make and inform HP of noteworthy uses of
00020  * this software.  Correspondence should be provided to HP at:
00021  *
00022  *                       Director of Intellectual Property Licensing
00023  *                       Office of Strategy and Technology
00024  *                       Hewlett-Packard Company
00025  *                       1501 Page Mill Road
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00027  *
00028  * This software may be distributed (but not offered for sale or transferred
00029  * for compensation) to third parties, provided such third parties agree to
00030  * abide by the terms and conditions of this notice.
00031  *
00032  * THE SOFTWARE IS PROVIDED "AS IS" AND HP DISCLAIMS ALL
00033  * WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
00034  * OF MERCHANTABILITY AND FITNESS.   IN NO EVENT SHALL HP
00035  * CORPORATION BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
00036  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
00037  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS
00038  * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
00039  * SOFTWARE.
00040  *------------------------------------------------------------*/
00041 
00042 
00043 
00044 #ifndef __PARAMETER_H__
00045 #define __PARAMETER_H__
00046 
00047 #include "area.h"
00048 #include "const.h"
00049 #include "cacti_interface.h"
00050 #include "io.h"
00051 
00052 // parameters which are functions of certain device technology
00053 class TechnologyParameter
00054 {
00055  public:
00056   class DeviceType
00057   {
00058    public:
00059     double C_g_ideal;
00060     double C_fringe;
00061     double C_overlap;
00062     double C_junc;  // C_junc_area
00063     double C_junc_sidewall;
00064     double l_phy;
00065     double l_elec;
00066     double R_nch_on;
00067     double R_pch_on;
00068     double Vdd;
00069     double Vth;
00070     double I_on_n;
00071     double I_on_p;
00072     double I_off_n;
00073     double I_off_p;
00074     double I_g_on_n;
00075     double I_g_on_p;
00076     double C_ox;
00077     double t_ox;
00078     double n_to_p_eff_curr_drv_ratio;
00079     double long_channel_leakage_reduction;
00080 
00081     DeviceType(): C_g_ideal(0), C_fringe(0), C_overlap(0), C_junc(0),
00082                   C_junc_sidewall(0), l_phy(0), l_elec(0), R_nch_on(0), R_pch_on(0),
00083                   Vdd(0), Vth(0),
00084                   I_on_n(0), I_on_p(0), I_off_n(0), I_off_p(0),I_g_on_n(0),I_g_on_p(0),
00085                   C_ox(0), t_ox(0), n_to_p_eff_curr_drv_ratio(0), long_channel_leakage_reduction(0) { };
00086     void reset()
00087     {
00088       C_g_ideal = 0;
00089       C_fringe  = 0;
00090       C_overlap = 0;
00091       C_junc    = 0;
00092       l_phy     = 0;
00093       l_elec    = 0;
00094       R_nch_on  = 0;
00095       R_pch_on  = 0;
00096       Vdd       = 0;
00097       Vth       = 0;
00098       I_on_n    = 0;
00099       I_on_p    = 0;
00100       I_off_n   = 0;
00101       I_off_p   = 0;
00102       I_g_on_n   = 0;
00103       I_g_on_p   = 0;
00104       C_ox      = 0;
00105       t_ox      = 0;
00106       n_to_p_eff_curr_drv_ratio = 0;
00107       long_channel_leakage_reduction = 0;
00108     }
00109 
00110     void display(uint32_t indent = 0);
00111   };
00112   class InterconnectType
00113   {
00114    public:
00115     double pitch;
00116     double R_per_um;
00117     double C_per_um;
00118     double horiz_dielectric_constant;
00119     double vert_dielectric_constant;
00120     double aspect_ratio;
00121     double miller_value;
00122     double ild_thickness;
00123 
00124     InterconnectType(): pitch(0), R_per_um(0), C_per_um(0) { };
00125 
00126     void reset()
00127     {
00128       pitch = 0;
00129       R_per_um = 0;
00130       C_per_um = 0;
00131       horiz_dielectric_constant = 0;
00132       vert_dielectric_constant = 0;
00133       aspect_ratio = 0;
00134       miller_value = 0;
00135       ild_thickness = 0;
00136     }
00137 
00138     void display(uint32_t indent = 0);
00139   };
00140   class MemoryType
00141   {
00142    public:
00143     double b_w;
00144     double b_h;
00145     double cell_a_w;
00146     double cell_pmos_w;
00147     double cell_nmos_w;
00148     double Vbitpre;
00149 
00150     void reset()
00151     {
00152       b_w = 0;
00153       b_h = 0;
00154       cell_a_w = 0;
00155       cell_pmos_w = 0;
00156       cell_nmos_w = 0;
00157       Vbitpre = 0;
00158     }
00159 
00160     void display(uint32_t indent = 0);
00161   };
00162 
00163   class ScalingFactor
00164   {
00165    public:
00166     double logic_scaling_co_eff;
00167     double core_tx_density;
00168     double long_channel_leakage_reduction;
00169 
00170     ScalingFactor(): logic_scaling_co_eff(0), core_tx_density(0),
00171     long_channel_leakage_reduction(0) { };
00172 
00173     void reset()
00174     {
00175       logic_scaling_co_eff= 0;
00176       core_tx_density = 0;
00177       long_channel_leakage_reduction= 0;
00178     }
00179 
00180     void display(uint32_t indent = 0);
00181   };
00182 
00183   double ram_wl_stitching_overhead_;
00184   double min_w_nmos_;
00185   double max_w_nmos_;
00186   double max_w_nmos_dec;
00187   double unit_len_wire_del;
00188   double FO4;
00189   double kinv;
00190   double vpp;
00191   double w_sense_en;
00192   double w_sense_n;
00193   double w_sense_p;
00194   double sense_delay;
00195   double sense_dy_power;
00196   double w_iso;
00197   double w_poly_contact;
00198   double spacing_poly_to_poly;
00199   double spacing_poly_to_contact;
00200 
00201   double w_comp_inv_p1;
00202   double w_comp_inv_p2;
00203   double w_comp_inv_p3;
00204   double w_comp_inv_n1;
00205   double w_comp_inv_n2;
00206   double w_comp_inv_n3;
00207   double w_eval_inv_p;
00208   double w_eval_inv_n;
00209   double w_comp_n;
00210   double w_comp_p;
00211 
00212   double dram_cell_I_on;
00213   double dram_cell_Vdd;
00214   double dram_cell_I_off_worst_case_len_temp;
00215   double dram_cell_C;
00216   double gm_sense_amp_latch;
00217 
00218   double w_nmos_b_mux;
00219   double w_nmos_sa_mux;
00220   double w_pmos_bl_precharge;
00221   double w_pmos_bl_eq;
00222   double MIN_GAP_BET_P_AND_N_DIFFS;
00223   double MIN_GAP_BET_SAME_TYPE_DIFFS;
00224   double HPOWERRAIL;
00225   double cell_h_def;
00226 
00227   double chip_layout_overhead;
00228   double macro_layout_overhead;
00229   double sckt_co_eff;
00230 
00231   double fringe_cap;
00232 
00233   uint64_t h_dec;
00234 
00235   DeviceType sram_cell;   // SRAM cell transistor
00236   DeviceType dram_acc;    // DRAM access transistor
00237   DeviceType dram_wl;     // DRAM wordline transistor
00238   DeviceType peri_global; // peripheral global
00239   DeviceType cam_cell;   // SRAM cell transistor
00240 
00241   InterconnectType wire_local;
00242   InterconnectType wire_inside_mat;
00243   InterconnectType wire_outside_mat;
00244 
00245   ScalingFactor scaling_factor;
00246 
00247   MemoryType sram;
00248   MemoryType dram;
00249   MemoryType cam;
00250 
00251   void display(uint32_t indent = 0);
00252 
00253   void reset()
00254   {
00255     dram_cell_Vdd  = 0;
00256     dram_cell_I_on = 0;
00257     dram_cell_C    = 0;
00258     vpp            = 0;
00259 
00260     sense_delay               = 0;
00261     sense_dy_power            = 0;
00262     fringe_cap                = 0;
00263 //    horiz_dielectric_constant = 0;
00264 //    vert_dielectric_constant  = 0;
00265 //    aspect_ratio              = 0;
00266 //    miller_value              = 0;
00267 //    ild_thickness             = 0;
00268 
00269     dram_cell_I_off_worst_case_len_temp = 0;
00270 
00271     sram_cell.reset();
00272     dram_acc.reset();
00273     dram_wl.reset();
00274     peri_global.reset();
00275     cam_cell.reset();
00276 
00277     scaling_factor.reset();
00278 
00279     wire_local.reset();
00280     wire_inside_mat.reset();
00281     wire_outside_mat.reset();
00282 
00283     sram.reset();
00284     dram.reset();
00285     cam.reset();
00286 
00287     chip_layout_overhead  = 0;
00288     macro_layout_overhead = 0;
00289     sckt_co_eff           = 0;
00290   }
00291 };
00292 
00293 
00294 
00295 class DynamicParameter
00296 {
00297   public:
00298     bool is_tag;
00299     bool pure_ram;
00300     bool pure_cam;
00301     bool fully_assoc;
00302     int tagbits;
00303     int num_subarrays;  // only for leakage computation  -- the number of subarrays per bank
00304     int num_mats;       // only for leakage computation  -- the number of mats per bank
00305     double Nspd;
00306     int Ndwl;
00307     int Ndbl;
00308     int Ndcm;
00309     int deg_bl_muxing;
00310     int deg_senseamp_muxing_non_associativity;
00311     int Ndsam_lev_1;
00312     int Ndsam_lev_2;
00313     int number_addr_bits_mat;             // per port
00314     int number_subbanks_decode;           // per_port
00315     int num_di_b_bank_per_port;
00316     int num_do_b_bank_per_port;
00317     int num_di_b_mat;
00318     int num_do_b_mat;
00319     int num_di_b_subbank;
00320     int num_do_b_subbank;
00321 
00322     int num_si_b_mat;
00323     int num_so_b_mat;
00324     int num_si_b_subbank;
00325     int num_so_b_subbank;
00326         int num_si_b_bank_per_port;
00327         int num_so_b_bank_per_port;
00328 
00329     int number_way_select_signals_mat;
00330     int num_act_mats_hor_dir;
00331 
00332     int num_act_mats_hor_dir_sl;
00333     bool is_dram;
00334     double V_b_sense;
00335     unsigned int num_r_subarray;
00336     unsigned int num_c_subarray;
00337     int tag_num_r_subarray;//sheng: fully associative cache tag and data must be computed together, data and tag must be separate
00338     int tag_num_c_subarray;
00339     int data_num_r_subarray;
00340     int data_num_c_subarray;
00341     int num_mats_h_dir;
00342     int num_mats_v_dir;
00343     uint32_t ram_cell_tech_type;
00344     double dram_refresh_period;
00345 
00346     DynamicParameter();
00347     DynamicParameter(
00348         bool         is_tag_,
00349         int          pure_ram_,
00350         int          pure_cam_,
00351         double       Nspd_,
00352         unsigned int Ndwl_,
00353         unsigned int Ndbl_,
00354         unsigned int Ndcm_,
00355         unsigned int Ndsam_lev_1_,
00356         unsigned int Ndsam_lev_2_,
00357         bool         is_main_mem_);
00358 
00359     int use_inp_params;
00360     unsigned int num_rw_ports;
00361     unsigned int num_rd_ports;
00362     unsigned int num_wr_ports;
00363     unsigned int num_se_rd_ports;  // number of single ended read ports
00364     unsigned int num_search_ports;
00365     unsigned int out_w;// == nr_bits_out
00366     bool   is_main_mem;
00367     Area   cell, cam_cell;//cell is the sram_cell in both nomal cache/ram and FA.
00368     bool   is_valid;
00369 };
00370 
00371 
00372 
00373 extern InputParameter * g_ip;
00374 extern TechnologyParameter g_tp;
00375 
00376 #endif
00377 

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