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sst/core/techModels/libMcPAT/cacti_interface.h

00001 /*****************************************************************************
00002  *                                McPAT
00003  *                      SOFTWARE LICENSE AGREEMENT
00004  *            Copyright 2009 Hewlett-Packard Development Company, L.P.
00005  *                          All Rights Reserved
00006  *
00007  * Permission to use, copy, and modify this software and its documentation is
00008  * hereby granted only under the following terms and conditions.  Both the
00009  * above copyright notice and this permission notice must appear in all copies
00010  * of the software, derivative works or modified versions, and any portions
00011  * thereof, and both notices must appear in supporting documentation.
00012  *
00013  * Any User of the software ("User"), by accessing and using it, agrees to the
00014  * terms and conditions set forth herein, and hereby grants back to Hewlett-
00015  * Packard Development Company, L.P. and its affiliated companies ("HP") a
00016  * non-exclusive, unrestricted, royalty-free right and license to copy,
00017  * modify, distribute copies, create derivate works and publicly display and
00018  * use, any changes, modifications, enhancements or extensions made to the
00019  * software by User, including but not limited to those affording
00020  * compatibility with other hardware or software, but excluding pre-existing
00021  * software applications that may incorporate the software.  User further
00022  * agrees to use its best efforts to inform HP of any such changes,
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00024  *
00025  * Correspondence should be provided to HP at:
00026  *
00027  * Director of Intellectual Property Licensing
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00029  * Hewlett-Packard Company
00030  * 1501 Page Mill Road
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00032  *
00033  * The software may be further distributed by User (but not offered for
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00037  *
00038  * THE SOFTWARE IS PROVIDED "AS IS" WITH ANY AND ALL ERRORS AND DEFECTS
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00047  ***************************************************************************/
00048 #ifndef __CACTI_INTERFACE_H__
00049 #define __CACTI_INTERFACE_H__
00050 
00051 
00052 class powerComponents
00053 {
00054  public:
00055   double dynamic;
00056   double sc;
00057   double leakage;
00058   double gonleakage;
00059 
00060   powerComponents() : dynamic(0), sc(0), leakage(0), gonleakage(0) { }
00061   powerComponents(const powerComponents & obj) { *this = obj; }
00062   powerComponents & operator=(const powerComponents & rhs)
00063   {
00064     dynamic     = rhs.dynamic;
00065     sc                  = rhs.sc;
00066     leakage     = rhs.leakage;
00067     gonleakage  = rhs.gonleakage;
00068     return *this;
00069   }
00070   void reset() { dynamic = 0; leakage = 0; sc = 0; gonleakage = 0; }
00071 
00072   friend powerComponents operator+(const powerComponents & x, const powerComponents & y);
00073 };
00074 
00075 class powerDef
00076 {
00077  public:
00078   powerComponents readOp;
00079   powerComponents writeOp;
00080 
00081   powerDef() : readOp(), writeOp() { }
00082   void reset() { readOp.reset(); writeOp.reset(); }
00083 
00084   friend powerDef operator+(const powerDef & x, const powerDef & y);
00085 };
00086 
00087 
00088 
00089 class InputParameter
00090 {
00091  public:
00092   InputParameter() {};
00093 
00094   unsigned int cache_sz;
00095   unsigned int line_sz;
00096   unsigned int assoc;
00097   unsigned int nbanks;
00098   unsigned int out_w;  // == nr_bits_out
00099   bool     specific_tag;
00100   unsigned int tag_w;
00101   unsigned int access_mode;
00102   unsigned int obj_func_dyn_energy;
00103   unsigned int obj_func_dyn_power;
00104   unsigned int obj_func_leak_power;
00105   unsigned int obj_func_cycle_t;
00106 
00107   double   F_sz_nm;          // feature size in nm
00108   double   F_sz_um;          // feature size in um
00109   unsigned int num_rw_ports;
00110   unsigned int num_rd_ports;
00111   unsigned int num_wr_ports;
00112   unsigned int num_se_rd_ports;  // number of single ended read ports
00113   bool     is_main_mem;
00114   bool     is_cache;
00115   bool     rpters_in_htree;  // if there are repeaters in htree segment
00116   unsigned int ver_htree_wires_over_array;
00117   unsigned int broadcast_addr_din_over_ver_htrees;
00118   unsigned int temp;
00119 
00120   double   max_area_t_constraint_perc;
00121   double   max_acc_t_constraint_perc;
00122   double   max_perc_diff_in_delay_fr_best_delay_rptr_sol;
00123   unsigned int ram_cell_tech_type;
00124   unsigned int peri_global_tech_type;
00125   unsigned int data_arr_ram_cell_tech_type;
00126   unsigned int data_arr_peri_global_tech_type;
00127   unsigned int tag_arr_ram_cell_tech_type;
00128   unsigned int tag_arr_peri_global_tech_type;
00129 
00130   unsigned int burst_len;
00131   unsigned int int_prefetch_w;
00132   unsigned int page_sz_bits;
00133 
00134   unsigned int ic_proj_type;      // inteconnect_projection_type
00135   unsigned int wire_is_mat_type;  // wire_outside_mat_type
00136   unsigned int wire_os_mat_type;  // wire_inside_mat_type
00137 
00138   // parameters derived from input parameters
00139   bool     fast_access;
00140   unsigned int block_sz;
00141   unsigned int tag_assoc;
00142   unsigned int data_assoc;
00143   bool     is_seq_acc;
00144   bool     fully_assoc;
00145   unsigned int nsets;  // == number_of_sets
00146 
00147   // parameters about crossbar and links
00148   double LENGTH_INTERCONNECT_FROM_BANK_TO_CROSSBAR; //3791 // 2880//micron
00149 
00150   bool IS_CROSSBAR;
00151   unsigned int NUMBER_INPUT_PORTS_CROSSBAR ;
00152   unsigned int NUMBER_OUTPUT_PORTS_CROSSBAR ;
00153   unsigned int NUMBER_SIGNALS_PER_PORT_CROSSBAR ;
00154 
00155   //parameters for design constraint
00156   double throughput;
00157   double latency;
00158   bool pipelinable;
00159   int pipeline_stages;
00160   int per_stage_vector;
00161   bool with_clock_grid;
00162 };
00163 
00164 
00165 typedef struct{
00166   int Ndwl;
00167   int Ndbl;
00168   double Nspd;
00169   int deg_bitline_muxing;
00170   int Ndsam_lev_1;
00171   int Ndsam_lev_2;
00172   int number_activated_mats_horizontal_direction;
00173   int number_subbanks;
00174   int page_size_in_bits;
00175   double delay_route_to_bank;
00176   double delay_crossbar;
00177   double delay_addr_din_horizontal_htree;
00178   double delay_addr_din_vertical_htree;
00179   double delay_row_predecode_driver_and_block;
00180   double delay_row_decoder;
00181   double delay_bitlines;
00182   double delay_sense_amp;
00183   double delay_subarray_output_driver;
00184   double delay_bit_mux_predecode_driver_and_block;
00185   double delay_bit_mux_decoder;
00186   double delay_senseamp_mux_lev_1_predecode_driver_and_block;
00187   double delay_senseamp_mux_lev_1_decoder;
00188   double delay_senseamp_mux_lev_2_predecode_driver_and_block;
00189   double delay_senseamp_mux_lev_2_decoder;
00190   double delay_dout_vertical_htree;
00191   double delay_dout_horizontal_htree;
00192   double delay_comparator;
00193   double access_time;
00194   double cycle_time;
00195   double multisubbank_interleave_cycle_time;
00196   double delay_request_network;
00197   double delay_inside_mat;
00198   double delay_reply_network;
00199   double trcd;
00200   double cas_latency;
00201   double precharge_delay;
00202   powerDef power_routing_to_bank;
00203   powerDef power_addr_horizontal_htree;
00204   powerDef power_datain_horizontal_htree;
00205   powerDef power_dataout_horizontal_htree;
00206   powerDef power_addr_vertical_htree;
00207   powerDef power_datain_vertical_htree;
00208   powerDef power_row_predecoder_drivers;
00209   powerDef power_row_predecoder_blocks;
00210   powerDef power_row_decoders;
00211   powerDef power_bit_mux_predecoder_drivers;
00212   powerDef power_bit_mux_predecoder_blocks;
00213   powerDef power_bit_mux_decoders;
00214   powerDef power_senseamp_mux_lev_1_predecoder_drivers;
00215   powerDef power_senseamp_mux_lev_1_predecoder_blocks;
00216   powerDef power_senseamp_mux_lev_1_decoders;
00217   powerDef power_senseamp_mux_lev_2_predecoder_drivers;
00218   powerDef power_senseamp_mux_lev_2_predecoder_blocks;
00219   powerDef power_senseamp_mux_lev_2_decoders;
00220   powerDef power_bitlines;
00221   powerDef power_sense_amps;
00222   powerDef power_prechg_eq_drivers;
00223   powerDef power_output_drivers_at_subarray;
00224   powerDef power_dataout_vertical_htree;
00225   powerDef power_comparators;
00226   powerDef power_crossbar;
00227   powerDef total_power;
00228   double area;
00229   double all_banks_height;
00230   double all_banks_width;
00231   double bank_height;
00232   double bank_width;
00233   double subarray_memory_cell_area_height;
00234   double subarray_memory_cell_area_width;
00235   double mat_height;
00236   double mat_width;
00237   double routing_area_height_within_bank;
00238   double routing_area_width_within_bank;
00239   double area_efficiency;
00240   double perc_power_dyn_routing_to_bank;
00241   double perc_power_dyn_addr_horizontal_htree;
00242   double perc_power_dyn_datain_horizontal_htree;
00243   double perc_power_dyn_dataout_horizontal_htree;
00244   double perc_power_dyn_addr_vertical_htree;
00245   double perc_power_dyn_datain_vertical_htree;
00246   double perc_power_dyn_row_predecoder_drivers;
00247   double perc_power_dyn_row_predecoder_blocks;
00248   double perc_power_dyn_row_decoders;
00249   double perc_power_dyn_bit_mux_predecoder_drivers;
00250   double perc_power_dyn_bit_mux_predecoder_blocks;
00251   double perc_power_dyn_bit_mux_decoders;
00252   double perc_power_dyn_senseamp_mux_lev_1_predecoder_drivers;
00253   double perc_power_dyn_senseamp_mux_lev_1_predecoder_blocks;
00254   double perc_power_dyn_senseamp_mux_lev_1_decoders;
00255   double perc_power_dyn_senseamp_mux_lev_2_predecoder_drivers;
00256   double perc_power_dyn_senseamp_mux_lev_2_predecoder_blocks;
00257   double perc_power_dyn_senseamp_mux_lev_2_decoders;
00258   double perc_power_dyn_bitlines;
00259   double perc_power_dyn_sense_amps;
00260   double perc_power_dyn_prechg_eq_drivers;
00261   double perc_power_dyn_subarray_output_drivers;
00262   double perc_power_dyn_dataout_vertical_htree;
00263   double perc_power_dyn_comparators;
00264   double perc_power_dyn_crossbar;
00265   double perc_power_dyn_spent_outside_mats;
00266   double perc_power_leak_routing_to_bank;
00267   double perc_power_leak_addr_horizontal_htree;
00268   double perc_power_leak_datain_horizontal_htree;
00269   double perc_power_leak_dataout_horizontal_htree;
00270   double perc_power_leak_addr_vertical_htree;
00271   double perc_power_leak_datain_vertical_htree;
00272   double perc_power_leak_row_predecoder_drivers;
00273   double perc_power_leak_row_predecoder_blocks;
00274   double perc_power_leak_row_decoders;
00275   double perc_power_leak_bit_mux_predecoder_drivers;
00276   double perc_power_leak_bit_mux_predecoder_blocks;
00277   double perc_power_leak_bit_mux_decoders;
00278   double perc_power_leak_senseamp_mux_lev_1_predecoder_drivers;
00279   double perc_power_leak_senseamp_mux_lev_1_predecoder_blocks;
00280   double perc_power_leak_senseamp_mux_lev_1_decoders;
00281   double perc_power_leak_senseamp_mux_lev_2_predecoder_drivers;
00282   double perc_power_leak_senseamp_mux_lev_2_predecoder_blocks;
00283   double perc_power_leak_senseamp_mux_lev_2_decoders;
00284   double perc_power_leak_bitlines;
00285   double perc_power_leak_sense_amps;
00286   double perc_power_leak_prechg_eq_drivers;
00287   double perc_power_leak_subarray_output_drivers;
00288   double perc_power_leak_dataout_vertical_htree;
00289   double perc_power_leak_comparators;
00290   double perc_power_leak_crossbar;
00291   double perc_leak_mats;
00292   double perc_active_mats;
00293   double refresh_power;
00294   double dram_refresh_period;
00295   double dram_array_availability;
00296   double dyn_read_energy_from_closed_page;
00297   double dyn_read_energy_from_open_page;
00298   double leak_power_subbank_closed_page;
00299   double leak_power_subbank_open_page;
00300   double leak_power_request_and_reply_networks;
00301   double activate_energy;
00302   double read_energy;
00303   double write_energy;
00304   double precharge_energy;
00305 } results_mem_array;
00306 
00307 
00308 typedef struct{
00309   results_mem_array tag_array;
00310   results_mem_array data_array;
00311   double access_time;
00312   double cycle_time;
00313   double area;
00314   double area_efficiency;
00315   powerDef power;
00316   double leak_power_with_sleep_transistors_in_mats;
00317   InputParameter ip;
00318   double cache_ht;
00319   double cache_len;
00320   char file_n[100];
00321   double vdd_periph_global;
00322   bool valid;
00323 } final_results;
00324 
00325 
00326 final_results cacti_interface(
00327   int cache_size,
00328   int line_size,
00329   int associativity,
00330   int rw_ports,
00331   int excl_read_ports,
00332   int excl_write_ports,
00333   int single_ended_read_ports,
00334   int banks,
00335   double tech_node,
00336   int output_width,
00337   int specific_tag,
00338   int tag_width,
00339   int access_mode,
00340   int cache,
00341   int main_mem,
00342   int obj_func_dynamic_energy,
00343   int obj_func_dynamic_power,
00344   int obj_func_leakage_power,
00345   int obj_func_cycle_time,
00346   int temp,
00347   int data_arr_ram_cell_tech_flavor_in,
00348   int data_arr_periph_global_tech_flavor_in,
00349   int tag_arr_ram_cell_tech_flavor_in,
00350   int tag_arr_periph_global_tech_flavor_in,
00351   int interconnect_projection_type_in,
00352   int wire_inside_mat_type_in,
00353   int wire_outside_mat_type_in,
00354   int REPEATERS_IN_HTREE_SEGMENTS_in,
00355   int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in,
00356   int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in,
00357   double MIN_PERCENT_WITHIN_BEST_AREA_in,
00358   double MIN_PERCENT_WITHIN_BEST_DELAY_in,
00359   double MAX_PERC_DIFF_IN_DELAY_FROM_BEST_DELAY_REPEATER_SOLUTION_in,
00360   int PAGE_SIZE_BITS_in,
00361   int BURST_SIZE_in,
00362   int INTERNAL_PREFETCH_WIDTH_in);
00363 
00364 final_results cacti_interface(const InputParameter *local_interface);
00365 
00366 final_results init_interface(const InputParameter *local_interface);
00367 
00368 #endif

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