00001 #if !defined(__QEMU_MIPS_EXEC_H__)
00002 #define __QEMU_MIPS_EXEC_H__
00003
00004
00005
00006 #include "config.h"
00007 #include "mips-defs.h"
00008 #include "dyngen-exec.h"
00009 #include "cpu-defs.h"
00010
00011 register struct CPUMIPSState *env asm(AREG0);
00012
00013 #include "cpu.h"
00014 #include "exec-all.h"
00015
00016 #if !defined(CONFIG_USER_ONLY)
00017 #include "softmmu_exec.h"
00018 #endif
00019
00020 void do_mtc0_status_debug(uint32_t old, uint32_t val);
00021 void do_mtc0_status_irqraise_debug(void);
00022 void dump_fpu(CPUState *env);
00023 void fpu_dump_state(CPUState *env, FILE *f,
00024 int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
00025 int flags);
00026
00027 void cpu_mips_clock_init (CPUState *env);
00028 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
00029
00030 static inline void env_to_regs(void)
00031 {
00032 }
00033
00034 static inline void regs_to_env(void)
00035 {
00036 }
00037
00038 static inline int cpu_halted(CPUState *env)
00039 {
00040 if (!env->halted)
00041 return 0;
00042 if (env->interrupt_request &
00043 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
00044 env->halted = 0;
00045 return 0;
00046 }
00047 return EXCP_HALTED;
00048 }
00049
00050 static inline void compute_hflags(CPUState *env)
00051 {
00052 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
00053 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
00054 MIPS_HFLAG_UX);
00055 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
00056 !(env->CP0_Status & (1 << CP0St_ERL)) &&
00057 !(env->hflags & MIPS_HFLAG_DM)) {
00058 env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
00059 }
00060 #if defined(TARGET_MIPS64)
00061 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
00062 (env->CP0_Status & (1 << CP0St_PX)) ||
00063 (env->CP0_Status & (1 << CP0St_UX)))
00064 env->hflags |= MIPS_HFLAG_64;
00065 if (env->CP0_Status & (1 << CP0St_UX))
00066 env->hflags |= MIPS_HFLAG_UX;
00067 #endif
00068 if ((env->CP0_Status & (1 << CP0St_CU0)) ||
00069 !(env->hflags & MIPS_HFLAG_KSU))
00070 env->hflags |= MIPS_HFLAG_CP0;
00071 if (env->CP0_Status & (1 << CP0St_CU1))
00072 env->hflags |= MIPS_HFLAG_FPU;
00073 if (env->CP0_Status & (1 << CP0St_FR))
00074 env->hflags |= MIPS_HFLAG_F64;
00075 if (env->insn_flags & ISA_MIPS32R2) {
00076 if (env->active_fpu.fcr0 & (1 << FCR0_F64))
00077 env->hflags |= MIPS_HFLAG_COP1X;
00078 } else if (env->insn_flags & ISA_MIPS32) {
00079 if (env->hflags & MIPS_HFLAG_64)
00080 env->hflags |= MIPS_HFLAG_COP1X;
00081 } else if (env->insn_flags & ISA_MIPS4) {
00082
00083
00084
00085
00086 if (env->CP0_Status & (1 << CP0St_CU3))
00087 env->hflags |= MIPS_HFLAG_COP1X;
00088 }
00089 }
00090
00091 #endif