Public Member Functions |
| LoadStoreU (ParseXML *XML_interface, int ithCore_, InputParameter *interface_ip_, const CoreDynParam &dyn_p_, bool exist_=true) |
void | computeEnergy (bool is_tdp=true) |
void | displayEnergy (uint32_t indent=0, int plevel=100, bool is_tdp=true) |
void | SSTcomputeEnergy (bool is_tdp=true, double dl1_read=0, double dl1_readmiss=0, double dl1_write=0, double dl1_writemiss=0, double LSQ_read=0, double LSQ_write=0, double loadQ_read=0, double loadQ_write=0) |
DataCache | SSTreturnDcache () |
ArrayST * | SSTreturnLSQ () |
ArrayST * | SSTreturnLoadQ () |
| LoadStoreU (ParseXML *XML_interface, int ithCore_, InputParameter *interface_ip_, const CoreDynParam &dyn_p_) |
void | computeEnergy (bool is_tdp=true) |
void | displayEnergy (uint32_t indent=0, int plevel=100, bool is_tdp=true) |
void | SSTcomputeEnergy (bool is_tdp=true, double dl1_read=0, double dl1_readmiss=0, double dl1_write=0, double dl1_writemiss=0, double LSQ_read=0, double LSQ_write=0) |
DataCache | SSTreturnDcache () |
ArrayST * | SSTreturnLSQ () |
ArrayST * | SSTreturnLoadQ () |
Data Fields |
ParseXML * | XML |
int | ithCore |
InputParameter | interface_ip |
CoreDynParam | coredynp |
enum Cache_policy | cache_p |
double | clockRate |
double | executionTime |
double | scktRatio |
double | chip_PR_overhead |
double | macro_PR_overhead |
double | lsq_height |
DataCache | dcache |
ArrayST * | LSQ |
ArrayST * | LoadQ |
bool | exist |
The documentation for this class was generated from the following files:
- sst/core/techModels/libMcPATbeta/core.h
- sst/core/techModels/libMcPATbeta06/core.h
- sst/core/techModels/libMcPATbeta/core.cc
- sst/core/techModels/libMcPATbeta06/core.cc