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00049 #ifndef __CACTI_INTERFACE_H__
00050 #define __CACTI_INTERFACE_H__
00051
00052 #include <map>
00053 #include <string>
00054 #include <vector>
00055 #include <list>
00056 #include <iostream>
00057 #include "const.h"
00058
00059 using namespace std;
00060
00061
00062 class min_values_t;
00063 class mem_array;
00064 class uca_org_t;
00065
00066
00067 class powerComponents
00068 {
00069 public:
00070 double dynamic;
00071 double leakage;
00072 double gate_leakage;
00073 double short_circuit;
00074
00075 powerComponents() : dynamic(0), leakage(0), gate_leakage(0), short_circuit(0) { }
00076 powerComponents(const powerComponents & obj) { *this = obj; }
00077 powerComponents & operator=(const powerComponents & rhs)
00078 {
00079 dynamic = rhs.dynamic;
00080 leakage = rhs.leakage;
00081 gate_leakage = rhs.gate_leakage;
00082 short_circuit = rhs.short_circuit;
00083 return *this;
00084 }
00085 void reset() { dynamic = 0; leakage = 0; gate_leakage = 0; short_circuit = 0;}
00086
00087 friend powerComponents operator+(const powerComponents & x, const powerComponents & y);
00088 friend powerComponents operator*(const powerComponents & x, double const * const y);
00089 };
00090
00091
00092
00093 class powerDef
00094 {
00095 public:
00096 powerComponents readOp;
00097 powerComponents writeOp;
00098 powerComponents searchOp;
00099
00100 powerDef() : readOp(), writeOp(), searchOp() { }
00101 void reset() { readOp.reset(); writeOp.reset(); searchOp.reset();}
00102
00103 friend powerDef operator+(const powerDef & x, const powerDef & y);
00104 friend powerDef operator*(const powerDef & x, double const * const y);
00105 };
00106
00107 class statsComponents
00108 {
00109 public:
00110 double access;
00111 double hit;
00112 double miss;
00113
00114 statsComponents() : access(0), hit(0), miss(0) {}
00115 statsComponents(const statsComponents & obj) { *this = obj; }
00116 statsComponents & operator=(const statsComponents & rhs)
00117 {
00118 access = rhs.access;
00119 hit = rhs.hit;
00120 miss = rhs.miss;
00121 return *this;
00122 }
00123 void reset() { access = 0; hit = 0; miss = 0;}
00124
00125 friend statsComponents operator+(const statsComponents & x, const statsComponents & y);
00126 friend statsComponents operator*(const statsComponents & x, double const * const y);
00127 };
00128
00129 class statsDef
00130 {
00131 public:
00132 statsComponents readAc;
00133 statsComponents writeAc;
00134 statsComponents searchAc;
00135
00136 statsDef() : readAc(), writeAc(),searchAc() { }
00137 void reset() { readAc.reset(); writeAc.reset();searchAc.reset();}
00138
00139 friend statsDef operator+(const statsDef & x, const statsDef & y);
00140 friend statsDef operator*(const statsDef & x, double const * const y);
00141 };
00142
00143 enum Wire_type
00144 {
00145 Global ,
00146 Global_5 ,
00147 Global_10 ,
00148 Global_20 ,
00149 Global_30 ,
00150 Low_swing ,
00151 Semi_global ,
00152 Transmission ,
00153 Optical ,
00154 Invalid_wtype
00155 };
00156
00157
00158
00159 class InputParameter
00160 {
00161 public:
00162 void parse_cfg(const string & infile);
00163
00164 bool error_checking();
00165 void display_ip();
00166
00167 unsigned int cache_sz;
00168 unsigned int line_sz;
00169 unsigned int assoc;
00170 unsigned int nbanks;
00171 unsigned int out_w;
00172 bool specific_tag;
00173 unsigned int tag_w;
00174 unsigned int access_mode;
00175 unsigned int obj_func_dyn_energy;
00176 unsigned int obj_func_dyn_power;
00177 unsigned int obj_func_leak_power;
00178 unsigned int obj_func_cycle_t;
00179
00180 double F_sz_nm;
00181 double F_sz_um;
00182 unsigned int num_rw_ports;
00183 unsigned int num_rd_ports;
00184 unsigned int num_wr_ports;
00185 unsigned int num_se_rd_ports;
00186 unsigned int num_search_ports;
00187 bool is_main_mem;
00188 bool is_cache;
00189 bool pure_ram;
00190 bool pure_cam;
00191 bool rpters_in_htree;
00192 unsigned int ver_htree_wires_over_array;
00193 unsigned int broadcast_addr_din_over_ver_htrees;
00194 unsigned int temp;
00195
00196 unsigned int ram_cell_tech_type;
00197 unsigned int peri_global_tech_type;
00198 unsigned int data_arr_ram_cell_tech_type;
00199 unsigned int data_arr_peri_global_tech_type;
00200 unsigned int tag_arr_ram_cell_tech_type;
00201 unsigned int tag_arr_peri_global_tech_type;
00202
00203 unsigned int burst_len;
00204 unsigned int int_prefetch_w;
00205 unsigned int page_sz_bits;
00206
00207 unsigned int ic_proj_type;
00208 unsigned int wire_is_mat_type;
00209 unsigned int wire_os_mat_type;
00210 enum Wire_type wt;
00211 int force_wiretype;
00212 bool print_input_args;
00213 unsigned int nuca_cache_sz;
00214 int ndbl, ndwl, nspd, ndsam1, ndsam2, ndcm;
00215 bool force_cache_config;
00216
00217 int cache_level;
00218 int cores;
00219 int nuca_bank_count;
00220 int force_nuca_bank;
00221
00222 int delay_wt, dynamic_power_wt, leakage_power_wt,
00223 cycle_time_wt, area_wt;
00224 int delay_wt_nuca, dynamic_power_wt_nuca, leakage_power_wt_nuca,
00225 cycle_time_wt_nuca, area_wt_nuca;
00226
00227 int delay_dev, dynamic_power_dev, leakage_power_dev,
00228 cycle_time_dev, area_dev;
00229 int delay_dev_nuca, dynamic_power_dev_nuca, leakage_power_dev_nuca,
00230 cycle_time_dev_nuca, area_dev_nuca;
00231 int ed;
00232 int nuca;
00233
00234 bool fast_access;
00235 unsigned int block_sz;
00236 unsigned int tag_assoc;
00237 unsigned int data_assoc;
00238 bool is_seq_acc;
00239 bool fully_assoc;
00240 unsigned int nsets;
00241 int print_detail;
00242
00243
00244 bool add_ecc_b_;
00245
00246 double throughput;
00247 double latency;
00248 bool pipelinable;
00249 int pipeline_stages;
00250 int per_stage_vector;
00251 bool with_clock_grid;
00252 };
00253
00254
00255 typedef struct{
00256 int Ndwl;
00257 int Ndbl;
00258 double Nspd;
00259 int deg_bl_muxing;
00260 int Ndsam_lev_1;
00261 int Ndsam_lev_2;
00262 int number_activated_mats_horizontal_direction;
00263 int number_subbanks;
00264 int page_size_in_bits;
00265 double delay_route_to_bank;
00266 double delay_crossbar;
00267 double delay_addr_din_horizontal_htree;
00268 double delay_addr_din_vertical_htree;
00269 double delay_row_predecode_driver_and_block;
00270 double delay_row_decoder;
00271 double delay_bitlines;
00272 double delay_sense_amp;
00273 double delay_subarray_output_driver;
00274 double delay_bit_mux_predecode_driver_and_block;
00275 double delay_bit_mux_decoder;
00276 double delay_senseamp_mux_lev_1_predecode_driver_and_block;
00277 double delay_senseamp_mux_lev_1_decoder;
00278 double delay_senseamp_mux_lev_2_predecode_driver_and_block;
00279 double delay_senseamp_mux_lev_2_decoder;
00280 double delay_input_htree;
00281 double delay_output_htree;
00282 double delay_dout_vertical_htree;
00283 double delay_dout_horizontal_htree;
00284 double delay_comparator;
00285 double access_time;
00286 double cycle_time;
00287 double multisubbank_interleave_cycle_time;
00288 double delay_request_network;
00289 double delay_inside_mat;
00290 double delay_reply_network;
00291 double trcd;
00292 double cas_latency;
00293 double precharge_delay;
00294 powerDef power_routing_to_bank;
00295 powerDef power_addr_input_htree;
00296 powerDef power_data_input_htree;
00297 powerDef power_data_output_htree;
00298 powerDef power_addr_horizontal_htree;
00299 powerDef power_datain_horizontal_htree;
00300 powerDef power_dataout_horizontal_htree;
00301 powerDef power_addr_vertical_htree;
00302 powerDef power_datain_vertical_htree;
00303 powerDef power_row_predecoder_drivers;
00304 powerDef power_row_predecoder_blocks;
00305 powerDef power_row_decoders;
00306 powerDef power_bit_mux_predecoder_drivers;
00307 powerDef power_bit_mux_predecoder_blocks;
00308 powerDef power_bit_mux_decoders;
00309 powerDef power_senseamp_mux_lev_1_predecoder_drivers;
00310 powerDef power_senseamp_mux_lev_1_predecoder_blocks;
00311 powerDef power_senseamp_mux_lev_1_decoders;
00312 powerDef power_senseamp_mux_lev_2_predecoder_drivers;
00313 powerDef power_senseamp_mux_lev_2_predecoder_blocks;
00314 powerDef power_senseamp_mux_lev_2_decoders;
00315 powerDef power_bitlines;
00316 powerDef power_sense_amps;
00317 powerDef power_prechg_eq_drivers;
00318 powerDef power_output_drivers_at_subarray;
00319 powerDef power_dataout_vertical_htree;
00320 powerDef power_comparators;
00321 powerDef power_crossbar;
00322 powerDef total_power;
00323 double area;
00324 double all_banks_height;
00325 double all_banks_width;
00326 double bank_height;
00327 double bank_width;
00328 double subarray_memory_cell_area_height;
00329 double subarray_memory_cell_area_width;
00330 double mat_height;
00331 double mat_width;
00332 double routing_area_height_within_bank;
00333 double routing_area_width_within_bank;
00334 double area_efficiency;
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00388 double refresh_power;
00389 double dram_refresh_period;
00390 double dram_array_availability;
00391 double dyn_read_energy_from_closed_page;
00392 double dyn_read_energy_from_open_page;
00393 double leak_power_subbank_closed_page;
00394 double leak_power_subbank_open_page;
00395 double leak_power_request_and_reply_networks;
00396 double activate_energy;
00397 double read_energy;
00398 double write_energy;
00399 double precharge_energy;
00400 } results_mem_array;
00401
00402
00403 class uca_org_t
00404 {
00405 public:
00406 mem_array * tag_array2;
00407 mem_array * data_array2;
00408 double access_time;
00409 double cycle_time;
00410 double area;
00411 double area_efficiency;
00412 powerDef power;
00413 double leak_power_with_sleep_transistors_in_mats;
00414 double cache_ht;
00415 double cache_len;
00416 char file_n[100];
00417 double vdd_periph_global;
00418 bool valid;
00419 results_mem_array tag_array;
00420 results_mem_array data_array;
00421
00422 void find_delay();
00423 void find_energy();
00424 void find_area();
00425 void find_cyc();
00426 };
00427
00428
00429 uca_org_t cacti_interface(const string & infile_name);
00430 uca_org_t cacti_interface(InputParameter * const local_interface);
00431 uca_org_t init_interface(InputParameter * const local_interface);
00432
00433 uca_org_t cacti_interface(
00434 int cache_size,
00435 int line_size,
00436 int associativity,
00437 int rw_ports,
00438 int excl_read_ports,
00439 int excl_write_ports,
00440 int single_ended_read_ports,
00441 int search_ports,
00442 int banks,
00443 double tech_node,
00444 int output_width,
00445 int specific_tag,
00446 int tag_width,
00447 int access_mode,
00448 int cache,
00449 int main_mem,
00450 int obj_func_delay,
00451 int obj_func_dynamic_power,
00452 int obj_func_leakage_power,
00453 int obj_func_area,
00454 int obj_func_cycle_time,
00455 int dev_func_delay,
00456 int dev_func_dynamic_power,
00457 int dev_func_leakage_power,
00458 int dev_func_area,
00459 int dev_func_cycle_time,
00460 int temp,
00461 int data_arr_ram_cell_tech_flavor_in,
00462 int data_arr_peri_global_tech_flavor_in,
00463 int tag_arr_ram_cell_tech_flavor_in,
00464 int tag_arr_peri_global_tech_flavor_in,
00465 int interconnect_projection_type_in,
00466 int wire_inside_mat_type_in,
00467 int wire_outside_mat_type_in,
00468 int REPEATERS_IN_HTREE_SEGMENTS_in,
00469 int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in,
00470 int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in,
00471 int PAGE_SIZE_BITS_in,
00472 int BURST_LENGTH_in,
00473 int INTERNAL_PREFETCH_WIDTH_in,
00474 int force_wiretype,
00475 int wiretype,
00476 int force_config,
00477 int ndwl,
00478 int ndbl,
00479 int nspd,
00480 int ndcm,
00481 int ndsam1,
00482 int ndsam2,
00483 int ecc);
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00528 class mem_array
00529 {
00530 public:
00531 int Ndwl;
00532 int Ndbl;
00533 double Nspd;
00534 int deg_bl_muxing;
00535 int Ndsam_lev_1;
00536 int Ndsam_lev_2;
00537 double access_time;
00538 double cycle_time;
00539 double multisubbank_interleave_cycle_time;
00540 double area_ram_cells;
00541 double area;
00542 powerDef power;
00543 double delay_senseamp_mux_decoder;
00544 double delay_before_subarray_output_driver;
00545 double delay_from_subarray_output_driver_to_output;
00546 double height;
00547 double width;
00548
00549 double delay_route_to_bank,
00550 delay_input_htree,
00551 delay_row_predecode_driver_and_block,
00552 delay_row_decoder,
00553 delay_bitlines,
00554 delay_sense_amp,
00555 delay_subarray_output_driver,
00556 delay_dout_htree,
00557 delay_comparator,
00558 delay_matchlines;
00559
00560 double all_banks_height,
00561 all_banks_width,
00562 area_efficiency;
00563
00564 powerDef power_routing_to_bank;
00565 powerDef power_addr_input_htree;
00566 powerDef power_data_input_htree;
00567 powerDef power_data_output_htree;
00568 powerDef power_htree_in_search;
00569 powerDef power_htree_out_search;
00570 powerDef power_row_predecoder_drivers;
00571 powerDef power_row_predecoder_blocks;
00572 powerDef power_row_decoders;
00573 powerDef power_bit_mux_predecoder_drivers;
00574 powerDef power_bit_mux_predecoder_blocks;
00575 powerDef power_bit_mux_decoders;
00576 powerDef power_senseamp_mux_lev_1_predecoder_drivers;
00577 powerDef power_senseamp_mux_lev_1_predecoder_blocks;
00578 powerDef power_senseamp_mux_lev_1_decoders;
00579 powerDef power_senseamp_mux_lev_2_predecoder_drivers;
00580 powerDef power_senseamp_mux_lev_2_predecoder_blocks;
00581 powerDef power_senseamp_mux_lev_2_decoders;
00582 powerDef power_bitlines;
00583 powerDef power_sense_amps;
00584 powerDef power_prechg_eq_drivers;
00585 powerDef power_output_drivers_at_subarray;
00586 powerDef power_dataout_vertical_htree;
00587 powerDef power_comparators;
00588
00589 powerDef power_cam_bitline_precharge_eq_drv;
00590 powerDef power_searchline;
00591 powerDef power_searchline_precharge;
00592 powerDef power_matchlines;
00593 powerDef power_matchline_precharge;
00594 powerDef power_matchline_to_wordline_drv;
00595
00596 min_values_t *arr_min;
00597 enum Wire_type wt;
00598
00599
00600 double activate_energy, read_energy, write_energy, precharge_energy,
00601 refresh_power, leak_power_subbank_closed_page, leak_power_subbank_open_page,
00602 leak_power_request_and_reply_networks;
00603
00604 double precharge_delay;
00605
00606 static bool lt(const mem_array * m1, const mem_array * m2);
00607 };
00608
00609
00610 #endif