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sst/core/techModels/libMcPAT/basic_components.h

00001 /*****************************************************************************
00002  *                                McPAT
00003  *                      SOFTWARE LICENSE AGREEMENT
00004  *            Copyright 2009 Hewlett-Packard Development Company, L.P.
00005  *                          All Rights Reserved
00006  *
00007  * Permission to use, copy, and modify this software and its documentation is
00008  * hereby granted only under the following terms and conditions.  Both the
00009  * above copyright notice and this permission notice must appear in all copies
00010  * of the software, derivative works or modified versions, and any portions
00011  * thereof, and both notices must appear in supporting documentation.
00012  *
00013  * Any User of the software ("User"), by accessing and using it, agrees to the
00014  * terms and conditions set forth herein, and hereby grants back to Hewlett-
00015  * Packard Development Company, L.P. and its affiliated companies ("HP") a
00016  * non-exclusive, unrestricted, royalty-free right and license to copy,
00017  * modify, distribute copies, create derivate works and publicly display and
00018  * use, any changes, modifications, enhancements or extensions made to the
00019  * software by User, including but not limited to those affording
00020  * compatibility with other hardware or software, but excluding pre-existing
00021  * software applications that may incorporate the software.  User further
00022  * agrees to use its best efforts to inform HP of any such changes,
00023  * modifications, enhancements or extensions.
00024  *
00025  * Correspondence should be provided to HP at:
00026  *
00027  * Director of Intellectual Property Licensing
00028  * Office of Strategy and Technology
00029  * Hewlett-Packard Company
00030  * 1501 Page Mill Road
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00032  *
00033  * The software may be further distributed by User (but not offered for
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00035  * condition that such third parties agree to abide by the terms and
00036  * conditions of this license.
00037  *
00038  * THE SOFTWARE IS PROVIDED "AS IS" WITH ANY AND ALL ERRORS AND DEFECTS
00039  * AND USER ACKNOWLEDGES THAT THE SOFTWARE MAY CONTAIN ERRORS AND DEFECTS.
00040  * HP DISCLAIMS ALL WARRANTIES WITH REGARD TO THE SOFTWARE, INCLUDING ALL
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00047  ***************************************************************************/
00048 
00049 #ifndef BASIC_COMPONENTS_H_
00050 #define BASIC_COMPONENTS_H_
00051 
00052 #include "XML_Parse.h"
00053 #include "area.h"
00054 #include "decoder.h"
00055 #include "parameter.h"
00056 //#include "io.h"
00057 #include "array.h"
00058 #include "wires.h"
00059 #include "arbiter.h"
00060 //#include "Undifferentiated_Core_Area.h"
00061 #include <vector>
00062 
00063 
00064 
00065 typedef struct{
00066   Cache gpredictor, lpredictor, chooser, ras;
00067   final_results result_gpredictor, result_lpredictor, result_chooser, result_ras;
00068   int predictor_accesses, ras_accesses;
00069   powerDef tot_power, max_power;
00070   double area, maxPower, runtimeDynamicPower, totalLeakage, totalPower;
00071 } predictor_core;
00072 
00073 typedef struct{
00074   //params
00075   Cache tlb;
00076   final_results result_tlb;
00077   //stats
00078   int total_accesses;
00079   int read_accesses;
00080   int write_accesses;
00081   int write_hits;
00082   int read_hits;
00083   int read_misses;
00084   int write_misses;
00085   int total_hits;
00086   int total_misses;
00087   powerDef tot_power, max_power;
00088   double area, maxPower, runtimeDynamicPower;
00089 } tlb_core;
00090 
00091 typedef struct{
00092   //params
00093   Cache caches, missb, ifb, prefetchb, wbb;
00094   final_results result_caches, result_missb, result_ifb, result_prefetchb, result_wbb;
00095   //stats
00096   int total_accesses;
00097   int read_accesses;
00098   int write_accesses;
00099   int total_hits;
00100   int total_misses;
00101   int read_hits;
00102   int write_hits;
00103   int read_misses;
00104   int write_misses;
00105   int replacements;
00106   int write_backs;
00107   int miss_buffer_access;
00108   int fill_buffer_accesses;
00109   int prefetch_buffer_accesses;
00110   int prefetch_buffer_writes;
00111   int prefetch_buffer_reads;
00112   int prefetch_buffer_hits;
00113   int wbb_writes;
00114   int wbb_reads;
00115   powerDef tot_power, max_power;
00116   double area, maxPower, runtimeDynamicPower;
00117 } cache_processor;
00118 
00119 typedef struct{
00120   //params
00121   Cache btb;
00122   final_results result_btb;
00123   //stats
00124   int total_accesses;
00125   int read_accesses;
00126   int write_accesses;
00127   int total_hits;
00128   int total_misses;
00129   int read_hits;
00130   int write_hits;
00131   int read_misses;
00132   int write_misses;
00133   int replacements;
00134   powerDef tot_power, max_power;
00135   double area, maxPower, runtimeDynamicPower, totalLeakage, totalPower;;
00136 } BTB_core;
00137 
00138 typedef struct{
00139   //params
00140   Cache rat;
00141   final_results result_rat;
00142   //stats
00143   int total_accesses;
00144   int read_accesses;
00145   int write_accesses;
00146   powerDef tot_power, max_power;
00147   double area, maxPower, runtimeDynamicPower, totalLeakage, totalPower;
00148 } RAT_core;
00149 
00150 typedef struct{
00151   //params
00152   Cache RF;
00153   final_results result_RF;
00154   //stats
00155   int total_accesses;
00156   int read_accesses;
00157   int write_accesses;
00158   powerDef tot_power, max_power;
00159   double area, maxPower, runtimeDynamicPower;
00160 } RF_core;
00161 
00162 typedef struct{
00163   //params
00164   Cache ROB;
00165   final_results result_ROB;
00166   //stats
00167   int total_accesses;
00168   int read_accesses;
00169   int write_accesses;
00170   powerDef tot_power, max_power;
00171   double area, maxPower, runtimeDynamicPower, totalLeakage, totalPower;
00172 } ROB_core;
00173 
00174 typedef struct{
00175   //params
00176   Cache IB;
00177   final_results result_IB;
00178   //stats
00179   int total_accesses;
00180   int read_accesses;
00181   int write_accesses;
00182   powerDef tot_power, max_power;
00183   double area, maxPower, runtimeDynamicPower;
00184 } IB_core;
00185 
00186 typedef struct{//reservation station or instruction issue queue
00187   //params
00188   Cache RS;
00189   final_results result_RS;
00190   //stats
00191   int total_accesses;
00192   int read_accesses;
00193   int write_accesses;
00194   powerDef tot_power, max_power;
00195   double area, maxPower, runtimeDynamicPower;
00196 } RS_core;
00197 
00198 typedef struct{
00199   //params
00200   Cache LSQ;
00201   final_results result_LSQ;
00202   //stats
00203   int total_accesses;
00204   int read_accesses;
00205   int write_accesses;
00206   powerDef tot_power, max_power;
00207   double area,maxPower, runtimeDynamicPower;
00208 } LSQ_core;
00209 
00210 typedef struct{
00211   //params
00212   wire wires;
00213   final_results result_wire;
00214   //stats
00215   int total_accesses;
00216   powerDef tot_power, max_power;
00217   double area,maxPower, runtimeDynamicPower;
00218 } resultbus;
00219 
00220 #endif /* BASIC_COMPONENTS_H_ */

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