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sst/core/techModels/libMcPATbeta/const.h

00001 /*------------------------------------------------------------
00002  *                              CACTI 6.5
00003  *         Copyright 2008 Hewlett-Packard Development Corporation
00004  *                         All Rights Reserved
00005  *
00006  * Permission to use, copy, and modify this software and its documentation is
00007  * hereby granted only under the following terms and conditions.  Both the
00008  * above copyright notice and this permission notice must appear in all copies
00009  * of the software, derivative works or modified versions, and any portions
00010  * thereof, and both notices must appear in supporting documentation.
00011  *
00012  * Users of this software agree to the terms and conditions set forth herein, and
00013  * hereby grant back to Hewlett-Packard Company and its affiliated companies ("HP")
00014  * a non-exclusive, unrestricted, royalty-free right and license under any changes,
00015  * enhancements or extensions  made to the core functions of the software, including
00016  * but not limited to those affording compatibility with other hardware or software
00017  * environments, but excluding applications which incorporate this software.
00018  * Users further agree to use their best efforts to return to HP any such changes,
00019  * enhancements or extensions that they make and inform HP of noteworthy uses of
00020  * this software.  Correspondence should be provided to HP at:
00021  *
00022  *                       Director of Intellectual Property Licensing
00023  *                       Office of Strategy and Technology
00024  *                       Hewlett-Packard Company
00025  *                       1501 Page Mill Road
00026  *                       Palo Alto, California  94304
00027  *
00028  * This software may be distributed (but not offered for sale or transferred
00029  * for compensation) to third parties, provided such third parties agree to
00030  * abide by the terms and conditions of this notice.
00031  *
00032  * THE SOFTWARE IS PROVIDED "AS IS" AND HP DISCLAIMS ALL
00033  * WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
00034  * OF MERCHANTABILITY AND FITNESS.   IN NO EVENT SHALL HP
00035  * CORPORATION BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
00036  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
00037  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS
00038  * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
00039  * SOFTWARE.
00040  *------------------------------------------------------------*/
00041 
00042 #ifndef __CONST_H__
00043 #define __CONST_H__
00044 
00045 #include <stdint.h>
00046 #include <stdlib.h>
00047 #include <string.h>
00048 #include <stdio.h>
00049 #include <math.h>
00050 
00051 /*  The following are things you might want to change
00052  *  when compiling
00053  */
00054 
00055 /*
00056  * Address bits in a word, and number of output bits from the cache
00057  */
00058 
00059 /*
00060 was: #define ADDRESS_BITS 32
00061 now: I'm using 42 bits as in the Power4,
00062 since that's bigger then the 36 bits on the Pentium 4
00063 and 40 bits on the Opteron
00064 */
00065 const int ADDRESS_BITS = 42;
00066 
00067 /*dt: In addition to the tag bits, the tags also include 1 valid bit, 1 dirty bit, 2 bits for a 4-state
00068   cache coherency protocoll (MESI), 1 bit for MRU (change this to log(ways) for full LRU).
00069   So in total we have 1 + 1 + 2 + 1 = 5 */
00070 const int EXTRA_TAG_BITS = 5;
00071 
00072 /* limits on the various N parameters */
00073 
00074 const unsigned int MAXDATAN     = 512;      // maximum for Ndwl and Ndbl
00075 const unsigned int MAXSUBARRAYS = 1048576;  // maximum subarrays for data and tag arrays
00076 const unsigned int MAXDATASPD   = 256;      // maximum for Nspd
00077 const unsigned int MAX_COL_MUX  = 256;
00078 
00079 
00080 
00081 #define ROUTER_TYPES 3
00082 #define WIRE_TYPES 6
00083 
00084 const double Cpolywire = 0;
00085 
00086 
00087 /* Threshold voltages (as a proportion of Vdd)
00088    If you don't know them, set all values to 0.5 */
00089 #define VTHFA1         0.452
00090 #define VTHFA2         0.304
00091 #define VTHFA3         0.420
00092 #define VTHFA4         0.413
00093 #define VTHFA5         0.405
00094 #define VTHFA6         0.452
00095 #define VSINV          0.452
00096 #define VTHCOMPINV     0.437
00097 #define VTHMUXNAND     0.548  // TODO : this constant must be revisited
00098 #define VTHEVALINV     0.452
00099 #define VTHSENSEEXTDRV 0.438
00100 
00101 
00102 //WmuxdrvNANDn and WmuxdrvNANDp are no longer being used but it's part of the old
00103 //delay_comparator function which we are using exactly as it used to be, so just setting these to 0
00104 const double WmuxdrvNANDn = 0;
00105 const double WmuxdrvNANDp = 0;
00106 
00107 
00108 /*===================================================================*/
00109 /*
00110  * The following are things you probably wouldn't want to change.
00111  */
00112 #ifndef BIGNUM
00113 #define BIGNUM 1e30
00114 #endif
00115 #define INF 9999999
00116 #ifndef MAX
00117 #define MAX(a,b) (((a)>(b))?(a):(b))
00118 #endif
00119 #ifndef MIN
00120 #define MIN(a,b) (((a)<(b))?(a):(b))
00121 #endif
00122 
00123 /* Used to communicate with the horowitz model */
00124 #define RISE 1
00125 #define FALL 0
00126 #define NCH  1
00127 #define PCH  0
00128 
00129 
00130 #define EPSILON 0.5 //v4.1: This constant is being used in order to fix floating point -> integer
00131 //conversion problems that were occuring within CACTI. Typical problem that was occuring was
00132 //that with different compilers a floating point number like 3.0 would get represented as either
00133 //2.9999....or 3.00000001 and then the integer part of the floating point number (3.0) would
00134 //be computed differently depending on the compiler. What we are doing now is to replace
00135 //int (x) with (int) (x+EPSILON) where EPSILON is 0.5. This would fix such problems. Note that
00136 //this works only when x is an integer >= 0.
00137 /*
00138  * Sheng thinks this is more a solution to solve the simple truncate problem
00139  * (http://www.cs.tut.fi/~jkorpela/round.html) rather than the problem mentioned above.
00140  * Unfortunately, this solution causes nasty bugs (different results when using O0 and O3).
00141  * Moreover, round is not correct in CACTI since when an extra fraction of bit/line is needed,
00142  * we need to provide a complete bit/line even the fraction is just 0.01.
00143  * So, in later version than 6.5 we use (int)ceil() to get double to int conversion.
00144  */
00145 
00146 #define EPSILON2 0.1
00147 #define EPSILON3 0.6
00148 
00149 
00150 #define MINSUBARRAYROWS 16 //For simplicity in modeling, for the row decoding structure, we assume
00151 //that each row predecode block is composed of at least one 2-4 decoder. When the outputs from the
00152 //row predecode blocks are combined this means that there are at least 4*4=16 row decode outputs
00153 #define MAXSUBARRAYROWS 262144 //Each row predecode block produces a max of 2^9 outputs. So
00154 //the maximum number of row decode outputs will be 2^9*2^9
00155 #define MINSUBARRAYCOLS 2
00156 #define MAXSUBARRAYCOLS 262144
00157 
00158 
00159 #define INV 0
00160 #define NOR 1
00161 #define NAND 2
00162 
00163 
00164 #define NUMBER_TECH_FLAVORS 4
00165 
00166 #define NUMBER_INTERCONNECT_PROJECTION_TYPES 2 //aggressive and conservative
00167 //0 = Aggressive projections, 1 = Conservative projections
00168 #define NUMBER_WIRE_TYPES 4 //local, semi-global and global
00169 //1 = 'Semi-global' wire type, 2 = 'Global' wire type
00170 
00171 
00172 const int dram_cell_tech_flavor = 3;
00173 
00174 
00175 #define VBITSENSEMIN 0.08 //minimum bitline sense voltage is fixed to be 80 mV.
00176 
00177 #define fopt 4.0
00178 
00179 #define INPUT_WIRE_TO_INPUT_GATE_CAP_RATIO 0
00180 #define BUFFER_SEPARATION_LENGTH_MULTIPLIER 1
00181 #define NUMBER_MATS_PER_REDUNDANT_MAT 8
00182 
00183 #define NUMBER_STACKED_DIE_LAYERS 1
00184 
00185 // this variable can be set to carry out solution optimization for
00186 // a maximum area allocation.
00187 #define STACKED_DIE_LAYER_ALLOTED_AREA_mm2 0 //6.24 //6.21//71.5
00188 
00189 // this variable can also be employed when solution optimization
00190 // with maximum area allocation is carried out.
00191 #define MAX_PERCENT_AWAY_FROM_ALLOTED_AREA 50
00192 
00193 // this variable can also be employed when solution optimization
00194 // with maximum area allocation is carried out.
00195 #define MIN_AREA_EFFICIENCY 20
00196 
00197 // this variable can be employed when solution with a desired
00198 // aspect ratio is required.
00199 #define STACKED_DIE_LAYER_ASPECT_RATIO 1
00200 
00201 // this variable can be employed when solution with a desired
00202 // aspect ratio is required.
00203 #define MAX_PERCENT_AWAY_FROM_ASPECT_RATIO 101
00204 
00205 // this variable can be employed to carry out solution optimization
00206 // for a certain target random cycle time.
00207 #define TARGET_CYCLE_TIME_ns 1000000000
00208 
00209 #define NUMBER_PIPELINE_STAGES 4
00210 
00211 // this can be used to model the length of interconnect
00212 // between a bank and a crossbar
00213 #define LENGTH_INTERCONNECT_FROM_BANK_TO_CROSSBAR 0 //3791 // 2880//micron
00214 
00215 #define IS_CROSSBAR 0
00216 #define NUMBER_INPUT_PORTS_CROSSBAR 8
00217 #define NUMBER_OUTPUT_PORTS_CROSSBAR 8
00218 #define NUMBER_SIGNALS_PER_PORT_CROSSBAR 256
00219 
00220 
00221 #define MAT_LEAKAGE_REDUCTION_DUE_TO_SLEEP_TRANSISTORS_FACTOR 1
00222 #define LEAKAGE_REDUCTION_DUE_TO_LONG_CHANNEL_HP_TRANSISTORS_FACTOR 1
00223 
00224 #define PAGE_MODE 0
00225 
00226 #define MAIN_MEM_PER_CHIP_STANDBY_CURRENT_mA 60
00227 // We are actually not using this variable in the CACTI code. We just want to acknowledge that
00228 // this current should be multiplied by the DDR(n) system VDD value to compute the standby power
00229 // consumed during precharge.
00230 
00231 
00232 const double VDD_STORAGE_LOSS_FRACTION_WORST = 0.125;
00233 const double CU_RESISTIVITY = 0.022; //ohm-micron
00234 const double BULK_CU_RESISTIVITY = 0.018; //ohm-micron
00235 const double PERMITTIVITY_FREE_SPACE = 8.854e-18; //F/micron
00236 
00237 const static uint32_t sram_num_cells_wl_stitching_ = 16;
00238 const static uint32_t dram_num_cells_wl_stitching_ = 64;
00239 const static uint32_t comm_dram_num_cells_wl_stitching_ = 256;
00240 const static double num_bits_per_ecc_b_          = 8.0;
00241 
00242 const double    bit_to_byte  = 8.0;
00243 
00244 #define MAX_NUMBER_GATES_STAGE 20
00245 #define MAX_NUMBER_HTREE_NODES 20
00246 #define NAND2_LEAK_STACK_FACTOR 0.2
00247 #define NAND3_LEAK_STACK_FACTOR 0.2
00248 #define NOR2_LEAK_STACK_FACTOR 0.2
00249 #define INV_LEAK_STACK_FACTOR  0.5
00250 #define MAX_NUMBER_ARRAY_PARTITIONS 1000000
00251 
00252 // abbreviations used in this project
00253 // ----------------------------------
00254 //
00255 //  num  : number
00256 //  rw   : read/write
00257 //  rd   : read
00258 //  wr   : write
00259 //  se   : single-ended
00260 //  sz   : size
00261 //  F    : feature
00262 //  w    : width
00263 //  h    : height or horizontal
00264 //  v    : vertical or velocity
00265 
00266 
00267 enum ram_cell_tech_type_num
00268 {
00269   itrs_hp   = 0,
00270   itrs_lstp = 1,
00271   itrs_lop  = 2,
00272   lp_dram   = 3,
00273   comm_dram = 4
00274 };
00275 
00276 const double pppm[4]      = {1,1,1,1};
00277 const double pppm_lkg[4]  = {0,1,1,0};
00278 const double pppm_dyn[4]  = {1,0,0,0};
00279 const double pppm_Isub[4] = {0,1,0,0};
00280 const double pppm_Ig[4]   = {0,0,1,0};
00281 const double pppm_sc[4]   = {0,0,0,1};
00282 
00283 
00284 
00285 #endif

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