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sst/elements/power/power.h

00001 // Copyright 2009-2010 Sandia Corporation. Under the terms
00002 // of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
00003 // Government retains certain rights in this software.
00004 // 
00005 // Copyright (c) 2009-2010, Sandia Corporation
00006 // All rights reserved.
00007 // 
00008 // This file is part of the SST software package. For license
00009 // information, see the LICENSE file in the top level directory of the
00010 // distribution.
00011 
00012 #ifndef _SST_POWER_H
00013 #define _SST_POWER_H
00014 
00015 
00016 #include "interface.h"
00017 #include "HotSpot-interface.h"
00018 #include "IntSim-interface.h"
00019 
00020 
00021 /*********Sim-Panalyzer************/
00022 //#define PANALYZER_H
00023 ////#define LV1_PANALYZER_H
00024 //#define LV2_PANALYZER_H
00025 
00026 /* added for sim-panalyzer power analysis */
00027 extern "C"{
00028 #ifdef PANALYZER_H
00029 
00030 #ifdef LV1_PANALYZER_H
00031 #include "../sst/core/techModels/libsim-panalyzer/lv1_opts.h"
00032 #include "../sst/core/techModels/libsim-panalyzer/lv1_panalyzer.h"
00033 #include "../sst/core/techModels/libsim-panalyzer/lv1_cache_panalyzer.h"
00034 #include "../sst/core/techModels/libsim-panalyzer/io_panalyzer.h"
00035 #endif
00036 
00037 #ifdef LV2_PANALYZER_H
00038 #include "../sst/core/techModels/libsim-panalyzer/technology.h"
00039 #include "../sst/core/techModels/libsim-panalyzer/alu_panalyzer.h"
00040 #include "../sst/core/techModels/libsim-panalyzer/mult_panalyzer.h"
00041 #include "../sst/core/techModels/libsim-panalyzer/fpu_panalyzer.h"
00042 #include "../sst/core/techModels/libsim-panalyzer/uarch_panalyzer.h"
00043 #endif //lv2_panalyzer_h
00044 
00045 #endif //panalyzer_h
00046 }
00047 
00048 
00049 /***********McPAT05****************/
00050 //#define McPAT05_H
00051 
00052 /*added for McPAT05 power analysis */
00053 #ifdef McPAT05_H
00054 #include "../sst/core/techModels/libMcPAT/io.h"
00055 #include "../sst/core/techModels/libMcPAT/logic.h"
00056 #include "../sst/core/techModels/libMcPAT/full_decoder.h"
00057 #include "../sst/core/techModels/libMcPAT/crossbarswitch.h"
00058 #include "../sst/core/techModels/libMcPAT/basic_circuit.h"
00059 #include "../sst/core/techModels/libMcPAT/processor.h"
00060 #endif //mcpat05_h
00061 
00062 
00063 /***********McPAT06****************/
00064 //#define McPAT06_H
00065 
00066 /*added for McPAT06 power analysis */
00067 #ifdef McPAT06_H
00068 #include "../sst/core/techModels/libMcPATbeta06/io.h"
00069 #include "../sst/core/techModels/libMcPATbeta06/logic.h"
00070 #include "../sst/core/techModels/libMcPATbeta06/basic_circuit.h"
00071 #include "../sst/core/techModels/libMcPATbeta06/processor.h"
00072 #endif //mcpat06_h
00073 
00074 /***********McPAT07****************/
00075 #define McPAT07_H
00076 
00077 /*added for McPAT07 power analysis */
00078 #ifdef McPAT07_H
00079 #include "../sst/core/techModels/libMcPATbeta/io.h"
00080 #include "../sst/core/techModels/libMcPATbeta/logic.h"
00081 #include "../sst/core/techModels/libMcPATbeta/basic_circuit.h"
00082 #include "../sst/core/techModels/libMcPATbeta/processor.h"
00083 #endif //mcpat07_h
00084 
00085 /*********ORION******************/
00086 #define ORION_H
00087 
00088 /*added for ORION power analysis */
00089 extern "C"{
00090 #ifdef ORION_H
00091 #include "../sst/core/techModels/libORION/SIM_parameter.h"
00092 #include "../sst/core/techModels/libORION/SIM_router.h"
00093 #include "../sst/core/techModels/libORION/SIM_link.h"
00094 #endif //orion_h
00095 }
00096 
00097 
00098 
00099 #define MAX_NUM_SUBCOMP 20
00100 
00101 
00102 namespace SST {
00103 
00104         typedef int nm;
00105         typedef int ns;
00106 
00107         enum logic_style {STATIC, DYNAMIC};
00108         enum clock_style{NORM_H, BALANCED_H};
00109         enum io_style{IN, OUT, BI};
00110         enum topology_style{TWODMESH, RING, CROSSBAR}; 
00111 
00112         //TODO consider to add "ALL" to ptype, so users don't have to list/decouple power params one by one.
00113         enum ptype {CACHE_IL1, CACHE_IL2, CACHE_DL1, CACHE_DL2, CACHE_ITLB, CACHE_DTLB, CLOCK, BPRED, RF, IO, LOGIC, EXEU_ALU, EXEU_FPU, MULT, IB, ISSUE_Q, INST_DECODER, BYPASS, EXEU, PIPELINE, LSQ, RAT, ROB, BTB, CACHE_L2, MEM_CTRL, ROUTER, LOAD_Q, RENAME_U, SCHEDULER_U, CACHE_L3, CACHE_L1DIR, CACHE_L2DIR, UARCH}; //RS is renamed by ISSUE_Q because of name collision       in s-p
00114         enum pmodel{McPAT, SimPanalyzer, McPAT05, IntSim, ORION}; //McPAT05 is an older version
00115         enum tmodel {HOTSPOT};
00116         enum tlayer{SILICON, INTERFACE, SPREADER, HEATSINK, NUM_THERMAL_LAYERS};
00117         
00118 
00119 typedef struct 
00120 {
00121         watts il1_read, il1_write;
00122         watts il2_read, il2_write;
00123         watts dl1_read, dl1_write;
00124         watts dl2_read, dl2_write;
00125         watts itlb_read, itlb_write;
00126         watts dtlb_read, dtlb_write;
00127         watts aio, dio;
00128         watts clock;
00129         watts logic;
00130         watts rf, bpred;
00131         watts alu, fpu, mult, exeu;
00132         watts ib, issueQ, decoder, bypass, pipeline, lsq;
00133         watts rat, rob, btb, l2, mc, router, loadQ, rename, scheduler, l3, l1dir, l2dir;
00134         watts uarch;
00135 }Punit_t;
00136 
00137 typedef struct  //this takes over the core params in each subcomponent_params_t
00138 {
00139         unsigned core_physical_address_width, core_temperature, core_tech_node;
00140         unsigned core_virtual_address_width, core_virtual_memory_page_size, core_number_hardware_threads;               
00141         unsigned machine_bits, archi_Regs_IRF_size, archi_Regs_FRF_size, core_phy_Regs_IRF_size, core_phy_Regs_FRF_size;
00142         unsigned core_register_windows_size, core_opcode_width; 
00143         unsigned core_instruction_window_size;
00144         unsigned core_issue_width, core_decode_width, core_fetch_width, core_commit_width;      
00145         unsigned core_instruction_length;
00146         unsigned core_instruction_buffer_size;
00147         unsigned ALU_per_core, FPU_per_core, MUL_per_core;      
00148         unsigned core_store_buffer_size, core_memory_ports;
00149         unsigned core_int_pipeline_depth, core_RAS_size, core_ROB_size, core_load_buffer_size, core_number_of_NoCs;
00150         unsigned core_number_instruction_fetch_ports, core_fp_issue_width, core_fp_instruction_window_size, core_peak_issue_width, core_micro_opcode_width;     
00151         unsigned core_long_channel;
00152 } core_params_t;
00153 
00154 typedef struct
00155 {
00156         std::vector<farads> unit_scap;   //switching
00157         //farads unit_scap;  
00158         farads unit_icap;  //internal
00159         farads unit_lcap;  //leakage
00160         farads unit_ecap;  //effective capacitance-for lv1
00161         volts vss;
00162         double op_freq;
00163         unsigned core_physical_address_width;
00164         unsigned core_virtual_address_width, core_virtual_memory_page_size, core_number_hardware_threads;
00165         unsigned core_temperature, core_tech_node;  
00166 
00167         //for cache components
00168         int num_sets;
00169         std::vector<int> line_size;
00170         int num_bitlines;
00171         int num_wordlines;
00172         std::vector<int> assoc;
00173         unsigned num_rwports, num_rports, num_wports;
00174         std::vector<unsigned> num_banks;
00175         std::vector<double> throughput;
00176         std::vector<double> latency;
00177         std::vector<unsigned> miss_buf_size, fill_buf_size, prefetch_buf_size, wbb_buf_size;
00178         unsigned number_entries;
00179         unsigned device_type, directory_type;
00180         double area, num_transistors;
00181 } cache_params_t;
00182 
00183 
00184 
00185 struct clock_params_t
00186 {
00187         farads unit_scap;  //switching
00188         farads unit_icap;  //internal
00189         farads unit_lcap;   //leakage
00190         farads unit_ecap;  //effective capacitance-for lv1
00191         volts vss;
00192         double op_freq;
00193         unsigned core_temperature, core_tech_node;      
00194 
00195         //for clock components
00196         clock_style clk_style;
00197         double skew;
00198         nm chip_area;
00199         farads node_cap;
00200         int opt_clock_buffer_num;
00201         double area, num_transistors;
00202         clock_option_type_t clock_option;
00203 };
00204 
00205 struct bpred_params_t
00206 {
00207         farads unit_icap; //internal
00208         farads unit_ecap;  //effective capacitance-for lv1
00209         farads unit_scap;  //switching
00210         volts vss;
00211         double op_freq;
00212 
00213         unsigned global_predictor_bits, global_predictor_entries, prediction_width, local_predictor_size, local_predictor_entries;
00214         unsigned chooser_predictor_bits, chooser_predictor_entries;
00215         unsigned nrows, ncols;
00216         unsigned num_rwports, num_rports, num_wports;   
00217         unsigned long bpred_access;
00218         double area, num_transistors;
00219 };
00220 
00221 struct rf_params_t
00222 {
00223         farads unit_icap; //internal
00224         farads unit_ecap;  //effective capacitance-for lv1
00225         farads unit_scap;  //switching
00226         volts vss;
00227         unsigned machine_bits, archi_Regs_IRF_size, archi_Regs_FRF_size;
00228         unsigned core_issue_width, core_register_windows_size, core_number_hardware_threads, core_opcode_width, core_virtual_address_width;
00229         unsigned core_temperature, core_tech_node;
00230 
00231         double op_freq;
00232         unsigned nrows, ncols;
00233         unsigned num_rwports, num_rports, num_wports;   
00234         unsigned long rf_access;
00235         double area, num_transistors;
00236 };
00237 
00238 struct io_params_t
00239 {
00240         farads unit_scap;      //switching
00241         farads unit_icap;  //internal
00242         farads unit_lcap;   //leakage
00243         farads unit_ecap;  //effective capacitance-for lv1
00244         volts vss;
00245         double op_freq;
00246         
00247         //for I/O components
00248         io_style i_o_style;
00249         unsigned opt_io_buffer_num;
00250         double ustrip_len;
00251         unsigned bus_width;   //bus width
00252         unsigned bus_size;    //io transaction size = buffer size = bsize in io_panalyzer
00253         unsigned io_access_time;  //in cycles
00254         unsigned io_cycle_time;  // in cycles
00255         double area, num_transistors;
00256 };
00257 
00258 struct logic_params_t
00259 {
00260         farads unit_scap;      //switching
00261         farads unit_icap;  //internal
00262         farads unit_lcap;   //leakage
00263         farads unit_ecap;  //effective capacitance-for lv1
00264         volts vss;
00265         double op_freq;
00266         unsigned core_instruction_window_size, core_issue_width, core_number_hardware_threads;
00267         unsigned core_decode_width, archi_Regs_IRF_size, archi_Regs_FRF_size;
00268         unsigned core_temperature, core_tech_node;
00269 
00270         //for logic components
00271         logic_style lgc_style; //Dynamic/Static Logic   
00272         unsigned num_gates;
00273         unsigned num_functions;   // Does this mean and, or, xor??
00274         unsigned num_fan_in;
00275         unsigned num_fan_out;
00276         double area, num_transistors;
00277 };
00278 
00279 struct other_params_t
00280 {
00281         farads unit_scap;      //switching
00282         farads unit_icap;  //internal
00283         farads unit_lcap;   //leakage
00284         farads unit_ecap;  //effective capacitance-for lv1
00285         volts vss;
00286         double op_freq;
00287         double area, num_transistors;
00288 };
00289 
00290 
00291 struct ib_params_t
00292 {
00293         unsigned core_instruction_length, core_issue_width, core_number_hardware_threads;
00294         unsigned core_instruction_buffer_size, num_rwports;
00295         unsigned core_temperature, core_tech_node, core_virtual_address_width, core_virtual_memory_page_size;
00296         double area, num_transistors;
00297 };
00298 
00299 struct irs_params_t
00300 {
00301         unsigned core_number_hardware_threads, core_instruction_length, core_instruction_window_size;
00302         unsigned core_issue_width;
00303         unsigned core_temperature, core_tech_node;
00304         double area, num_transistors;
00305 };
00306 
00307 struct decoder_params_t
00308 {
00309         unsigned core_opcode_width;
00310         unsigned core_temperature, core_tech_node;
00311         double area, num_transistors;
00312 };
00313 
00314 struct bypass_params_t
00315 {
00316         unsigned core_number_hardware_threads, ALU_per_core, machine_bits, FPU_per_core;
00317         unsigned core_opcode_width, core_virtual_address_width;
00318         unsigned core_store_buffer_size, core_memory_ports;
00319         unsigned core_temperature, core_tech_node;
00320         double area, num_transistors;
00321 };
00322 
00323 struct pipeline_params_t
00324 {
00325         unsigned core_number_hardware_threads, core_fetch_width, core_decode_width;
00326         unsigned core_issue_width, core_commit_width, core_instruction_length, core_virtual_address_width;
00327         unsigned core_opcode_width, core_int_pipeline_depth;
00328         unsigned machine_bits, archi_Regs_IRF_size;
00329         unsigned core_temperature, core_tech_node;
00330         double area, num_transistors;
00331 };
00332 
00333 typedef struct
00334 {
00335         farads unit_scap;  //switching
00336         volts vss;
00337         double op_freq;
00338 
00339         //for btb components
00340         
00341         int line_size, assoc;
00342         unsigned num_banks;
00343         double throughput, latency;
00344         double area, num_transistors;
00345 } btb_params_t;
00346 
00347 typedef struct
00348 {
00349         double mc_clock;
00350         unsigned llc_line_length, databus_width, addressbus_width, req_window_size_per_channel;
00351         unsigned memory_channels_per_mc, IO_buffer_size_per_channel;
00352         unsigned memory_number_ranks, memory_peak_transfer_rate;
00353         double area, num_transistors;
00354 } mc_params_t;
00355 
00356 typedef struct
00357 {
00358         double clockrate, vdd;
00359         unsigned has_global_link, flit_bits, input_buffer_entries_per_vc, virtual_channel_per_port, input_ports;
00360         unsigned output_ports, link_throughput, link_latency, horizontal_nodes, vertical_nodes;
00361         topology_style topology;
00362         double area, num_transistors;
00363         double link_length;
00364 } router_params_t;
00365 
00366 
00367 typedef struct
00368 {
00369         /*McPAT*/
00370         double branch_read, branch_write, RAS_read, RAS_write;
00371         double il1_read[MAX_NUM_SUBCOMP], il1_readmiss[MAX_NUM_SUBCOMP], IB_read[MAX_NUM_SUBCOMP], IB_write[MAX_NUM_SUBCOMP], BTB_read[MAX_NUM_SUBCOMP], BTB_write[MAX_NUM_SUBCOMP], ID_inst_read[MAX_NUM_SUBCOMP], ID_operand_read[MAX_NUM_SUBCOMP], ID_misc_read[MAX_NUM_SUBCOMP];
00372         double int_win_read, int_win_write, int_win_search, fp_win_read, fp_win_write, fp_win_search, ROB_read, ROB_write;
00373         double iFRAT_read, iFRAT_write, iFRAT_search, fFRAT_read, fFRAT_write, fFRAT_search, iRRAT_read, fRRAT_read, iRRAT_write, fRRAT_write;
00374         double ifreeL_read, ifreeL_write, ffreeL_read, ffreeL_write, idcl_read, fdcl_read;
00375         double dl1_read[MAX_NUM_SUBCOMP], dl1_readmiss[MAX_NUM_SUBCOMP], dl1_write[MAX_NUM_SUBCOMP], dl1_writemiss[MAX_NUM_SUBCOMP], LSQ_read[MAX_NUM_SUBCOMP], LSQ_write[MAX_NUM_SUBCOMP], loadQ_read[MAX_NUM_SUBCOMP], loadQ_write[MAX_NUM_SUBCOMP];
00376         double itlb_read[MAX_NUM_SUBCOMP], itlb_readmiss[MAX_NUM_SUBCOMP], dtlb_read[MAX_NUM_SUBCOMP], dtlb_readmiss[MAX_NUM_SUBCOMP];
00377         double int_regfile_reads, int_regfile_writes, float_regfile_reads, float_regfile_writes, RFWIN_read, RFWIN_write;
00378         double bypass_access;
00379         double router_access;
00380         double L2_read[MAX_NUM_SUBCOMP], L2_readmiss[MAX_NUM_SUBCOMP], L2_write[MAX_NUM_SUBCOMP], L2_writemiss[MAX_NUM_SUBCOMP], L3_read[MAX_NUM_SUBCOMP], L3_readmiss[MAX_NUM_SUBCOMP], L3_write[MAX_NUM_SUBCOMP], L3_writemiss[MAX_NUM_SUBCOMP];
00381         double L1Dir_read[MAX_NUM_SUBCOMP], L1Dir_readmiss[MAX_NUM_SUBCOMP], L1Dir_write[MAX_NUM_SUBCOMP], L1Dir_writemiss[MAX_NUM_SUBCOMP], L2Dir_read[MAX_NUM_SUBCOMP], L2Dir_readmiss[MAX_NUM_SUBCOMP], L2Dir_write[MAX_NUM_SUBCOMP], L2Dir_writemiss[MAX_NUM_SUBCOMP];
00382         double memctrl_read, memctrl_write;
00383         /*S-P*/
00384         double il1_ReadorWrite,  il1_datablock,  il1_access;
00385         unsigned il1_accessaddress,il1_latency;
00386         double il2_ReadorWrite, il2_datablock, il2_access;
00387         unsigned il2_accessaddress, il2_latency;
00388         double dl1_ReadorWrite, dl1_datablock, dl1_access;
00389         unsigned dl1_accessaddress, dl1_latency;
00390         double dl2_ReadorWrite, dl2_datablock, dl2_access;
00391         unsigned dl2_accessaddress, dl2_latency;
00392         double itlb_ReadorWrite, itlb_datablock, itlb_access;
00393         unsigned itlb_accessaddress, itlb_latency;
00394         double dtlb_ReadorWrite, dtlb_datablock, dtlb_access;
00395         unsigned dtlb_accessaddress, dtlb_latency;
00396         double bpred_access, rf_access, alu_access, fpu_access, mult_access, exeu_access, logic_access, clock_access; 
00397         double io_ReadorWrite, io_datablock, io_access;
00398         unsigned io_accessaddress, io_latency;
00399         /*IntSim*/
00400         double ib_access, issueQ_access, decoder_access, pipeline_access, lsq_access;
00401         double rat_access, rob_access, btb_access, l2_access, mc_access;
00402         double loadQ_access, rename_access, scheduler_access, l3_access, l1dir_access, l2dir_access;
00403 } usagecounts_t;
00404 
00405 struct powerModel_t
00406 {
00407         pmodel il1, il2, dl1, dl2, itlb, dtlb;
00408         pmodel clock, bpred, rf, io, logic, alu, fpu, mult;
00409         pmodel ib, issueQ, decoder, bypass, exeu, pipeline;
00410         pmodel lsq, rat, rob, btb, L2, mc, router, loadQ;
00411         pmodel rename, scheduler, L3, L1dir, L2dir;
00412 
00413         powerModel_t() : il1(McPAT), il2(McPAT), dl1(McPAT), dl2(McPAT), itlb(McPAT), dtlb(McPAT),
00414         clock(McPAT), bpred(McPAT), rf(McPAT), io(McPAT), logic(McPAT), alu(McPAT), fpu(McPAT), mult(McPAT),
00415         ib(McPAT), issueQ(McPAT), decoder(McPAT), bypass(McPAT), exeu(McPAT), pipeline(McPAT),
00416         lsq(McPAT), rat(McPAT), rob(McPAT), btb(McPAT), L2(McPAT), mc(McPAT), router(McPAT), loadQ(McPAT),
00417         rename(McPAT), scheduler(McPAT), L3(McPAT), L1dir(McPAT), L2dir(McPAT) {}
00418 };
00419 
00420 struct device_params_t
00421 {
00422         unsigned number_il1, number_dl1, number_itlb, number_dtlb, number_L1dir, number_L2dir, number_L2, number_L3;
00423         unsigned machineType; //1: inorder, 0:ooo
00424         float clockRate; //frequency McPAT
00425 };
00426 
00427 struct floorplan_id_t
00428 {
00429         int il1, il2, dl1, dl2, itlb, dtlb;
00430         int clock, bpred, rf, io, logic, alu, fpu, mult;
00431         int ib, issueQ, decoder, bypass, exeu, pipeline;
00432         int lsq, rat, rob, btb, L2, mc, router, loadQ;
00433         int rename, scheduler, L3, L1dir, L2dir;
00434 };
00435 
00436 
00437 
00438 class Power{
00439    public:
00440         Pdissipation_t p_usage_cache_il1;
00441         Pdissipation_t p_usage_cache_il2;
00442         Pdissipation_t p_usage_cache_dl1;
00443         Pdissipation_t p_usage_cache_dl2;
00444         Pdissipation_t p_usage_cache_itlb;
00445         Pdissipation_t p_usage_cache_dtlb;
00446         Pdissipation_t p_usage_clock;
00447         Pdissipation_t p_usage_io;
00448         Pdissipation_t p_usage_logic;
00449         Pdissipation_t p_usage_alu;
00450         Pdissipation_t p_usage_fpu;
00451         Pdissipation_t p_usage_mult;    
00452         Pdissipation_t p_usage_rf;
00453         Pdissipation_t p_usage_bpred;
00454         Pdissipation_t p_usage_ib;
00455         Pdissipation_t p_usage_rs;
00456         Pdissipation_t p_usage_decoder;
00457         Pdissipation_t p_usage_bypass;
00458         Pdissipation_t p_usage_exeu;
00459         Pdissipation_t p_usage_pipeline;
00460         Pdissipation_t p_usage_lsq;
00461         Pdissipation_t p_usage_rat;
00462         Pdissipation_t p_usage_rob;
00463         Pdissipation_t p_usage_btb;
00464         std::vector<Pdissipation_t> p_usage_cache_l2;
00465         Pdissipation_t p_usage_mc;
00466         Pdissipation_t p_usage_router;
00467         Pdissipation_t p_usage_loadQ;
00468         Pdissipation_t p_usage_renameU;
00469         Pdissipation_t p_usage_schedulerU;
00470         std::vector<Pdissipation_t> p_usage_cache_l3;
00471         std::vector<Pdissipation_t> p_usage_cache_l1dir;
00472         std::vector<Pdissipation_t> p_usage_cache_l2dir;
00473         Pdissipation_t p_usage_uarch; //"ALL"
00474 
00475         device_params_t device_tech;
00476         cache_params_t cache_il1_tech;
00477         cache_params_t cache_il2_tech;
00478         cache_params_t cache_dl1_tech;
00479         cache_params_t cache_dl2_tech;
00480         cache_params_t cache_itlb_tech;
00481         cache_params_t cache_dtlb_tech;
00482         cache_params_t cache_l2_tech;
00483         cache_params_t cache_l3_tech;
00484         cache_params_t cache_l1dir_tech;
00485         cache_params_t cache_l2dir_tech;
00486         clock_params_t clock_tech;
00487         bpred_params_t bpred_tech;
00488         rf_params_t rf_tech;
00489         io_params_t io_tech;
00490         logic_params_t logic_tech;
00491         other_params_t alu_tech;
00492         other_params_t fpu_tech;
00493         other_params_t mult_tech;
00494         other_params_t uarch_tech;
00495         ib_params_t ib_tech;
00496         irs_params_t irs_tech;
00497         bypass_params_t bypass_tech;
00498         decoder_params_t decoder_tech;
00499         pipeline_params_t pipeline_tech;
00500         core_params_t core_tech;        
00501         btb_params_t btb_tech;
00502         mc_params_t mc_tech;
00503         router_params_t router_tech;
00504         floorplan_id_t floorplan_id;
00505 
00506         
00507         ComponentId_t p_compID;
00508         int p_powerLevel; //level 1: v, f, sC, iC, lC; level 2: v, f, sC, and other params
00509         bool p_powerMonitor; // if a component want to have power modeled
00510         bool p_tempMonitor; // if a component want to have temperature modeled
00511         powerModel_t p_powerModel;
00512         Punit_t p_unitPower; // stores unit power per sub-component access
00513         I p_meanPeak, p_meanPeakAll; // for manual error bar on mean peak power
00514         double p_areaMcPAT;
00515         char *p_McPATxmlpath;
00516         unsigned p_maxNumSubComp;  //max number of sub-comp of the same type
00517         bool p_ifReadEntireXML, p_ifGetMcPATUnitP;
00518         std::map<ptype,int> subcompList; //stores subcomp types and the floorplan they reside on
00519         
00520         // floorplan and thermal tiles parameters
00521         static parameters_chip_t chip;
00522         static chip_t p_chip; 
00523         static int p_NumCompNeedPower;
00524 
00525         // sim-panalyzer parameters
00526         #ifdef LV2_PANALYZER_H
00527         #ifdef CACHE_PANALYZER_H
00528         fu_cache_pspec_t *il1_pspec;
00529         fu_cache_pspec_t *il2_pspec;
00530         fu_cache_pspec_t *dl1_pspec;
00531         fu_cache_pspec_t *dl2_pspec;
00532         fu_cache_pspec_t *itlb_pspec;
00533         fu_cache_pspec_t *dtlb_pspec;
00534         #endif /* CACHE_PANALYZER_H */
00535         #ifdef CLOCK_PANALYZER_H
00536         fu_clock_pspec_t *clock_pspec;
00537         #endif /* CLOCK_PANALYZER_H */
00538         #ifdef MEMORY_PANALYZER_H
00539         fu_sbank_pspec_t *rf_pspec;
00540         fu_sbank_pspec_t *bpred_pspec;
00541         #endif /* MEMORY_PANALYZER_H */
00542         #ifdef LOGIC_PANALYZER_H 
00543         fu_logic_pspec_t *logic_pspec;
00544         #endif  /*LOGIC_PANALYZER_H*/   
00545         fu_alu_pspec_t *alu_pspec;
00546         fu_mult_pspec_t *mult_pspec;
00547         fu_fpu_pspec_t *fpu_pspec;
00548         #endif /*lv2_panalyzer*/
00549         
00550         #ifdef IO_PANALYZER_H
00551         /* address io panalyzer */
00552         fu_io_pspec_t *aio_pspec;
00553         /* data io panalyzer */
00554         fu_io_pspec_t *dio_pspec;
00555         #endif /* IO_PANALYZER_H */
00556 
00557         // McPAT05 parameters
00558         int perThreadState;
00559         double C_EXEU; //exeu capacitance
00560 
00561         #ifdef McPAT05_H
00562         #ifdef  XML_PARSE_H_
00563         ParseXML *p_Mp1;
00564         #endif /*  XML_PARSE_H_ */
00565         #ifdef  PROCESSOR_H_
00566         Processor p_Mproc;
00567         InputParameter interface_ip;
00568         #endif /* PROCESSOR_H_*/
00569         #ifdef  CORE_H_
00570         tlb_core itlb, dtlb;
00571         cache_processor icache, dcache;
00572         BTB_core BTB;
00573         RF_core  IRF, FRF, RFWIN, phyIRF, phyFRF;
00574         IB_core  IB;
00575         RS_core  iRS, iISQ,fRS, fISQ;
00576         LSQ_core LSQ, loadQ;
00577         resultbus int_bypass,intTagBypass, fp_bypass, fpTagBypass;
00578         selection_logic instruction_selection;
00579         dep_resource_conflict_check idcl,fdcl;
00580         full_decoder inst_decoder;
00581         core_pipeline corepipe;
00582         UndifferentiatedCore undifferentiatedCore;
00583         MCclock_network clockNetwork;
00584         ROB_core ROB;   
00585         predictor_core predictor;
00586         RAT_core iRRAT,iFRAT,iFRATCG, fRRAT,fFRAT,fFRATCG;
00587         #endif /* CORE_H_*/
00588         #ifdef  SHAREDCACHE_H_
00589         cache_processor llCache,directory;
00590         pipeline pipeLogicCache, pipeLogicDirectory;
00591         MCclock_network L2clockNetwork;
00592         #endif /*  SHAREDCACHE_H_*/
00593         #ifdef MEMORYCTRL_H_
00594         selection_logic MC_arb;
00595         cache_processor frontendBuffer,readBuffer, writeBuffer;
00596         pipeline MCpipeLogic;
00597         MCclock_network MCclockNetwork;
00598         MCBackend transecEngine;
00599         MCPHY     PHY;
00600         #endif /*MEMORYCTRL_H_*/
00601         #ifdef ROUTER_H_
00602         cache_processor inputBuffer, routingTable;
00603         crossbarswitch xbar;
00604         Arbiter vcAllocatorStage1,vcAllocatorStage2, switchAllocatorStage1, switchAllocatorStage2;
00605         wire globalInterconnect;
00606         pipeline RTpipeLogic;
00607         MCclock_network RTclockNetwork;
00608         #endif /*ROUTER_H_*/
00609         #endif /*McPAT05_H*/
00610 
00611 
00612         //McPAT06 parameters
00613         #ifdef McPAT06_H
00614         #ifdef  XML_PARSE_H_
00615         ParseXML *p_Mp1;
00616         #endif /*  XML_PARSE_H_ */
00617         #ifdef  PROCESSOR_H_
00618         Processor p_Mproc;
00619         Core *p_Mcore;
00620         SharedCache* l2array;
00621         SharedCache* l3array;
00622         SharedCache* l1dirarray;
00623         SharedCache* l2dirarray;
00624         NoC* nocs;
00625         MemoryController* mc;
00626         #endif /* PROCESSOR_H_*/
00627         #ifdef  CORE_H_
00628         InstFetchU * ifu;
00629         LoadStoreU * lsu;
00630         MemManU    * mmu;
00631         EXECU      * exu;
00632         RENAMINGU  * rnu;
00633         Pipeline   * corepipe;
00634         UndiffCore * undiffCore;
00635         CoreDynParam  coredynp;
00636         
00637         ArrayST * globalBPT;
00638         ArrayST * L1_localBPT;
00639         ArrayST * L2_localBPT;
00640         ArrayST * chooser;
00641         ArrayST * RAS;
00642         
00643         InstCache icache;
00644         ArrayST * IB;
00645         ArrayST * BTB;
00646         BranchPredictor * BPT;
00647 
00648         ArrayST         * int_inst_window;
00649         ArrayST         * fp_inst_window;
00650         ArrayST         * ROB;
00651         selection_logic * instruction_selection;
00652 
00653         ArrayST * iFRAT;
00654         ArrayST * fFRAT;
00655         ArrayST * iRRAT;
00656         ArrayST * fRRAT;
00657         ArrayST * ifreeL;
00658         ArrayST * ffreeL;
00659         dep_resource_conflict_check * idcl;
00660         dep_resource_conflict_check * fdcl;
00661 
00662         DataCache dcache;
00663         ArrayST * LSQ;//it is actually the store queue but for inorder processors it serves as both loadQ and StoreQ
00664         ArrayST * LoadQ;
00665 
00666         ArrayST * itlb;
00667         ArrayST * dtlb;
00668 
00669         ArrayST * IRF;
00670         ArrayST * FRF;
00671         ArrayST * RFWIN;
00672 
00673         RegFU          * rfu;
00674         SchedulerU     * scheu;
00675         FunctionalUnit * fp_u;
00676         FunctionalUnit * exeu;
00677         McPATComponent  bypass;
00678         interconnect * int_bypass;
00679         interconnect * intTagBypass;
00680         interconnect * fp_bypass;
00681         interconnect * fpTagBypass;
00682         #endif /* CORE_H_*/
00683         #endif /*McPAT06_H*/
00684 
00685         //McPAT07 parameters
00686         #ifdef McPAT07_H
00687         #ifdef  XML_PARSE_H_
00688         ParseXML *p_Mp1;
00689         #endif /*  XML_PARSE_H_ */
00690         #ifdef  PROCESSOR_H_
00691         Processor p_Mproc;
00692         Core *p_Mcore;
00693         SharedCache* l2array;
00694         SharedCache* l3array;
00695         SharedCache* l1dirarray;
00696         SharedCache* l2dirarray;
00697         NoC* nocs;
00698         MemoryController* mc;
00699         #endif /* PROCESSOR_H_*/
00700         #ifdef  CORE_H_
00701         InstFetchU * ifu;
00702         LoadStoreU * lsu;
00703         MemManU    * mmu;
00704         EXECU      * exu;
00705         RENAMINGU  * rnu;
00706         Pipeline   * corepipe;
00707         UndiffCore * undiffCore;
00708         CoreDynParam  coredynp;
00709         
00710         ArrayST * globalBPT;
00711         ArrayST * localBPT; //
00712         ArrayST * L1_localBPT;
00713         ArrayST * L2_localBPT;
00714         ArrayST * chooser;
00715         ArrayST * RAS;
00716         
00717         InstCache icache;
00718         ArrayST * IB;
00719         ArrayST * BTB;
00720         BranchPredictor * BPT;
00721         inst_decoder * ID_inst;
00722         inst_decoder * ID_operand;
00723         inst_decoder * ID_misc;
00724 
00725         ArrayST         * int_inst_window;
00726         ArrayST         * fp_inst_window;
00727         ArrayST         * ROB;
00728         selection_logic * instruction_selection;
00729 
00730         ArrayST * iFRAT;
00731         ArrayST * fFRAT;
00732         ArrayST * iRRAT;
00733         ArrayST * fRRAT;
00734         ArrayST * ifreeL;
00735         ArrayST * ffreeL;
00736         dep_resource_conflict_check * idcl;
00737         dep_resource_conflict_check * fdcl;
00738 
00739         DataCache dcache;
00740         ArrayST * LSQ;//it is actually the store queue but for inorder processors it serves as both loadQ and StoreQ
00741         ArrayST * LoadQ;
00742 
00743         ArrayST * itlb;
00744         ArrayST * dtlb;
00745 
00746         ArrayST * IRF;
00747         ArrayST * FRF;
00748         ArrayST * RFWIN;
00749 
00750         RegFU          * rfu;
00751         SchedulerU     * scheu;
00752         FunctionalUnit * fp_u;
00753         FunctionalUnit * exeu;
00754         FunctionalUnit * mul; //
00755         McPATComponent  bypass;
00756         interconnect * int_bypass;
00757         interconnect * intTagBypass;
00758         interconnect * int_mul_bypass;//
00759         interconnect * intTag_mul_Bypass;//
00760         interconnect * fp_bypass;
00761         interconnect * fpTagBypass;
00762         #endif /* CORE_H_*/
00763         #endif /*McPAT07_H*/
00764 
00765         #ifdef INTSIM_H
00766         IntSim_library *intsim_il1, *intsim_il2, *intsim_dl1, *intsim_dl2, *intsim_itlb, *intsim_dtlb;
00767         IntSim_library *intsim_clock, *intsim_bpred, *intsim_rf, *intsim_io, *intsim_logic, *intsim_alu, *intsim_fpu, *intsim_mult;
00768         IntSim_library *intsim_ib, *intsim_issueQ, *intsim_decoder, *intsim_bypass, *intsim_exeu, *intsim_pipeline;
00769         IntSim_library *intsim_lsq, *intsim_rat, *intsim_rob, *intsim_btb, *intsim_L2, *intsim_mc, *intsim_router, *intsim_loadQ;
00770         IntSim_library *intsim_rename, *intsim_scheduler, *intsim_L3, *intsim_L1dir, *intsim_L2dir;
00771         #endif
00772 
00773 
00774    public:
00775         //Default constructor
00776         Power();
00777         Power(ComponentId_t compID) {
00778             PowerInit(compID);}
00779         void PowerInit(ComponentId_t compID) {
00780             p_compID = compID;
00781             p_powerLevel = 1; p_powerMonitor = false; p_tempMonitor = false; //p_powerModel = McPAT;  // This setting is important since params are not read in order as they apprears
00782             p_meanPeak = p_meanPeakAll = 0.0;
00783             p_areaMcPAT = 0.0; p_maxNumSubComp = 0;
00784             p_ifReadEntireXML = p_ifGetMcPATUnitP = false;
00785             //p_McPATonPipe = p_McPATonIRS = p_McPATonRF = false;  //if xxx has power estimated by McPAT already
00786             #ifdef McPAT05_H
00787             McPAT05initBasic(); //initialize basic InputParameter interface_ip
00788             #endif
00789 
00790             // power usage initialization
00791             memset(&p_usage_cache_il1,0,sizeof(Pdissipation_t));
00792             memset(&p_usage_cache_il2,0,sizeof(Pdissipation_t));
00793             memset(&p_usage_cache_dl1,0,sizeof(Pdissipation_t));
00794             memset(&p_usage_cache_dl2,0,sizeof(Pdissipation_t));
00795             memset(&p_usage_cache_itlb,0,sizeof(Pdissipation_t));
00796             memset(&p_usage_cache_dtlb,0,sizeof(Pdissipation_t));
00797             memset(&p_usage_clock,0,sizeof(Pdissipation_t));
00798             memset(&p_usage_io,0,sizeof(Pdissipation_t));
00799             memset(&p_usage_logic,0,sizeof(Pdissipation_t));
00800             memset(&p_usage_alu,0,sizeof(Pdissipation_t));
00801             memset(&p_usage_fpu,0,sizeof(Pdissipation_t));
00802             memset(&p_usage_mult,0,sizeof(Pdissipation_t));
00803             memset(&p_usage_uarch,0,sizeof(Pdissipation_t));
00804             memset(&p_usage_rf,0,sizeof(Pdissipation_t));
00805             memset(&p_usage_bpred,0,sizeof(Pdissipation_t));
00806             memset(&p_usage_ib,0,sizeof(Pdissipation_t));
00807             memset(&p_usage_rs,0,sizeof(Pdissipation_t));
00808             memset(&p_usage_decoder,0,sizeof(Pdissipation_t));
00809             memset(&p_usage_bypass,0,sizeof(Pdissipation_t));
00810             memset(&p_usage_exeu,0,sizeof(Pdissipation_t));
00811             memset(&p_usage_pipeline,0,sizeof(Pdissipation_t));
00812             memset(&p_usage_lsq,0,sizeof(Pdissipation_t));
00813             memset(&p_usage_rat,0,sizeof(Pdissipation_t));
00814             memset(&p_usage_rob,0,sizeof(Pdissipation_t));
00815             memset(&p_usage_btb,0,sizeof(Pdissipation_t));
00816             memset(&p_usage_cache_l2,0,sizeof(Pdissipation_t));
00817             memset(&p_usage_mc,0,sizeof(Pdissipation_t));
00818             memset(&p_usage_router,0,sizeof(Pdissipation_t));
00819             memset(&p_usage_loadQ,0,sizeof(Pdissipation_t));
00820             memset(&p_usage_renameU,0,sizeof(Pdissipation_t));
00821             memset(&p_usage_schedulerU,0,sizeof(Pdissipation_t));
00822             memset(&p_usage_cache_l3,0,sizeof(Pdissipation_t));
00823             memset(&p_usage_cache_l1dir,0,sizeof(Pdissipation_t));
00824             memset(&p_usage_cache_l2dir,0,sizeof(Pdissipation_t));
00825             memset(&p_unitPower,0,sizeof(Punit_t));
00826             memset(&floorplan_id,0,sizeof(floorplan_id_t));
00827             // device params initilaization
00828             device_tech.clockRate = 2200000000.0; device_tech.machineType = 0; 
00829             device_tech.number_L1dir=1; device_tech.number_L2dir=1;
00830             device_tech.number_L2=1; device_tech.number_L3=1;
00831             device_tech.number_il1=1; device_tech.number_dl1=1;
00832             device_tech.number_itlb=1; device_tech.number_dtlb=1;
00833             // cache params initilaization
00834             /* cache_il1 */
00835             cache_il1_tech.unit_scap.push_back(32768.0); cache_il1_tech.vss = 0.0; cache_il1_tech.op_freq = 0; cache_il1_tech.num_sets = 0;         
00836             cache_il1_tech.line_size.push_back(32); cache_il1_tech.num_bitlines = 0; cache_il1_tech.num_wordlines = 0; cache_il1_tech.assoc.push_back(8);
00837             cache_il1_tech.unit_icap = 0.0; cache_il1_tech.unit_lcap = 0.0; cache_il1_tech.unit_ecap = 0;
00838             cache_il1_tech.num_rwports = cache_il1_tech.num_rports = cache_il1_tech.num_wports = 0; cache_il1_tech.num_banks.push_back(1);
00839             cache_il1_tech.throughput.push_back(3.0); cache_il1_tech.latency.push_back(3.0); cache_il1_tech.core_physical_address_width = 52;
00840             cache_il1_tech.miss_buf_size.push_back(16); cache_il1_tech.fill_buf_size.push_back(16); cache_il1_tech.prefetch_buf_size.push_back(16); cache_il1_tech.wbb_buf_size.push_back(0);
00841             cache_il1_tech.core_virtual_address_width = 64; cache_il1_tech.core_virtual_memory_page_size = 4096; cache_il1_tech.core_number_hardware_threads = 2;       
00842             cache_il1_tech.number_entries = 0; cache_il1_tech.core_temperature=360; cache_il1_tech.core_tech_node=32;  cache_il1_tech.device_type = 0; cache_il1_tech.area = 0.41391e-6; cache_il1_tech.num_transistors = 0.584e6;
00843             cache_il1_tech.directory_type = 1;  
00844             /* cache_il2 */
00845             cache_il2_tech.unit_scap.push_back(0.0); cache_il2_tech.vss = 0.0; cache_il2_tech.op_freq = 0; cache_il2_tech.num_sets = 0;
00846             cache_il2_tech.line_size.push_back(0); cache_il2_tech.num_bitlines = 0; cache_il2_tech.num_wordlines = 0; cache_il2_tech.assoc.push_back(0);
00847             cache_il2_tech.unit_icap = 0.0; cache_il2_tech.unit_lcap = 0.0; cache_il2_tech.unit_ecap = 0;
00848             cache_il2_tech.num_rwports = cache_il2_tech.num_rports = cache_il2_tech.num_wports = 0; cache_il2_tech.num_banks.push_back(0);
00849             cache_il2_tech.throughput.push_back(0.0); cache_il2_tech.latency.push_back(0.0); cache_il2_tech.core_physical_address_width = 0;
00850             cache_il2_tech.miss_buf_size.push_back(0); cache_il2_tech.fill_buf_size.push_back(0); cache_il2_tech.prefetch_buf_size.push_back(0); cache_il2_tech.wbb_buf_size.push_back(0);
00851             cache_il2_tech.core_virtual_address_width = cache_il2_tech.core_virtual_memory_page_size = cache_il2_tech.core_number_hardware_threads = 0; 
00852             cache_il2_tech.number_entries = 0; cache_il2_tech.core_temperature=360; cache_il2_tech.core_tech_node=65; cache_il2_tech.device_type = 0;     
00853             cache_il2_tech.directory_type = 1;  cache_il2_tech.area = 0.41391e-6; cache_il2_tech.num_transistors = 0.584e6;
00854             /* cache_dl1 */
00855             cache_dl1_tech.unit_scap.push_back(16384.0); cache_dl1_tech.vss = 0.0; cache_dl1_tech.op_freq = 0; cache_dl1_tech.num_sets = 0;
00856             cache_dl1_tech.line_size.push_back(32); cache_dl1_tech.num_bitlines = 0; cache_dl1_tech.num_wordlines = 0; cache_dl1_tech.assoc.push_back(8);
00857             cache_dl1_tech.unit_icap = 0.0; cache_dl1_tech.unit_lcap = 0.0; cache_dl1_tech.unit_ecap = 0;
00858             cache_dl1_tech.num_rwports = cache_dl1_tech.num_rports = cache_dl1_tech.num_wports = 1; cache_dl1_tech.num_banks.push_back(1);
00859             cache_dl1_tech.throughput.push_back(3.0); cache_dl1_tech.latency.push_back(3.0); cache_dl1_tech.core_physical_address_width = 52;
00860             cache_dl1_tech.miss_buf_size.push_back(16); cache_dl1_tech.fill_buf_size.push_back(16); cache_dl1_tech.prefetch_buf_size.push_back(16); cache_dl1_tech.wbb_buf_size.push_back(16);
00861             cache_dl1_tech.core_virtual_address_width = cache_dl1_tech.core_virtual_memory_page_size = cache_dl1_tech.core_number_hardware_threads = 0; 
00862             cache_dl1_tech.number_entries = 0; cache_dl1_tech.core_temperature=360; cache_dl1_tech.core_tech_node=32; cache_dl1_tech.device_type = 0;
00863             cache_dl1_tech.directory_type = 1; cache_dl1_tech.area = 0.41391e-6; cache_dl1_tech.num_transistors = 0.584e6;          
00864             /* cache_dl2 */
00865             cache_dl2_tech.unit_scap.push_back(0.0); cache_dl2_tech.vss = 0.0; cache_dl2_tech.op_freq = 0; cache_dl2_tech.num_sets = 0;
00866             cache_dl2_tech.line_size.push_back(0); cache_dl2_tech.num_bitlines = 0; cache_dl2_tech.num_wordlines = 0; cache_dl2_tech.assoc.push_back(0);
00867             cache_dl2_tech.unit_icap = 0.0; cache_dl2_tech.unit_lcap = 0.0; cache_dl2_tech.unit_ecap = 0;
00868             cache_dl2_tech.num_rwports = cache_dl2_tech.num_rports = cache_dl2_tech.num_wports = 0; cache_dl2_tech.num_banks.push_back(0);
00869             cache_dl2_tech.throughput.push_back(0.0); cache_dl2_tech.latency.push_back(0.0); cache_dl2_tech.core_physical_address_width = 0;
00870             cache_dl2_tech.miss_buf_size.push_back(0); cache_dl2_tech.fill_buf_size.push_back(0); cache_dl2_tech.prefetch_buf_size.push_back(0); cache_dl2_tech.wbb_buf_size.push_back(0);
00871             cache_dl2_tech.core_virtual_address_width = cache_dl2_tech.core_virtual_memory_page_size = cache_dl2_tech.core_number_hardware_threads = 0; 
00872             cache_dl2_tech.number_entries = 0; cache_dl2_tech.core_temperature=360; cache_dl2_tech.core_tech_node=65; cache_dl2_tech.device_type = 0;
00873             cache_dl2_tech.directory_type = 1; cache_dl2_tech.area = 0.41391e-6; cache_dl2_tech.num_transistors = 0.584e6;          
00874             /* cache_itlb */
00875             cache_itlb_tech.unit_scap.push_back(0.0); cache_itlb_tech.vss = 0.0; cache_itlb_tech.op_freq = 0; cache_itlb_tech.num_sets = 0;
00876             cache_itlb_tech.line_size.push_back(0); cache_itlb_tech.num_bitlines = 0; cache_itlb_tech.num_wordlines = 0; cache_itlb_tech.assoc.push_back(0);
00877             cache_itlb_tech.unit_icap = 0.0; cache_itlb_tech.unit_lcap = 0.0; cache_itlb_tech.unit_ecap = 0;
00878             cache_itlb_tech.num_rwports = cache_itlb_tech.num_rports = cache_itlb_tech.num_wports = 0; cache_itlb_tech.num_banks.push_back(0);
00879             cache_itlb_tech.throughput.push_back(0); cache_itlb_tech.latency.push_back(0.0); cache_itlb_tech.core_physical_address_width = 0;
00880             cache_itlb_tech.miss_buf_size.push_back(0); cache_itlb_tech.fill_buf_size.push_back(0); cache_itlb_tech.prefetch_buf_size.push_back(0); cache_itlb_tech.wbb_buf_size.push_back(0);  
00881             cache_itlb_tech.core_virtual_address_width = 64; cache_itlb_tech.core_virtual_memory_page_size = 4096; 
00882             cache_itlb_tech.core_number_hardware_threads = 2; cache_itlb_tech.core_physical_address_width = 52; cache_itlb_tech.number_entries = 128;   
00883             cache_itlb_tech.core_temperature=360; cache_itlb_tech.core_tech_node=32;  cache_itlb_tech.device_type = 0;
00884             cache_itlb_tech.directory_type = 1; cache_itlb_tech.area = 0.41391e-6; cache_itlb_tech.num_transistors = 0.584e6;
00885             /* cache_dtlb */
00886             cache_dtlb_tech.unit_scap.push_back(0.0); cache_dtlb_tech.vss = 0.0; cache_dtlb_tech.op_freq = 0; cache_dtlb_tech.num_sets = 0;
00887             cache_dtlb_tech.line_size.push_back(0); cache_dtlb_tech.num_bitlines = 0; cache_dtlb_tech.num_wordlines = 0; cache_dtlb_tech.assoc.push_back(0);
00888             cache_dtlb_tech.unit_icap = 0.0; cache_dtlb_tech.unit_lcap = 0.0; cache_dtlb_tech.unit_ecap = 0;
00889             cache_dtlb_tech.num_rwports = cache_dtlb_tech.num_rports = cache_dtlb_tech.num_wports = 0; cache_dtlb_tech.num_banks.push_back(0);
00890             cache_dtlb_tech.throughput.push_back(0.0); cache_dtlb_tech.latency.push_back(0.0); cache_dtlb_tech.core_physical_address_width = 0;
00891             cache_dtlb_tech.miss_buf_size.push_back(0); cache_dtlb_tech.fill_buf_size.push_back(0); cache_dtlb_tech.prefetch_buf_size.push_back(0); cache_dtlb_tech.wbb_buf_size.push_back(0);    
00892             cache_dtlb_tech.core_virtual_address_width = 64; cache_dtlb_tech.core_virtual_memory_page_size = 4096; 
00893             cache_dtlb_tech.core_number_hardware_threads = 2; cache_dtlb_tech.core_physical_address_width = 52; cache_dtlb_tech.number_entries = 128; 
00894             cache_dtlb_tech.core_temperature=360; cache_dtlb_tech.core_tech_node=32; cache_dtlb_tech.device_type = 0; 
00895             cache_dtlb_tech.directory_type = 1; cache_dtlb_tech.area = 0.41391e-6; cache_dtlb_tech.num_transistors = 0.584e6;
00896             /*clock*/
00897             clock_tech.unit_scap=0.0; clock_tech.unit_icap=0.0; clock_tech.unit_lcap=0.0; clock_tech.vss=0.0; 
00898             clock_tech.op_freq=0; clock_tech.clk_style=NORM_H; clock_tech.skew=0.0; clock_tech.chip_area=0; 
00899             clock_tech.node_cap=0.0; clock_tech.opt_clock_buffer_num=0; clock_tech.unit_ecap=0.0;
00900             clock_tech.core_temperature=360; clock_tech.core_tech_node=65; clock_tech.area = 0.41391e-6; clock_tech.num_transistors = 0.584e6; clock_tech.clock_option = GLOBAL_CLOCK;
00901             /*bpred*/
00902             bpred_tech.unit_icap=0.0; bpred_tech.unit_ecap=0.0; bpred_tech.vss=0.0;
00903             bpred_tech.op_freq=0; bpred_tech.unit_scap=0.0; bpred_tech.bpred_access=0; bpred_tech.nrows=0; bpred_tech.ncols=0;
00904             bpred_tech.num_rwports = bpred_tech.num_rports = bpred_tech.num_wports = 0;   
00905             bpred_tech.global_predictor_bits=2; bpred_tech.global_predictor_entries=4096; bpred_tech.prediction_width=0; bpred_tech.local_predictor_size=10;
00906             bpred_tech.local_predictor_entries=1024; bpred_tech.chooser_predictor_bits=2; bpred_tech.chooser_predictor_entries=4096;  bpred_tech.area = 0.41391e-6; bpred_tech.num_transistors = 0.584e6; 
00907             /*rf*/
00908             rf_tech.unit_scap=0.0; rf_tech.unit_icap=0.0; rf_tech.unit_ecap=0.0; rf_tech.vss=0.0;
00909             rf_tech.op_freq=0; rf_tech.rf_access=0; rf_tech.nrows=0; rf_tech.ncols=0;
00910             rf_tech.num_rwports = rf_tech.num_rports = rf_tech.num_wports = 0;  
00911             rf_tech.machine_bits = 64; rf_tech.archi_Regs_IRF_size = 32; rf_tech.archi_Regs_FRF_size = 32; rf_tech.core_issue_width = 1;  
00912             rf_tech.core_register_windows_size = 8;  rf_tech.core_number_hardware_threads = 4;      
00913             rf_tech.core_temperature=360; rf_tech.core_tech_node=65; rf_tech.core_opcode_width =8;  rf_tech.core_virtual_address_width = 64; rf_tech.area = 0.41391e-6; rf_tech.num_transistors = 0.584e6;
00914             /*io*/
00915             io_tech.unit_scap=0.0; io_tech.unit_icap=0.0; io_tech.unit_lcap=0.0; io_tech.vss=0.0; io_tech.op_freq=0;
00916             io_tech.i_o_style=OUT; io_tech.opt_io_buffer_num=0; io_tech.ustrip_len=0.0; io_tech.bus_width=0;    
00917             io_tech.bus_size=0; io_tech.io_access_time=0; io_tech.io_cycle_time=0; io_tech.unit_ecap=0.0;
00918             io_tech.area = 0.41391e-6; io_tech.num_transistors = 0.584e6;                       
00919             /*logic*/
00920             logic_tech.unit_scap=0.0; logic_tech.unit_icap=0.0; logic_tech.unit_lcap=0.0; logic_tech.vss=0.0; 
00921             logic_tech.op_freq=0; logic_tech.lgc_style=STATIC; logic_tech.num_gates=0; logic_tech.num_functions=0;
00922             logic_tech.num_fan_in=0; logic_tech.num_fan_out=0; logic_tech.unit_ecap=0.0;
00923             logic_tech.core_instruction_window_size = 64; logic_tech.core_issue_width = 1; logic_tech.core_number_hardware_threads = 4;
00924             logic_tech.core_decode_width = 1;  logic_tech.archi_Regs_IRF_size = 32; logic_tech.archi_Regs_FRF_size = 32;        
00925             logic_tech.core_temperature=360; logic_tech.core_tech_node=65;   
00926             logic_tech.area = 0.41391e-6; logic_tech.num_transistors = 0.584e6; 
00927             /*alu*/
00928             alu_tech.unit_scap=50.0; alu_tech.unit_icap=0.0; alu_tech.unit_lcap=0.0; alu_tech.vss=0.0;
00929             alu_tech.op_freq=0; alu_tech.unit_ecap=0.0; alu_tech.area = 0.41391e-6; alu_tech.num_transistors = 0.584e6;   
00930             /*fpu*/
00931             fpu_tech.unit_scap=350.0; fpu_tech.unit_icap=0.0; fpu_tech.unit_lcap=0.0; fpu_tech.vss=0.0;
00932             fpu_tech.op_freq=0; fpu_tech.unit_ecap=0.0; fpu_tech.area = 0.41391e-6; fpu_tech.num_transistors = 0.584e6;      
00933             /*mult*/
00934             mult_tech.unit_scap=0.0; mult_tech.unit_icap=0.0; mult_tech.unit_lcap=0.0; mult_tech.vss=0.0;
00935             mult_tech.op_freq=0; mult_tech.unit_ecap=0.0; mult_tech.area = 0.41391e-6; mult_tech.num_transistors = 0.584e6;
00936             /*IB*/
00937             ib_tech.core_instruction_length = 32; ib_tech.core_issue_width = 1; ib_tech.core_number_hardware_threads = 4;
00938             ib_tech.core_instruction_buffer_size = 20; ib_tech.num_rwports = 1; ib_tech.core_temperature=360; ib_tech.core_tech_node=65;
00939             ib_tech.core_virtual_address_width = 64; ib_tech.core_virtual_memory_page_size = 4096; ib_tech.area = 0.41391e-6; ib_tech.num_transistors = 0.584e6;
00940             /*IRS*/
00941             irs_tech.core_number_hardware_threads = 4;  irs_tech.core_instruction_length = 32;  irs_tech.core_instruction_window_size = 64;
00942             irs_tech.core_issue_width = 1;   
00943             irs_tech.core_temperature=360; irs_tech.core_tech_node=65; irs_tech.area = 0.41391e-6; irs_tech.num_transistors = 0.584e6;
00944             #ifdef McPAT05_H 
00945                 perThreadState = 4; //from McPAT
00946             #endif
00947             /*INST_DECODER*/
00948             decoder_tech.core_opcode_width = 8; decoder_tech.core_temperature=360; decoder_tech.core_tech_node=65;
00949             decoder_tech.area = 0.41391e-6; decoder_tech.num_transistors = 0.584e6;
00950             /*BYPASS*/
00951             bypass_tech.core_number_hardware_threads = 4;  bypass_tech.ALU_per_core = 3;   bypass_tech.machine_bits = 64; 
00952             bypass_tech.FPU_per_core = 1; bypass_tech.core_opcode_width = 8; bypass_tech.core_virtual_address_width =64; bypass_tech.machine_bits = 64;
00953             bypass_tech.core_store_buffer_size =32; bypass_tech.core_memory_ports = 1; bypass_tech.core_temperature=360; bypass_tech.core_tech_node=65; bypass_tech.area = 0.41391e-6; bypass_tech.num_transistors = 0.584e6;
00954             /*EXEU*/
00955             #ifdef McPAT05_H
00956             C_EXEU = 100.0; //pF
00957             #endif
00958             /*PIPELINE*/
00959             pipeline_tech.core_number_hardware_threads = 4;  pipeline_tech.core_fetch_width = 1; pipeline_tech.core_decode_width = 1;
00960             pipeline_tech.core_issue_width = 1; pipeline_tech.core_commit_width = 1; pipeline_tech.core_instruction_length = 32;
00961             pipeline_tech.core_virtual_address_width = 64;  pipeline_tech.core_opcode_width = 8; pipeline_tech.core_int_pipeline_depth = 12;
00962             pipeline_tech.machine_bits = 64;  pipeline_tech.archi_Regs_IRF_size = 32;   pipeline_tech.core_temperature=360; pipeline_tech.core_tech_node=65; pipeline_tech.area = 0.41391e-6; pipeline_tech.num_transistors = 0.584e6;
00963             /*schedulerU*/
00964             #ifdef McPAT06_H 
00965                 perThreadState = 8; //from McPAT
00966             #endif   
00967             #ifdef McPAT07_H 
00968                 perThreadState = 8; //from McPAT
00969             #endif  
00970             /*uarch*/
00971             uarch_tech.unit_scap=0.0; uarch_tech.unit_icap=0.0; uarch_tech.unit_lcap=0.0; uarch_tech.vss=0.0;
00972             uarch_tech.op_freq=0; uarch_tech.unit_ecap=0.0;
00973             /*btb*/
00974             btb_tech.unit_scap = 8192.0; btb_tech.vss = 0.0; btb_tech.op_freq = 0; 
00975             btb_tech.line_size = 4; btb_tech.assoc = 2; btb_tech.num_banks = 1;
00976             btb_tech.throughput =1.0; btb_tech.latency = 3.0; btb_tech.area = 0.41391e-6; btb_tech.num_transistors = 0.584e6;
00977             /*core--McPAT07*/
00978             core_tech.core_physical_address_width=52; core_tech.core_temperature=360; core_tech.core_tech_node=32;
00979             core_tech.core_virtual_address_width =64; core_tech.core_virtual_memory_page_size=4096; core_tech.core_number_hardware_threads=2;           
00980             core_tech.machine_bits=64; core_tech.archi_Regs_IRF_size=32; core_tech.archi_Regs_FRF_size=32;
00981             core_tech.core_issue_width=4; core_tech.core_register_windows_size=8; core_tech.core_opcode_width=11;       
00982             core_tech.core_instruction_window_size=64; core_tech.core_decode_width=4; core_tech.core_instruction_length=32;
00983             core_tech.core_instruction_buffer_size=20; core_tech.ALU_per_core=1; core_tech.FPU_per_core=1; core_tech.MUL_per_core=1; core_tech.core_ROB_size = 80;      
00984             core_tech.core_store_buffer_size=8; core_tech.core_load_buffer_size=32; core_tech.core_memory_ports=1; core_tech.core_fetch_width=4;
00985             core_tech.core_commit_width=4; core_tech.core_int_pipeline_depth=12; core_tech.core_phy_Regs_IRF_size=80; core_tech.core_phy_Regs_FRF_size=80; core_tech.core_RAS_size=32;  
00986             core_tech.core_number_of_NoCs = 1;  core_tech.core_number_instruction_fetch_ports = 1; core_tech.core_fp_issue_width = 1; core_tech.core_fp_instruction_window_size =64;
00987             core_tech.core_long_channel = 1; core_tech.core_peak_issue_width=4; core_tech.core_micro_opcode_width=11;
00988             /*core--McPAT06*/
00989             /*core_tech.core_physical_address_width=52; core_tech.core_temperature=360; core_tech.core_tech_node=32;
00990             core_tech.core_virtual_address_width =64; core_tech.core_virtual_memory_page_size=4096; core_tech.core_number_hardware_threads=2;           
00991             core_tech.machine_bits=64; core_tech.archi_Regs_IRF_size=32; core_tech.archi_Regs_FRF_size=32;
00992             core_tech.core_issue_width=4; core_tech.core_register_windows_size=8; core_tech.core_opcode_width=11;       
00993             core_tech.core_instruction_window_size=64; core_tech.core_decode_width=4; core_tech.core_instruction_length=32;
00994             core_tech.core_instruction_buffer_size=20; core_tech.ALU_per_core=1; core_tech.FPU_per_core=1; core_tech.core_ROB_size = 80;        
00995             core_tech.core_store_buffer_size=8; core_tech.core_load_buffer_size=32; core_tech.core_memory_ports=1; core_tech.core_fetch_width=4;
00996             core_tech.core_commit_width=4; core_tech.core_int_pipeline_depth=12; core_tech.core_phy_Regs_IRF_size=80; core_tech.core_phy_Regs_FRF_size=80; core_tech.core_RAS_size=32;  
00997             core_tech.core_number_of_NoCs = 1;  core_tech.core_number_instruction_fetch_ports = 1; core_tech.core_fp_issue_width = 1; core_tech.core_fp_instruction_window_size =64;*/
00998             /*core--McPAT05*/
00999             /*core_tech.core_physical_address_width=52; core_tech.core_temperature=360; core_tech.core_tech_node=65;
01000             core_tech.core_virtual_address_width =64; core_tech.core_virtual_memory_page_size=4096; core_tech.core_number_hardware_threads=4;           
01001             core_tech.machine_bits=64; core_tech.archi_Regs_IRF_size=32; core_tech.archi_Regs_FRF_size=32;
01002             core_tech.core_issue_width=1; core_tech.core_register_windows_size=8; core_tech.core_opcode_width=8;        
01003             core_tech.core_instruction_window_size=64; core_tech.core_decode_width=1; core_tech.core_instruction_length=32;
01004             core_tech.core_instruction_buffer_size=20; core_tech.ALU_per_core=3; core_tech.FPU_per_core=1; core_tech.core_ROB_size = 80;        
01005             core_tech.core_store_buffer_size=32; core_tech.core_load_buffer_size=32; core_tech.core_memory_ports=1; core_tech.core_fetch_width=1;
01006             core_tech.core_commit_width=1; core_tech.core_int_pipeline_depth=12; core_tech.core_phy_Regs_IRF_size=80; core_tech.core_phy_Regs_FRF_size=80; core_tech.core_RAS_size=32;  
01007             core_tech.core_number_of_NoCs = 1;*/
01008             /*cache_l2*/
01009             cache_l2_tech.unit_scap.push_back(262144.0); cache_l2_tech.vss = 0.0; cache_l2_tech.op_freq = 3500000000.0; cache_l2_tech.num_sets = 0;         
01010             cache_l2_tech.line_size.push_back(64); cache_l2_tech.num_bitlines = 0; cache_l2_tech.num_wordlines = 0; cache_l2_tech.assoc.push_back(16);
01011             cache_l2_tech.unit_icap = 0.0; cache_l2_tech.unit_lcap = 0.0; cache_l2_tech.unit_ecap = 0;
01012             cache_l2_tech.num_rwports = cache_l2_tech.num_rports = cache_l2_tech.num_wports = 1; cache_l2_tech.num_banks.push_back(1);
01013             cache_l2_tech.throughput.push_back(100.0); cache_l2_tech.latency.push_back(100.0); cache_l2_tech.core_physical_address_width = 52;
01014             cache_l2_tech.miss_buf_size.push_back(8); cache_l2_tech.fill_buf_size.push_back(8); cache_l2_tech.prefetch_buf_size.push_back(8); cache_l2_tech.wbb_buf_size.push_back(8);
01015             cache_l2_tech.core_virtual_address_width = cache_l2_tech.core_virtual_memory_page_size = cache_l2_tech.core_number_hardware_threads = 0;    
01016             cache_l2_tech.number_entries = 0; cache_l2_tech.core_temperature=360; cache_l2_tech.core_tech_node=65; cache_l2_tech.device_type = 1; 
01017             cache_l2_tech.directory_type = 1; cache_l2_tech.area = 0.41391e-6; cache_l2_tech.num_transistors = 0.584e6;
01018             /*cache_l3*/
01019             cache_l3_tech.unit_scap.push_back(1048576.0); cache_l3_tech.vss = 0.0; cache_l3_tech.op_freq = 3500000000.0; cache_l3_tech.num_sets = 0;        
01020             cache_l3_tech.line_size.push_back(64); cache_l3_tech.num_bitlines = 0; cache_l3_tech.num_wordlines = 0; cache_l3_tech.assoc.push_back(16);
01021             cache_l3_tech.unit_icap = 0.0; cache_l3_tech.unit_lcap = 0.0; cache_l3_tech.unit_ecap = 0;
01022             cache_l3_tech.num_rwports = cache_l3_tech.num_rports = cache_l3_tech.num_wports = 1; cache_l3_tech.num_banks.push_back(1);
01023             cache_l3_tech.throughput.push_back(2.0); cache_l3_tech.latency.push_back(100.0); cache_l3_tech.core_physical_address_width = 52;
01024             cache_l3_tech.miss_buf_size.push_back(16); cache_l3_tech.fill_buf_size.push_back(16); cache_l3_tech.prefetch_buf_size.push_back(16); cache_l3_tech.wbb_buf_size.push_back(16);
01025             cache_l3_tech.core_virtual_address_width = cache_l3_tech.core_virtual_memory_page_size = cache_l3_tech.core_number_hardware_threads = 0;    
01026             cache_l3_tech.number_entries = 0; cache_l3_tech.core_temperature=360; cache_l3_tech.core_tech_node=65; cache_l3_tech.device_type = 0;
01027             cache_l3_tech.directory_type = 1; cache_l3_tech.area = 0.41391e-6; cache_l3_tech.num_transistors = 0.584e6;
01028             /*cache_l1dir*/
01029             cache_l1dir_tech.unit_scap.push_back(1048576.0); cache_l1dir_tech.vss = 0.0; cache_l1dir_tech.op_freq = 3500000000.0; cache_l1dir_tech.num_sets = 0;            
01030             cache_l1dir_tech.line_size.push_back(16); cache_l1dir_tech.num_bitlines = 0; cache_l1dir_tech.num_wordlines = 0; cache_l1dir_tech.assoc.push_back(16);
01031             cache_l1dir_tech.unit_icap = 0.0; cache_l1dir_tech.unit_lcap = 0.0; cache_l1dir_tech.unit_ecap = 0;
01032             cache_l1dir_tech.num_rwports = cache_l1dir_tech.num_rports = cache_l1dir_tech.num_wports =1; cache_l1dir_tech.num_banks.push_back(1);
01033             cache_l1dir_tech.throughput.push_back(2.0); cache_l1dir_tech.latency.push_back(100.0); cache_l1dir_tech.core_physical_address_width = 52;
01034             cache_l1dir_tech.miss_buf_size.push_back(8); cache_l1dir_tech.fill_buf_size.push_back(8); cache_l1dir_tech.prefetch_buf_size.push_back(8); cache_l1dir_tech.wbb_buf_size.push_back(8);
01035             cache_l1dir_tech.core_virtual_address_width = cache_l1dir_tech.core_virtual_memory_page_size = cache_l1dir_tech.core_number_hardware_threads = 0;   
01036             cache_l1dir_tech.number_entries = 0; cache_l1dir_tech.core_temperature=360; cache_l1dir_tech.core_tech_node=65; cache_l1dir_tech.device_type = 0; 
01037             cache_l1dir_tech.directory_type = 1; cache_l1dir_tech.area = 0.41391e-6; cache_l1dir_tech.num_transistors = 0.584e6;
01038             /*cache_l2dir*/
01039             cache_l2dir_tech.unit_scap.push_back(1048576.0); cache_l2dir_tech.vss = 0.0; cache_l2dir_tech.op_freq = 3500000000.0; cache_l2dir_tech.num_sets = 0;            
01040             cache_l2dir_tech.line_size.push_back(16); cache_l2dir_tech.num_bitlines = 0; cache_l2dir_tech.num_wordlines = 0; cache_l2dir_tech.assoc.push_back(16);
01041             cache_l2dir_tech.unit_icap = 0.0; cache_l2dir_tech.unit_lcap = 0.0; cache_l2dir_tech.unit_ecap = 0;
01042             cache_l2dir_tech.num_rwports = cache_l2dir_tech.num_rports = cache_l2dir_tech.num_wports = 1; cache_l2dir_tech.num_banks.push_back(1);
01043             cache_l2dir_tech.throughput.push_back(2.0); cache_l2dir_tech.latency.push_back(100.0); cache_l2dir_tech.core_physical_address_width = 52;
01044             cache_l2dir_tech.miss_buf_size.push_back(8); cache_l2dir_tech.fill_buf_size.push_back(8); cache_l2dir_tech.prefetch_buf_size.push_back(8); cache_l2dir_tech.wbb_buf_size.push_back(8);
01045             cache_l2dir_tech.core_virtual_address_width = cache_l2dir_tech.core_virtual_memory_page_size = cache_l2dir_tech.core_number_hardware_threads = 0;   
01046             cache_l2dir_tech.number_entries = 0; cache_l2dir_tech.core_temperature=360; cache_l2dir_tech.core_tech_node=65; cache_l2dir_tech.device_type = 0;
01047             cache_l2dir_tech.directory_type = 1; cache_l2dir_tech.area = 0.41391e-6; cache_l2dir_tech.num_transistors = 0.584e6;
01048             /*mc*/
01049             mc_tech.mc_clock=400000000.0; mc_tech.llc_line_length=64; mc_tech.databus_width=128; mc_tech.addressbus_width=51; mc_tech.req_window_size_per_channel=32;
01050             mc_tech.memory_channels_per_mc=2; mc_tech.IO_buffer_size_per_channel=32; 
01051             mc_tech.memory_number_ranks=2; mc_tech.memory_peak_transfer_rate=6400;
01052             mc_tech.area = 0.41391e-6; mc_tech.num_transistors = 0.584e6;
01053             /*router*/
01054             router_tech.clockrate=3500000000.0; router_tech.vdd=1.5; router_tech.has_global_link=0; router_tech.flit_bits=128; router_tech.input_buffer_entries_per_vc=16;
01055             router_tech.virtual_channel_per_port=2; router_tech.input_ports=5; router_tech.horizontal_nodes=8; router_tech.vertical_nodes=4;
01056             router_tech.output_ports=8; router_tech.link_throughput=1; router_tech.link_latency=1; router_tech.topology = RING; router_tech.area = 0.41391e-6; router_tech.num_transistors = 0.584e6;
01057             router_tech.link_length = 15500; //unit is micron
01058 
01059             #ifdef LV2_PANALYZER_H
01060             il1_pspec = NULL; il2_pspec = NULL; dl1_pspec = NULL; dl2_pspec = NULL;  itlb_pspec = NULL;
01061             dtlb_pspec = NULL;  clock_pspec = NULL;  logic_pspec = NULL;  mult_pspec = NULL;    
01062             bpred_pspec = NULL; rf_pspec = NULL; alu_pspec = NULL;  fpu_pspec = NULL;            
01063             #endif  
01064             #ifdef IO_PANALYZER_H  
01065             aio_pspec = dio_pspec = NULL;
01066             #endif
01067             #ifdef  XML_PARSE_H_
01068             p_Mp1= new ParseXML();
01069             #endif /*XML_PARSE_H_*/
01070         }
01071 
01072         //Destructor
01073         virtual ~Power() {}
01074 
01075         void setTech(ComponentId_t compID, Component::Params_t params, ptype power_type, pmodel power_model);
01076         void getUnitPower(ptype power_type, int user_data, pmodel power_model);
01077         //Pdissipation_t& getPower(Cycle_t current, ptype power_type, char *user_parms, int total_cycles);
01078         //Pdissipation_t& getPower(Cycle_t current, ptype power_type, usagecounts_t counts, int total_cycles);
01079         Pdissipation_t& getPower(IntrospectedComponent* c, ptype power_type, usagecounts_t counts);  //execution time = total cycles/clock rate
01080         //void updatePowUsage(Pdissipation_t *comp_pusage, const I& totalPowerUsage, const I& dynamicPower, const I& leakage, const I& TDP, Cycle_t current);
01081         void updatePowUsage(IntrospectedComponent *c, ptype power_type, int fid, Pdissipation_t *comp_pusage, const I& totalPowerUsage, const I& dynamicPower, const I& leakage, const I& TDP);
01082         double estimateClockDieAreaSimPan();
01083         double estimateClockNodeCapSimPan();
01084         double estimateAreaMcPAT(){return p_areaMcPAT*1e-6;};
01085         void resetCounts(usagecounts_t *counts);
01086         I getExecutionTime(IntrospectedComponent *c);
01087         void setTech(Component::Params_t deviceParams); // called by setTech to set up device params values and store subcomp floorplan id information
01088         void setChip(Component::Params_t deviceParams);
01089         void floorParamInitialize();
01090         void updateFloorplanAreaInfo(int fid, double area);
01091         void compute_temperature(ComponentId_t compID);
01092         void leakage_feedback(pmodel power_model, parameters_tech_t device_tech, ptype power_type);
01093         void printFloorplanAreaInfo();
01094         void printFloorplanPowerInfo();
01095         void printFloorplanThermalInfo();
01096 
01097         // McPAT interface
01098         #ifdef McPAT05_H
01099         void McPAT05Setup();
01100         /*the following are no longer used*/
01101         void McPAT05initBasic();
01102         void McPATinitIcache();
01103         void McPATinitDcache();
01104         void McPATinitItlb();
01105         void McPATinitDtlb();
01106         void McPATinitIB();
01107         void McPATinitIRS();
01108         void McPATinitRF();
01109         void McPATinitBypass();
01110         void McPATinitLogic();
01111         void McPATinitDecoder();
01112         void McPATinitPipeline();
01113         void McPATinitClock();
01114         #endif
01115 
01116         #ifdef McPAT06_H
01117         void McPAT06Setup();
01118         #endif
01119         #ifdef McPAT07_H
01120         void McPATSetup();
01121         #endif
01122 
01123         friend class boost::serialization::access;
01124         template<class Archive>
01125         void serialize(Archive & ar, const unsigned int version );
01126 
01127         /*
01128         BOOST_SERIALIZE {
01129             _AR_DBG(Power,"start\n");
01130             ar & BOOST_SERIALIZATION_NVP(p_compID);
01131             ar & BOOST_SERIALIZATION_NVP(p_powerLevel);
01132             ar & BOOST_SERIALIZATION_NVP(p_powerMonitor);
01133             ar & BOOST_SERIALIZATION_NVP(p_powerModel);
01134             ar & BOOST_SERIALIZATION_NVP(p_usage_cache_il1);
01135             _AR_DBG(Power,"done\n");
01136         }
01137 
01138         SAVE_CONSTRUCT_DATA(Power)
01139         {
01140             _AR_DBG(Power,"\n");
01141             ComponentId_t p_compID = t->p_compID;
01142             ar << BOOST_SERIALIZATION_NVP( p_compID );
01143         }
01144 
01145         LOAD_CONSTRUCT_DATA(Power)
01146         {
01147             _AR_DBG(Power,"\n");
01148             ComponentId_t p_compID = t->p_compID;
01149             ar >> BOOST_SERIALIZATION_NVP( p_compID );
01150             ::new(t)Power( p_compID );
01151         }
01152         */
01153 
01154 };
01155 }
01156 #endif // POWER_H
01157 
01158 
01159 
01160 

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