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00020
00021 #if !defined (__CPU_ALPHA_H__)
00022 #define __CPU_ALPHA_H__
00023
00024 #include "config.h"
00025
00026 #define TARGET_LONG_BITS 64
00027
00028 #include "cpu-defs.h"
00029
00030 #include <setjmp.h>
00031
00032 #include "softfloat.h"
00033
00034 #define TARGET_HAS_ICE 1
00035
00036 #define ELF_MACHINE EM_ALPHA
00037
00038 #define ICACHE_LINE_SIZE 32
00039 #define DCACHE_LINE_SIZE 32
00040
00041 #define TARGET_PAGE_BITS 12
00042
00043 #define VA_BITS 43
00044
00045
00046 enum {
00047 ALPHA_EV3 = 1,
00048 ALPHA_EV4 = 2,
00049 ALPHA_SIM = 3,
00050 ALPHA_LCA = 4,
00051 ALPHA_EV5 = 5,
00052 ALPHA_EV45 = 6,
00053 ALPHA_EV56 = 7,
00054 };
00055
00056
00057 enum {
00058 ALPHA_EV4_2 = 0,
00059 ALPHA_EV4_3 = 1,
00060 };
00061
00062
00063 enum {
00064 ALPHA_LCA_1 = 1,
00065 ALPHA_LCA_2 = 2,
00066 ALPHA_LCA_3 = 3,
00067 ALPHA_LCA_4 = 4,
00068 ALPHA_LCA_5 = 5,
00069 ALPHA_LCA_6 = 6,
00070 };
00071
00072
00073 enum {
00074 ALPHA_EV5_1 = 1,
00075 ALPHA_EV5_2 = 2,
00076 ALPHA_EV5_3 = 3,
00077 ALPHA_EV5_4 = 4,
00078 ALPHA_EV5_5 = 5,
00079 };
00080
00081
00082 enum {
00083 ALPHA_EV45_1 = 1,
00084 ALPHA_EV45_2 = 2,
00085 ALPHA_EV45_3 = 3,
00086 };
00087
00088
00089 enum {
00090 ALPHA_EV56_1 = 1,
00091 ALPHA_EV56_2 = 2,
00092 };
00093
00094 enum {
00095 IMPLVER_2106x = 0,
00096 IMPLVER_21164 = 1,
00097 IMPLVER_21264 = 2,
00098 IMPLVER_21364 = 3,
00099 };
00100
00101 enum {
00102 AMASK_BWX = 0x00000001,
00103 AMASK_FIX = 0x00000002,
00104 AMASK_CIX = 0x00000004,
00105 AMASK_MVI = 0x00000100,
00106 AMASK_TRAP = 0x00000200,
00107 AMASK_PREFETCH = 0x00001000,
00108 };
00109
00110 enum {
00111 VAX_ROUND_NORMAL = 0,
00112 VAX_ROUND_CHOPPED,
00113 };
00114
00115 enum {
00116 IEEE_ROUND_NORMAL = 0,
00117 IEEE_ROUND_DYNAMIC,
00118 IEEE_ROUND_PLUS,
00119 IEEE_ROUND_MINUS,
00120 IEEE_ROUND_CHOPPED,
00121 };
00122
00123
00124
00125 enum {
00126 FP_TRAP_I = 0x0,
00127 FP_TRAP_U = 0x1,
00128 FP_TRAP_S = 0x4,
00129 FP_TRAP_SU = 0x5,
00130 FP_TRAP_SUI = 0x7,
00131 };
00132
00133
00134 enum {
00135 FP_ROUND_CHOPPED = 0x0,
00136 FP_ROUND_MINUS = 0x1,
00137 FP_ROUND_NORMAL = 0x2,
00138 FP_ROUND_DYNAMIC = 0x3,
00139 };
00140
00141
00142
00143 enum {
00144
00145 IPR_CC = 0xC0,
00146 IPR_CC_CTL = 0xC1,
00147 IPR_VA = 0xC2,
00148 IPR_VA_CTL = 0xC4,
00149 IPR_VA_FORM = 0xC3,
00150
00151 IPR_ITB_TAG = 0x00,
00152 IPR_ITB_PTE = 0x01,
00153 IPT_ITB_IAP = 0x02,
00154 IPT_ITB_IA = 0x03,
00155 IPT_ITB_IS = 0x04,
00156 IPR_PMPC = 0x05,
00157 IPR_EXC_ADDR = 0x06,
00158 IPR_IVA_FORM = 0x07,
00159 IPR_CM = 0x09,
00160 IPR_IER = 0x0A,
00161 IPR_SIRR = 0x0C,
00162 IPR_ISUM = 0x0D,
00163 IPR_HW_INT_CLR = 0x0E,
00164 IPR_EXC_SUM = 0x0F,
00165 IPR_PAL_BASE = 0x10,
00166 IPR_I_CTL = 0x11,
00167 IPR_I_STAT = 0x16,
00168 IPR_IC_FLUSH = 0x13,
00169 IPR_IC_FLUSH_ASM = 0x12,
00170 IPR_CLR_MAP = 0x15,
00171 IPR_SLEEP = 0x17,
00172 IPR_PCTX = 0x40,
00173 IPR_PCTR_CTL = 0x14,
00174
00175 IPR_DTB_TAG0 = 0x20,
00176 IPR_DTB_TAG1 = 0xA0,
00177 IPR_DTB_PTE0 = 0x21,
00178 IPR_DTB_PTE1 = 0xA1,
00179 IPR_DTB_ALTMODE = 0xA6,
00180 IPR_DTB_IAP = 0xA2,
00181 IPR_DTB_IA = 0xA3,
00182 IPR_DTB_IS0 = 0x24,
00183 IPR_DTB_IS1 = 0xA4,
00184 IPR_DTB_ASN0 = 0x25,
00185 IPR_DTB_ASN1 = 0xA5,
00186 IPR_MM_STAT = 0x27,
00187 IPR_M_CTL = 0x28,
00188 IPR_DC_CTL = 0x29,
00189 IPR_DC_STAT = 0x2A,
00190
00191 IPR_C_DATA = 0x2B,
00192 IPR_C_SHIFT = 0x2C,
00193
00194 IPR_ASN,
00195 IPR_ASTEN,
00196 IPR_ASTSR,
00197 IPR_DATFX,
00198 IPR_ESP,
00199 IPR_FEN,
00200 IPR_IPIR,
00201 IPR_IPL,
00202 IPR_KSP,
00203 IPR_MCES,
00204 IPR_PERFMON,
00205 IPR_PCBB,
00206 IPR_PRBR,
00207 IPR_PTBR,
00208 IPR_SCBB,
00209 IPR_SISR,
00210 IPR_SSP,
00211 IPR_SYSPTBR,
00212 IPR_TBCHK,
00213 IPR_TBIA,
00214 IPR_TBIAP,
00215 IPR_TBIS,
00216 IPR_TBISD,
00217 IPR_TBISI,
00218 IPR_USP,
00219 IPR_VIRBND,
00220 IPR_VPTB,
00221 IPR_WHAMI,
00222 IPR_ALT_MODE,
00223 IPR_LAST,
00224 };
00225
00226 typedef struct CPUAlphaState CPUAlphaState;
00227
00228 typedef struct pal_handler_t pal_handler_t;
00229 struct pal_handler_t {
00230
00231 void (*reset)(CPUAlphaState *env);
00232
00233 void (*machine_check)(CPUAlphaState *env);
00234
00235 void (*arithmetic)(CPUAlphaState *env);
00236
00237 void (*interrupt)(CPUAlphaState *env);
00238
00239 void (*dfault)(CPUAlphaState *env);
00240
00241 void (*dtb_miss_pal)(CPUAlphaState *env);
00242
00243 void (*dtb_miss_native)(CPUAlphaState *env);
00244
00245 void (*unalign)(CPUAlphaState *env);
00246
00247 void (*itb_miss)(CPUAlphaState *env);
00248
00249 void (*itb_acv)(CPUAlphaState *env);
00250
00251 void (*opcdec)(CPUAlphaState *env);
00252
00253 void (*fen)(CPUAlphaState *env);
00254
00255 void (*call_pal)(CPUAlphaState *env, uint32_t palcode);
00256 };
00257
00258 #define NB_MMU_MODES 4
00259
00260 struct CPUAlphaState {
00261 uint64_t ir[31];
00262 float64 fir[31];
00263 float_status fp_status;
00264 uint64_t fpcr;
00265 uint64_t pc;
00266 uint64_t lock;
00267 uint32_t pcc[2];
00268 uint64_t ipr[IPR_LAST];
00269 uint64_t ps;
00270 uint64_t unique;
00271 int saved_mode;
00272 int intr_flag;
00273
00274 #if TARGET_LONG_BITS > HOST_LONG_BITS
00275
00276
00277
00278 target_ulong t0, t1;
00279 #endif
00280
00281
00282 CPU_COMMON
00283
00284 uint32_t hflags;
00285
00286 int error_code;
00287
00288 uint32_t features;
00289 uint32_t amask;
00290 int implver;
00291 pal_handler_t *pal_handler;
00292 };
00293
00294 #define CPUState CPUAlphaState
00295 #define cpu_init cpu_alpha_init
00296 #define cpu_exec cpu_alpha_exec
00297 #define cpu_gen_code cpu_alpha_gen_code
00298 #define cpu_signal_handler cpu_alpha_signal_handler
00299
00300
00301 #define MMU_MODE0_SUFFIX _kernel
00302 #define MMU_MODE1_SUFFIX _executive
00303 #define MMU_MODE2_SUFFIX _supervisor
00304 #define MMU_MODE3_SUFFIX _user
00305 #define MMU_USER_IDX 3
00306 static inline int cpu_mmu_index (CPUState *env)
00307 {
00308 return (env->ps >> 3) & 3;
00309 }
00310
00311 #if defined(CONFIG_USER_ONLY)
00312 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
00313 {
00314 if (newsp)
00315 env->ir[30] = newsp;
00316
00317 }
00318 #endif
00319
00320 #include "cpu-all.h"
00321 #include "exec-all.h"
00322
00323 enum {
00324 FEATURE_ASN = 0x00000001,
00325 FEATURE_SPS = 0x00000002,
00326 FEATURE_VIRBND = 0x00000004,
00327 FEATURE_TBCHK = 0x00000008,
00328 };
00329
00330 enum {
00331 EXCP_RESET = 0x0000,
00332 EXCP_MCHK = 0x0020,
00333 EXCP_ARITH = 0x0060,
00334 EXCP_HW_INTERRUPT = 0x00E0,
00335 EXCP_DFAULT = 0x01E0,
00336 EXCP_DTB_MISS_PAL = 0x09E0,
00337 EXCP_ITB_MISS = 0x03E0,
00338 EXCP_ITB_ACV = 0x07E0,
00339 EXCP_DTB_MISS_NATIVE = 0x08E0,
00340 EXCP_UNALIGN = 0x11E0,
00341 EXCP_OPCDEC = 0x13E0,
00342 EXCP_FEN = 0x17E0,
00343 EXCP_CALL_PAL = 0x2000,
00344 EXCP_CALL_PALP = 0x3000,
00345 EXCP_CALL_PALE = 0x4000,
00346
00347 EXCP_CONSOLE_DISPATCH = 0x4001,
00348 EXCP_CONSOLE_FIXUP = 0x4002,
00349 };
00350
00351
00352 enum {
00353 EXCP_ARITH_OVERFLOW,
00354 };
00355
00356 enum {
00357 PALCODE_CALL = 0x00000000,
00358 PALCODE_LD = 0x01000000,
00359 PALCODE_ST = 0x02000000,
00360 PALCODE_MFPR = 0x03000000,
00361 PALCODE_MTPR = 0x04000000,
00362 PALCODE_REI = 0x05000000,
00363 PALCODE_INIT = 0xF0000000,
00364 };
00365
00366 enum {
00367 IR_V0 = 0,
00368 IR_T0 = 1,
00369 IR_T1 = 2,
00370 IR_T2 = 3,
00371 IR_T3 = 4,
00372 IR_T4 = 5,
00373 IR_T5 = 6,
00374 IR_T6 = 7,
00375 IR_T7 = 8,
00376 IR_S0 = 9,
00377 IR_S1 = 10,
00378 IR_S2 = 11,
00379 IR_S3 = 12,
00380 IR_S4 = 13,
00381 IR_S5 = 14,
00382 IR_S6 = 15,
00383 #define IR_FP IR_S6
00384 IR_A0 = 16,
00385 IR_A1 = 17,
00386 IR_A2 = 18,
00387 IR_A3 = 19,
00388 IR_A4 = 20,
00389 IR_A5 = 21,
00390 IR_T8 = 22,
00391 IR_T9 = 23,
00392 IR_T10 = 24,
00393 IR_T11 = 25,
00394 IR_RA = 26,
00395 IR_T12 = 27,
00396 #define IR_PV IR_T12
00397 IR_AT = 28,
00398 IR_GP = 29,
00399 IR_SP = 30,
00400 IR_ZERO = 31,
00401 };
00402
00403 CPUAlphaState * cpu_alpha_init (const char *cpu_model);
00404 int cpu_alpha_exec(CPUAlphaState *s);
00405
00406
00407
00408 int cpu_alpha_signal_handler(int host_signum, void *pinfo,
00409 void *puc);
00410 int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw,
00411 int mmu_idx, int is_softmmu);
00412 void do_interrupt (CPUState *env);
00413
00414 int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp);
00415 int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp);
00416 void pal_init (CPUState *env);
00417 #if !defined (CONFIG_USER_ONLY)
00418 void call_pal (CPUState *env);
00419 #else
00420 void call_pal (CPUState *env, int palcode);
00421 #endif
00422
00423 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
00424 {
00425 env->pc = tb->pc;
00426 }
00427
00428 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
00429 target_ulong *cs_base, int *flags)
00430 {
00431 *pc = env->pc;
00432 *cs_base = 0;
00433 *flags = env->ps;
00434 }
00435
00436 #endif