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sst/core/techModels/libIntSim/chip.h

00001 /*
00002         This simulator is C/C++ version of IntSim.
00003 
00004         Original copy was developed by D. Sekar, R. Venkatesan, R. Sarvari, K. Shakeri,
00005         J. Davis, and Prof. J. Meindl from Microelectronics Research Center,
00006         Georgia Tech, Atlanta, GA.
00007         
00008         Reference: D. Sekar, "Optimal Signal, Power, Clock, and Thermal Interconnect
00009         Networks for High-Performance 2D and 3D Integrated Circuits," Ph.D. Dissertation,
00010         School of ECE, Georgia Tech, Atlanta, GA, 2008.
00011 
00012         Copyright 2009
00013         William Song, Prof. Sudhakar Yalamanchili, and Prof. Saibal Mukhopadhyay
00014         Georgia Tech Research Corporation, Atlanta, GA 30332
00015 */
00016 #ifndef CHIP_T
00017 #define CHIP_T
00018 #include "parameters.h"
00019 
00020 class intsim_chip_t {
00021 public:
00022   intsim_chip_t() {}
00023   ~intsim_chip_t() {}
00024 
00025   double total_power;
00026 //  struct intsim_param_t * param;
00027 
00028   int gate_sizing(intsim_param_t * param); // Algorithm Step 2: Logic Gate Sizing
00029   void st_wiring(intsim_param_t * param); // Algorithm Step 3: Generation of Stochastic Wiring Distribution
00030   void baseline_param(intsim_param_t * param, double total_estimated_power); // Algorithm Step 4: Set Baseline Parameters for Iterations
00031   void local_interconnect(intsim_param_t * param); // Algorithm Step 5: Local Interconnect Modeling
00032   void no_repeaters(intsim_param_t * param); // Algorithm Step 6: Arrangement of Wires without Repeaters
00033   void global_interconnect(intsim_param_t * param, double total_estimated_power); // Algorithm Step 7: Global Interconnect Modeling
00034   void insert_repeaters(intsim_param_t * param); // Algorithm Step 8: Assignment of Wires with Repeaters
00035   // Algorithm Step 9: Power Computation and Iteration
00036   void output(intsim_param_t * param, double total_power); // Algorithm Step 10: Data Output
00037 
00038   // The leakage feedback algorithm was added for run-time leakage calculation with thermal simulation
00039   void leakage_feedback(intsim_param_t * intsim_param);
00040 
00041   double leakage_power_logic_gates, dyn_power_logic_gates;
00042   double leakage_power_repeaters, dyn_power_repeaters;
00043   double power_wires, clock_power;
00044   double clock_power_dynamic, clock_power_leakage;
00045   int tier;
00046 
00047 private:
00048   // Power variables
00049   double total_area_logic_gates;
00050   
00051   // Data arrays for integral equations
00052   double *intg_number;
00053   double *intg_length;
00054   double *pitch;
00055   double *net_wire_efficiency;
00056   double *length_max;
00057   double *net_wire_efficiency_repeaters;
00058   double *pitch_updated_with_repeaters;
00059   double *length_max_updated_with_repeaters;
00060   double *number_repeaters;
00061 
00062   // Local parameters
00063   double total_length;
00064   double leakage_power_two_input_nand, dyn_power_two_input_nand;
00065   double leakage_power_inv, dyn_power_inv;
00066   double area_two_input_nand_gate, area_rep_total, available_area;
00067   double total_number_repeaters;
00068   double max_power_repeaters, nv_power_ground;
00069   double global_wire_pitch;
00070   double l_last, lmin, lmax, n;
00071   double phigate, net_wl_rep;
00072   double cbuffer, number_rep_global, size_rep_global;
00073 };
00074 
00075 #endif

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