00001 #ifndef CPU_SPARC_H
00002 #define CPU_SPARC_H
00003
00004 #include "config.h"
00005
00006 #if !defined(TARGET_SPARC64)
00007 #define TARGET_LONG_BITS 32
00008 #define TARGET_FPREGS 32
00009 #define TARGET_PAGE_BITS 12
00010 #else
00011 #define TARGET_LONG_BITS 64
00012 #define TARGET_FPREGS 64
00013 #define TARGET_PAGE_BITS 13
00014 #endif
00015
00016 #define TARGET_PHYS_ADDR_BITS 64
00017
00018 #include "cpu-defs.h"
00019
00020 #include "softfloat.h"
00021
00022 #define TARGET_HAS_ICE 1
00023
00024 #if !defined(TARGET_SPARC64)
00025 #define ELF_MACHINE EM_SPARC
00026 #else
00027 #define ELF_MACHINE EM_SPARCV9
00028 #endif
00029
00030
00031
00032
00033 #ifndef TARGET_SPARC64
00034 #define TT_TFAULT 0x01
00035 #define TT_ILL_INSN 0x02
00036 #define TT_PRIV_INSN 0x03
00037 #define TT_NFPU_INSN 0x04
00038 #define TT_WIN_OVF 0x05
00039 #define TT_WIN_UNF 0x06
00040 #define TT_UNALIGNED 0x07
00041 #define TT_FP_EXCP 0x08
00042 #define TT_DFAULT 0x09
00043 #define TT_TOVF 0x0a
00044 #define TT_EXTINT 0x10
00045 #define TT_CODE_ACCESS 0x21
00046 #define TT_UNIMP_FLUSH 0x25
00047 #define TT_DATA_ACCESS 0x29
00048 #define TT_DIV_ZERO 0x2a
00049 #define TT_NCP_INSN 0x24
00050 #define TT_TRAP 0x80
00051 #else
00052 #define TT_TFAULT 0x08
00053 #define TT_CODE_ACCESS 0x0a
00054 #define TT_ILL_INSN 0x10
00055 #define TT_UNIMP_FLUSH TT_ILL_INSN
00056 #define TT_PRIV_INSN 0x11
00057 #define TT_NFPU_INSN 0x20
00058 #define TT_FP_EXCP 0x21
00059 #define TT_TOVF 0x23
00060 #define TT_CLRWIN 0x24
00061 #define TT_DIV_ZERO 0x28
00062 #define TT_DFAULT 0x30
00063 #define TT_DATA_ACCESS 0x32
00064 #define TT_UNALIGNED 0x34
00065 #define TT_PRIV_ACT 0x37
00066 #define TT_EXTINT 0x40
00067 #define TT_IVEC 0x60
00068 #define TT_TMISS 0x64
00069 #define TT_DMISS 0x68
00070 #define TT_DPROT 0x6c
00071 #define TT_SPILL 0x80
00072 #define TT_FILL 0xc0
00073 #define TT_WOTHER 0x10
00074 #define TT_TRAP 0x100
00075 #endif
00076
00077 #define PSR_NEG_SHIFT 23
00078 #define PSR_NEG (1 << PSR_NEG_SHIFT)
00079 #define PSR_ZERO_SHIFT 22
00080 #define PSR_ZERO (1 << PSR_ZERO_SHIFT)
00081 #define PSR_OVF_SHIFT 21
00082 #define PSR_OVF (1 << PSR_OVF_SHIFT)
00083 #define PSR_CARRY_SHIFT 20
00084 #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
00085 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
00086 #define PSR_EF (1<<12)
00087 #define PSR_PIL 0xf00
00088 #define PSR_S (1<<7)
00089 #define PSR_PS (1<<6)
00090 #define PSR_ET (1<<5)
00091 #define PSR_CWP 0x1f
00092
00093
00094 #define TBR_BASE_MASK 0xfffff000
00095
00096 #if defined(TARGET_SPARC64)
00097 #define PS_IG (1<<11)
00098 #define PS_MG (1<<10)
00099 #define PS_RMO (1<<7)
00100 #define PS_RED (1<<5)
00101 #define PS_PEF (1<<4)
00102 #define PS_AM (1<<3)
00103 #define PS_PRIV (1<<2)
00104 #define PS_IE (1<<1)
00105 #define PS_AG (1<<0)
00106
00107 #define FPRS_FEF (1<<2)
00108
00109 #define HS_PRIV (1<<2)
00110 #endif
00111
00112
00113 #define FSR_RD1 (1ULL << 31)
00114 #define FSR_RD0 (1ULL << 30)
00115 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
00116 #define FSR_RD_NEAREST 0
00117 #define FSR_RD_ZERO FSR_RD0
00118 #define FSR_RD_POS FSR_RD1
00119 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
00120
00121 #define FSR_NVM (1ULL << 27)
00122 #define FSR_OFM (1ULL << 26)
00123 #define FSR_UFM (1ULL << 25)
00124 #define FSR_DZM (1ULL << 24)
00125 #define FSR_NXM (1ULL << 23)
00126 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
00127
00128 #define FSR_NVA (1ULL << 9)
00129 #define FSR_OFA (1ULL << 8)
00130 #define FSR_UFA (1ULL << 7)
00131 #define FSR_DZA (1ULL << 6)
00132 #define FSR_NXA (1ULL << 5)
00133 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
00134
00135 #define FSR_NVC (1ULL << 4)
00136 #define FSR_OFC (1ULL << 3)
00137 #define FSR_UFC (1ULL << 2)
00138 #define FSR_DZC (1ULL << 1)
00139 #define FSR_NXC (1ULL << 0)
00140 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
00141
00142 #define FSR_FTT2 (1ULL << 16)
00143 #define FSR_FTT1 (1ULL << 15)
00144 #define FSR_FTT0 (1ULL << 14)
00145
00146
00147 #ifdef TARGET_SPARC64
00148 #define FSR_FTT_NMASK 0xfffffffffffe3fffULL
00149 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
00150 #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
00151 #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
00152 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
00153 #else
00154 #define FSR_FTT_NMASK 0xfffe3fffULL
00155 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
00156 #define FSR_LDFSR_OLDMASK 0x000fc000ULL
00157 #endif
00158 #define FSR_LDFSR_MASK 0xcfc00fffULL
00159 #define FSR_FTT_IEEE_EXCP (1ULL << 14)
00160 #define FSR_FTT_UNIMPFPOP (3ULL << 14)
00161 #define FSR_FTT_SEQ_ERROR (4ULL << 14)
00162 #define FSR_FTT_INVAL_FPR (6ULL << 14)
00163
00164 #define FSR_FCC1_SHIFT 11
00165 #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
00166 #define FSR_FCC0_SHIFT 10
00167 #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
00168
00169
00170 #define MMU_E (1<<0)
00171 #define MMU_NF (1<<1)
00172
00173 #define PTE_ENTRYTYPE_MASK 3
00174 #define PTE_ACCESS_MASK 0x1c
00175 #define PTE_ACCESS_SHIFT 2
00176 #define PTE_PPN_SHIFT 7
00177 #define PTE_ADDR_MASK 0xffffff00
00178
00179 #define PG_ACCESSED_BIT 5
00180 #define PG_MODIFIED_BIT 6
00181 #define PG_CACHE_BIT 7
00182
00183 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
00184 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
00185 #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
00186
00187
00188 #define MIN_NWINDOWS 3
00189 #define MAX_NWINDOWS 32
00190
00191 #if !defined(TARGET_SPARC64)
00192 #define NB_MMU_MODES 2
00193 #else
00194 #define NB_MMU_MODES 3
00195 typedef struct trap_state {
00196 uint64_t tpc;
00197 uint64_t tnpc;
00198 uint64_t tstate;
00199 uint32_t tt;
00200 } trap_state;
00201 #endif
00202
00203 typedef struct sparc_def_t {
00204 const char *name;
00205 target_ulong iu_version;
00206 uint32_t fpu_version;
00207 uint32_t mmu_version;
00208 uint32_t mmu_bm;
00209 uint32_t mmu_ctpr_mask;
00210 uint32_t mmu_cxr_mask;
00211 uint32_t mmu_sfsr_mask;
00212 uint32_t mmu_trcr_mask;
00213 uint32_t mxcc_version;
00214 uint32_t features;
00215 uint32_t nwindows;
00216 uint32_t maxtl;
00217 } sparc_def_t;
00218
00219 #define CPU_FEATURE_FLOAT (1 << 0)
00220 #define CPU_FEATURE_FLOAT128 (1 << 1)
00221 #define CPU_FEATURE_SWAP (1 << 2)
00222 #define CPU_FEATURE_MUL (1 << 3)
00223 #define CPU_FEATURE_DIV (1 << 4)
00224 #define CPU_FEATURE_FLUSH (1 << 5)
00225 #define CPU_FEATURE_FSQRT (1 << 6)
00226 #define CPU_FEATURE_FMUL (1 << 7)
00227 #define CPU_FEATURE_VIS1 (1 << 8)
00228 #define CPU_FEATURE_VIS2 (1 << 9)
00229 #define CPU_FEATURE_FSMULD (1 << 10)
00230 #define CPU_FEATURE_HYPV (1 << 11)
00231 #define CPU_FEATURE_CMT (1 << 12)
00232 #define CPU_FEATURE_GL (1 << 13)
00233 #ifndef TARGET_SPARC64
00234 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
00235 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
00236 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
00237 CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
00238 #else
00239 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
00240 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
00241 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
00242 CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
00243 CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
00244 enum {
00245 mmu_us_12,
00246 mmu_us_3,
00247 mmu_us_4,
00248 mmu_sun4v,
00249 };
00250 #endif
00251
00252 typedef struct CPUSPARCState {
00253 target_ulong gregs[8];
00254 target_ulong *regwptr;
00255 target_ulong pc;
00256 target_ulong npc;
00257 target_ulong y;
00258
00259
00260 target_ulong cc_src, cc_src2;
00261 target_ulong cc_dst;
00262
00263 target_ulong t0, t1;
00264 target_ulong cond;
00265
00266
00267 uint32_t psr;
00268 target_ulong fsr;
00269 float32 fpr[TARGET_FPREGS];
00270 uint32_t cwp;
00271
00272 uint32_t wim;
00273 target_ulong tbr;
00274 int psrs;
00275 int psrps;
00276 int psret;
00277 uint32_t psrpil;
00278 uint32_t pil_in;
00279 int psref;
00280 target_ulong version;
00281 int interrupt_index;
00282 uint32_t nwindows;
00283
00284 target_ulong regbase[MAX_NWINDOWS * 16 + 8];
00285
00286 CPU_COMMON
00287
00288
00289 #if defined(TARGET_SPARC64)
00290 uint64_t lsu;
00291 #define DMMU_E 0x8
00292 #define IMMU_E 0x4
00293 uint64_t immuregs[16];
00294 uint64_t dmmuregs[16];
00295 uint64_t itlb_tag[64];
00296 uint64_t itlb_tte[64];
00297 uint64_t dtlb_tag[64];
00298 uint64_t dtlb_tte[64];
00299 uint32_t mmu_version;
00300 #else
00301 uint32_t mmuregs[32];
00302 uint64_t mxccdata[4];
00303 uint64_t mxccregs[8];
00304 uint64_t mmubpregs[4];
00305 uint64_t prom_addr;
00306 #endif
00307
00308 float64 dt0, dt1;
00309 float128 qt0, qt1;
00310 float_status fp_status;
00311 #if defined(TARGET_SPARC64)
00312 #define MAXTL_MAX 8
00313 #define MAXTL_MASK (MAXTL_MAX - 1)
00314 trap_state *tsptr;
00315 trap_state ts[MAXTL_MAX];
00316 uint32_t xcc;
00317 uint32_t asi;
00318 uint32_t pstate;
00319 uint32_t tl;
00320 uint32_t maxtl;
00321 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
00322 uint64_t agregs[8];
00323 uint64_t bgregs[8];
00324 uint64_t igregs[8];
00325 uint64_t mgregs[8];
00326 uint64_t fprs;
00327 uint64_t tick_cmpr, stick_cmpr;
00328 void *tick, *stick;
00329 uint64_t gsr;
00330 uint32_t gl;
00331
00332 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
00333 void *hstick;
00334 uint32_t softint;
00335 #define SOFTINT_TIMER 1
00336 #define SOFTINT_STIMER (1 << 16)
00337 #endif
00338 sparc_def_t *def;
00339 } CPUSPARCState;
00340
00341
00342 CPUSPARCState *cpu_sparc_init(const char *cpu_model);
00343 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
00344 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
00345 ...));
00346 void cpu_lock(void);
00347 void cpu_unlock(void);
00348 int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
00349 int mmu_idx, int is_softmmu);
00350 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
00351 void dump_mmu(CPUSPARCState *env);
00352
00353
00354 void gen_intermediate_code_init(CPUSPARCState *env);
00355
00356
00357 int cpu_sparc_exec(CPUSPARCState *s);
00358
00359 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
00360 (env->psref? PSR_EF : 0) | \
00361 (env->psrpil << 8) | \
00362 (env->psrs? PSR_S : 0) | \
00363 (env->psrps? PSR_PS : 0) | \
00364 (env->psret? PSR_ET : 0) | env->cwp)
00365
00366 #ifndef NO_CPU_IO_DEFS
00367 static inline void memcpy32(target_ulong *dst, const target_ulong *src)
00368 {
00369 dst[0] = src[0];
00370 dst[1] = src[1];
00371 dst[2] = src[2];
00372 dst[3] = src[3];
00373 dst[4] = src[4];
00374 dst[5] = src[5];
00375 dst[6] = src[6];
00376 dst[7] = src[7];
00377 }
00378
00379 static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
00380 {
00381
00382 if (env1->cwp == env1->nwindows - 1)
00383 memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
00384 env1->cwp = new_cwp;
00385
00386 if (new_cwp == env1->nwindows - 1)
00387 memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
00388 env1->regwptr = env1->regbase + (new_cwp * 16);
00389 }
00390
00391 static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
00392 {
00393 if (unlikely(cwp >= env1->nwindows))
00394 cwp -= env1->nwindows;
00395 return cwp;
00396 }
00397
00398 static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
00399 {
00400 if (unlikely(cwp < 0))
00401 cwp += env1->nwindows;
00402 return cwp;
00403 }
00404 #endif
00405
00406 #define PUT_PSR(env, val) do { int _tmp = val; \
00407 env->psr = _tmp & PSR_ICC; \
00408 env->psref = (_tmp & PSR_EF)? 1 : 0; \
00409 env->psrpil = (_tmp & PSR_PIL) >> 8; \
00410 env->psrs = (_tmp & PSR_S)? 1 : 0; \
00411 env->psrps = (_tmp & PSR_PS)? 1 : 0; \
00412 env->psret = (_tmp & PSR_ET)? 1 : 0; \
00413 cpu_set_cwp(env, _tmp & PSR_CWP); \
00414 } while (0)
00415
00416 #ifdef TARGET_SPARC64
00417 #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
00418 #define PUT_CCR(env, val) do { int _tmp = val; \
00419 env->xcc = (_tmp >> 4) << 20; \
00420 env->psr = (_tmp & 0xf) << 20; \
00421 } while (0)
00422 #define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)
00423
00424 #ifndef NO_CPU_IO_DEFS
00425 static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
00426 {
00427 if (unlikely(cwp >= env1->nwindows || cwp < 0))
00428 cwp = 0;
00429 cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
00430 }
00431 #endif
00432 #endif
00433
00434
00435 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
00436 int is_asi, int size);
00437 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
00438
00439 #define CPUState CPUSPARCState
00440 #define cpu_init cpu_sparc_init
00441 #define cpu_exec cpu_sparc_exec
00442 #define cpu_gen_code cpu_sparc_gen_code
00443 #define cpu_signal_handler cpu_sparc_signal_handler
00444 #define cpu_list sparc_cpu_list
00445
00446 #define CPU_SAVE_VERSION 5
00447
00448
00449 #define MMU_MODE0_SUFFIX _user
00450 #define MMU_MODE1_SUFFIX _kernel
00451 #ifdef TARGET_SPARC64
00452 #define MMU_MODE2_SUFFIX _hypv
00453 #endif
00454 #define MMU_USER_IDX 0
00455 #define MMU_KERNEL_IDX 1
00456 #define MMU_HYPV_IDX 2
00457
00458 static inline int cpu_mmu_index(CPUState *env1)
00459 {
00460 #if defined(CONFIG_USER_ONLY)
00461 return MMU_USER_IDX;
00462 #elif !defined(TARGET_SPARC64)
00463 return env1->psrs;
00464 #else
00465 if (!env1->psrs)
00466 return MMU_USER_IDX;
00467 else if ((env1->hpstate & HS_PRIV) == 0)
00468 return MMU_KERNEL_IDX;
00469 else
00470 return MMU_HYPV_IDX;
00471 #endif
00472 }
00473
00474 static inline int cpu_fpu_enabled(CPUState *env1)
00475 {
00476 #if defined(CONFIG_USER_ONLY)
00477 return 1;
00478 #elif !defined(TARGET_SPARC64)
00479 return env1->psref;
00480 #else
00481 return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
00482 #endif
00483 }
00484
00485 #if defined(CONFIG_USER_ONLY)
00486 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
00487 {
00488 if (newsp)
00489 env->regwptr[22] = newsp;
00490 env->regwptr[0] = 0;
00491
00492
00493 printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
00494 }
00495 #endif
00496
00497 #include "cpu-all.h"
00498 #include "exec-all.h"
00499
00500
00501 void cpu_check_irqs(CPUSPARCState *env);
00502
00503 #ifdef TARGET_SPARC64
00504
00505 void cpu_tick_set_count(void *opaque, uint64_t count);
00506 uint64_t cpu_tick_get_count(void *opaque);
00507 void cpu_tick_set_limit(void *opaque, uint64_t limit);
00508 #endif
00509
00510 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
00511 {
00512 env->pc = tb->pc;
00513 env->npc = tb->cs_base;
00514 }
00515
00516 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
00517 target_ulong *cs_base, int *flags)
00518 {
00519 *pc = env->pc;
00520 *cs_base = env->npc;
00521 #ifdef TARGET_SPARC64
00522
00523 *flags = ((env->pstate & PS_AM) << 2)
00524 | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
00525 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
00526 #else
00527
00528 *flags = (env->psref << 4) | env->psrs;
00529 #endif
00530 }
00531
00532 #endif