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sst/core/techModels/libMcPATbeta06/htree2.h

00001 /*****************************************************************************
00002  *                                McPAT
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00048 
00049 #ifndef __HTREE2_H__
00050 #define __HTREE2_H__
00051 
00052 #include "basic_circuit.h"
00053 #include "McPATcomponent.h"
00054 #include "parameter.h"
00055 #include "assert.h"
00056 #include "subarray.h"
00057 #include "cacti_interface.h"
00058 #include "wire.h"
00059 
00060 // leakge power includes entire htree in a bank (when uca_tree == false)
00061 // leakge power includes only part to one bank when uca_tree == true
00062 
00063 class Htree2 : public McPATComponent
00064 {
00065   public:
00066     Htree2(enum Wire_type wire_model,
00067         double mat_w, double mat_h, int add, int data_in, int search_data_in, int data_out, int search_data_out, int bl, int wl,
00068         enum Htree_type h_type, bool uca_tree_ = false, bool search_tree_ = false,
00069         TechnologyParameter::DeviceType *dt = &(g_tp.peri_global));
00070     ~Htree2() {};
00071 
00072     void in_htree();
00073     void out_htree();
00074 
00075     // repeaters only at h-tree nodes
00076     void limited_in_htree();
00077     void limited_out_htree();
00078     void input_nand(double s1, double s2, double l);
00079     void output_buffer(double s1, double s2, double l);
00080 
00081     double in_rise_time, out_rise_time;
00082 
00083     void set_in_rise_time(double rt)
00084     {
00085       in_rise_time = rt;
00086     }
00087 
00088     double max_unpipelined_link_delay;
00089     powerDef power_bit;
00090 
00091 
00092   private:
00093     double wire_bw;
00094     double init_wire_bw;  // bus width at root
00095     enum Htree_type tree_type;
00096     double htree_hnodes;
00097     double htree_vnodes;
00098     double mat_width;
00099     double mat_height;
00100     int add_bits, data_in_bits,search_data_in_bits,data_out_bits,  search_data_out_bits;
00101     int ndbl, ndwl;
00102     bool uca_tree; // should have full bandwidth to access all banks in the array simultaneously
00103     bool search_tree;
00104 
00105     enum Wire_type wt;
00106     double min_w_nmos;
00107     double min_w_pmos;
00108 
00109     TechnologyParameter::DeviceType *deviceType;
00110 
00111 };
00112 
00113 #endif

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