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sst/core/techModels/libMcPAT/parameter.h

00001 /*****************************************************************************
00002  *                                McPAT
00003  *                      SOFTWARE LICENSE AGREEMENT
00004  *            Copyright 2009 Hewlett-Packard Development Company, L.P.
00005  *                          All Rights Reserved
00006  *
00007  * Permission to use, copy, and modify this software and its documentation is
00008  * hereby granted only under the following terms and conditions.  Both the
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00010  * of the software, derivative works or modified versions, and any portions
00011  * thereof, and both notices must appear in supporting documentation.
00012  *
00013  * Any User of the software ("User"), by accessing and using it, agrees to the
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00019  * software by User, including but not limited to those affording
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00033  * The software may be further distributed by User (but not offered for
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00048 
00049 #ifndef __PARAMETER_H__
00050 #define __PARAMETER_H__
00051 
00052 #include "const.h"
00053 #include "cacti_interface.h"
00054 
00055 // parameters which are functions of certain device technology
00056 class TechnologyParameter
00057 {
00058  public:
00059   class DeviceType
00060   {
00061    public:
00062     double C_g_ideal;
00063     double C_fringe;
00064     double C_overlap;
00065     double C_junc;
00066     double l_phy;
00067     double l_elec;
00068     double R_nch_on;
00069     double R_pch_on;
00070     double Vdd;
00071     double Vth;
00072     double I_on_n;
00073     double I_on_p;
00074     double I_off_n;
00075     double I_off_p;
00076     double C_ox;
00077     double t_ox;
00078     double n_to_p_eff_curr_drv_ratio;
00079 
00080     DeviceType(): C_g_ideal(0), C_fringe(0), C_overlap(0), C_junc(0),
00081                   l_phy(0), l_elec(0), R_nch_on(0), R_pch_on(0),
00082                   Vdd(0), Vth(0),
00083                   I_on_n(0), I_on_p(0), I_off_n(0), I_off_p(0),
00084                   C_ox(0), t_ox(0), n_to_p_eff_curr_drv_ratio(0) { };
00085     void reset()
00086     {
00087       C_g_ideal = 0;
00088       C_fringe  = 0;
00089       C_overlap = 0;
00090       C_junc    = 0;
00091       l_phy     = 0;
00092       l_elec    = 0;
00093       R_nch_on  = 0;
00094       R_pch_on  = 0;
00095       Vdd       = 0;
00096       Vth       = 0;
00097       I_on_n    = 0;
00098       I_on_p    = 0;
00099       I_off_n   = 0;
00100       I_off_p   = 0;
00101       C_ox      = 0;
00102       t_ox      = 0;
00103       n_to_p_eff_curr_drv_ratio = 0;
00104     }
00105   };
00106   class InterconnectType
00107   {
00108    public:
00109     double pitch;
00110     double R_per_um;
00111     double C_per_um;
00112 
00113     InterconnectType(): pitch(0), R_per_um(0), C_per_um(0) { };
00114 
00115     void reset()
00116     {
00117       pitch = 0;
00118       R_per_um = 0;
00119       C_per_um = 0;
00120     }
00121   };
00122   class MemoryType
00123   {
00124    public:
00125     double b_w;
00126     double b_h;
00127     double cell_a_w;
00128     double cell_pmos_w;
00129     double cell_nmos_w;
00130     double Vbitpre;
00131 
00132     void reset()
00133     {
00134       b_w = 0;
00135       b_h = 0;
00136       cell_a_w = 0;
00137       cell_pmos_w = 0;
00138       cell_nmos_w = 0;
00139       Vbitpre = 0;
00140     }
00141   };
00142 
00143   double ram_wl_stitching_overhead_;
00144   double min_w_nmos_;
00145   double max_w_nmos_;
00146   double unit_len_wire_del;
00147   double FO4;
00148   double kinv;
00149   double vpp;
00150   double w_sense_en;
00151   double w_sense_n;
00152   double w_sense_p;
00153   double w_iso;
00154   double w_poly_contact;
00155   double spacing_poly_to_poly;
00156   double spacing_poly_to_contact;
00157 
00158   double w_comp_inv_p1;
00159   double w_comp_inv_p2;
00160   double w_comp_inv_p3;
00161   double w_comp_inv_n1;
00162   double w_comp_inv_n2;
00163   double w_comp_inv_n3;
00164   double w_eval_inv_p;
00165   double w_eval_inv_n;
00166   double w_comp_n;
00167   double w_comp_p;
00168 
00169   double dram_cell_I_on;
00170   double dram_cell_Vdd;
00171   double dram_cell_I_off_worst_case_len_temp;
00172   double dram_cell_C;
00173   double gm_sense_amp_latch;
00174 
00175   double w_nmos_b_mux;
00176   double w_nmos_sa_mux;
00177   double w_pmos_bl_precharge;
00178   double w_pmos_bl_eq;
00179   double MIN_GAP_BET_P_AND_N_DIFFS;
00180   double MIN_GAP_BET_SAME_TYPE_DIFFS;
00181   double HPOWERRAIL;
00182   double cell_h_def;
00183 
00184   DeviceType sram_cell;   // SRAM cell transistor
00185   DeviceType dram_acc;    // DRAM access transistor
00186   DeviceType dram_wl;     // DRAM wordline transistor
00187   DeviceType peri_global; // peripheral global
00188 
00189   InterconnectType wire_local;
00190   InterconnectType wire_inside_mat;
00191   InterconnectType wire_outside_mat;
00192 
00193   MemoryType sram;
00194   MemoryType dram;
00195 
00196   void reset()
00197   {
00198     dram_cell_Vdd  = 0;
00199     dram_cell_I_on = 0;
00200     dram_cell_C    = 0;
00201     vpp            = 0;
00202 
00203     dram_cell_I_off_worst_case_len_temp = 0;
00204 
00205     sram_cell.reset();
00206     dram_acc.reset();
00207     dram_wl.reset();
00208     peri_global.reset();
00209 
00210     wire_local.reset();
00211     wire_inside_mat.reset();
00212     wire_outside_mat.reset();
00213 
00214     sram.reset();
00215     dram.reset();
00216   }
00217 };
00218 
00219 extern InputParameter g_ip;
00220 extern TechnologyParameter g_tp;
00221 
00222 class AreaPower {
00223  public:
00224          double area, maxPower, runtimePower, totalLeakage, totalPower, maxDynamicPower, runtimeDynamicPower;
00225      AreaPower();
00226 };
00227 
00228 #endif
00229 

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