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sst/core/techModels/libMcPAT/wires.h

00001 /*****************************************************************************
00002  *                                McPAT
00003  *                      SOFTWARE LICENSE AGREEMENT
00004  *            Copyright 2009 Hewlett-Packard Development Company, L.P.
00005  *                          All Rights Reserved
00006  *
00007  * Permission to use, copy, and modify this software and its documentation is
00008  * hereby granted only under the following terms and conditions.  Both the
00009  * above copyright notice and this permission notice must appear in all copies
00010  * of the software, derivative works or modified versions, and any portions
00011  * thereof, and both notices must appear in supporting documentation.
00012  *
00013  * Any User of the software ("User"), by accessing and using it, agrees to the
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00017  * modify, distribute copies, create derivate works and publicly display and
00018  * use, any changes, modifications, enhancements or extensions made to the
00019  * software by User, including but not limited to those affording
00020  * compatibility with other hardware or software, but excluding pre-existing
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00025  * Correspondence should be provided to HP at:
00026  *
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00033  * The software may be further distributed by User (but not offered for
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00038  * THE SOFTWARE IS PROVIDED "AS IS" WITH ANY AND ALL ERRORS AND DEFECTS
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00047  ***************************************************************************/
00048 
00049 #ifndef WIRES_H_
00050 #define WIRES_H_
00051 
00052 #include "const.h"
00053 #include "htree.h"
00054 #include "cacti_interface.h"
00055 #include "parameter.h"
00056 #include <vector>
00057 
00058 
00059 //using namespace std;
00060 //class ArrayEdgeToBankEdgeHtreeSizing;
00061 
00062 //for the first version, wire numbers are calculated either implicitly or by depositing the wire_length back.
00063 
00064 class base_wire {
00065 public:
00066         //base_wire(bool _is_default, const InputParameter *configure_interface);
00067         base_wire();
00068         ArrayEdgeToBankEdgeHtreeSizing link_with_repeater_sizing;
00069         InputParameter l_ip;
00070         final_results local_result;
00071         char   name[40];
00072         bool   is_default;
00073         double interconnect_length, area;
00074         double wire_drive_load;
00075         double throughput;
00076         double latency;//TODO: need to follow the design rule that keeps wire latency no more than 1/3 of total delay.
00077         int link_width;
00078         powerDef power_link, total_power;
00079         pair<double, double> ret_val;
00080         virtual void compute_base_power();
00081         void init_wire_external(bool   _is_default, const InputParameter *configure_interface);
00082         void init_wire();
00083         virtual ~base_wire(){};
00084 };//next version will have the computation separated from CACTI
00085 
00086 class wire :public base_wire {
00087 public:
00088         //wire(bool _is_default, const InputParameter *configure_interface);
00089         //wire();
00090         unsigned int start_wiring_level;
00091         unsigned int end_wiring_level;
00092         virtual void optimize_wire();
00093 };//next version will have the computation separated from CACTI
00094 
00095 class MCclock_network : public base_wire
00096 {
00097 public:
00098         //The bits of clock tree will double after each node.
00099         int start_wiring_level;
00100         int end_wiring_level;
00101         double clk_area;
00102         int num_regs;
00103         virtual void optimize_wire();
00104 };
00105 
00106 
00107 #endif /* WIRES_H_ */

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