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00013 #ifndef _PREFETCH_H_
00014 #define _PREFETCH_H_
00015
00016 #include "sst_config.h"
00017 #include <string>
00018 #include <queue>
00019 #include <set>
00020 #include <map>
00021 #ifdef HAVE_UNORDERED_SET
00022 # include <unordered_set>
00023 #elif defined(HAVE_TR1_UNORDERED_SET)
00024 # include <tr1/unordered_set>
00025 #else
00026 # ifdef __GNUC__
00027 # if __GNUC__ < 3
00028 # include <hash_set.h>
00029 namespace extension { using ::hash_set; };
00030 # else
00031 # include <ext/hash_set>
00032
00033 # if __GNUC__ == 3 && __GNUC_MINOR__ == 0
00034 namespace extension = std;
00035 # else
00036 namespace extension = ::__gnu_cxx;
00037 # endif
00038 # endif
00039 # else
00040 # include <hash_set>
00041 # endif
00042 #endif
00043 #include <list>
00044 #include "FE/pool.h"
00045 #include "ssb_DMA_fakeInst.h"
00046 #include "instruction.h"
00047
00048 using namespace std;
00049
00050
00051 class prefetchMC {
00052 public:
00053 virtual ~prefetchMC() {;}
00054
00055
00056
00057 virtual int load()=0;
00058 };
00059
00060
00061
00062
00063 class prefetchProc {
00064 public:
00065 virtual ~prefetchProc() {;}
00066
00067 virtual bool checkCache(const simAddress)=0;
00068
00069 virtual void insertCache(const simAddress)=0;
00070
00071 virtual void sendToMem(instruction *p)=0;
00072
00073 virtual void wakeUpPrefetched(instruction*)=0;
00074
00075 virtual uint64_t getCurrentCycle()=0;
00076 };
00077
00078
00079
00080
00081 class prefetcher {
00082 typedef map<string,string> paramMap_t;
00083
00084 paramMap_t params;
00085 int getValue(string s) {
00086 paramMap_t::iterator i = params.find(s);
00087 if (i != params.end()) {
00088 printf("getValue %s: %s (%d)\n", s.c_str(), i->second.c_str(), atoi(i->second.c_str()));
00089 return atoi(i->second.c_str());
00090 } else {
00091 return -1;
00092 }
00093 }
00094 string getStrValue(string s) {
00095 paramMap_t::iterator i = params.find(s);
00096 if (i != params.end()) {
00097 printf("getStrValue %s: %s\n", s.c_str(), i->second.c_str());
00098 return i->second;
00099 } else {
00100 return "";
00101 }
00102 }
00103
00104
00105 prefetchProc *proc;
00106
00107 int tagged;
00108
00109
00110
00111 int degree;
00112
00113 int adaptive;
00114
00115 unsigned long long adaptQuantaMask;
00116
00117
00118
00119 int adaptMax;
00120
00121
00122
00123 int decDeg;
00124
00125
00126
00127 int incDeg;
00128
00129
00130 int pageShift;
00131
00132
00133
00134 set<fakeDMAInstruction*> fakes;
00135
00136 set<simAddress> addrs;
00137
00138 #ifdef HAVE_UNORDERED_SET
00139 typedef std::unordered_set<simAddress> inCacheSet;
00140 #elif defined(HAVE_TR1_UNORDERED_SET)
00141 typedef std::tr1::unordered_set<simAddress> inCacheSet;
00142 #else
00143 # ifdef __GNUC__
00144 # if __GNUC__ < 3
00145 typedef hash_set<simAddress> inCacheSet;
00146 # elif __GNUC__ == 3 && __GNUC_MINOR__ == 0
00147 typedef std::hash_set<simAddress> inCacheSet;
00148 # else
00149 typedef __gnu_cxx::hash_set<simAddress> inCacheSet;
00150 # endif
00151 # else
00152 typedef std::hash_set<simAddress> inCacheSet;
00153 # endif
00154 #endif
00155
00156
00157
00158
00159 inCacheSet reqInCache;
00160
00161 static pool<fakeDMAInstruction> fakeInst;
00162
00163 unsigned long long requestsIssued;
00164
00165 unsigned long long requestsHit;
00166
00167 unsigned long long totalReq;
00168
00169
00170
00171
00172 unsigned long long overPage;
00173 unsigned long long tooLate;
00174
00175 int adaptions;
00176
00177
00178
00179 int subTotalReq;
00180
00181
00182
00183 int subRequestsHit;
00184
00185
00186 unsigned long long streamReq;
00187
00188 unsigned long long streamsDetected;
00189
00190
00191 int loadAware;
00192
00193 typedef list<instruction *> wakeUpList_t;
00194 typedef map<simAddress, wakeUpList_t > wakeUpMap_t;
00195
00196
00197
00198
00199 wakeUpMap_t wakeUpMap;
00200
00201 prefetchMC *mc;
00202
00203
00204
00205
00206 set<simAddress> streamIssued;
00207
00208 inCacheSet reqInSCache;
00209
00210 unsigned long long streamRequestsHit;
00211
00212
00213 int streams;
00214
00215 int windowL;
00216
00217 int detLeng;
00218
00219 int rr;
00220
00221
00222
00223 set<simAddress> streamSet;
00224
00225 int inWin;
00226
00227 std::queue<simAddress> window;
00228
00229 deque<simAddress> recentStreams;
00230
00231
00232
00233 inCacheSet contigCount;
00234
00235
00236
00237 simAddress lastBlock;
00238 void detectStream(const simAddress);
00239
00240
00241
00242
00243 int stats;
00244
00245 bool memReq(const simAddress, bool &);
00246 public:
00247 prefetcher(paramMap_t, prefetchProc *, prefetchMC *);
00248 typedef enum {INST, DATA} memAccType;
00249 typedef enum {READ,WRITE} memAccDir;
00250 void memRef(const simAddress, const memAccType, const memAccDir, bool hit);
00251 void reportCacheEject(const simAddress);
00252 bool handleParcel(instruction *p);
00253 bool isPreFetching(const simAddress);
00254 void setWakeUp(instruction *, simAddress);
00255 void finish();
00256 void preTic();
00257 };
00258
00259 #endif
00260
00261