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sst/core/techModels/libMcPATbeta06/core.h

00001 /*****************************************************************************
00002  *                                McPAT
00003  *                      SOFTWARE LICENSE AGREEMENT
00004  *            Copyright 2009 Hewlett-Packard Development Company, L.P.
00005  *                          All Rights Reserved
00006  *
00007  * Permission to use, copy, and modify this software and its documentation is
00008  * hereby granted only under the following terms and conditions.  Both the
00009  * above copyright notice and this permission notice must appear in all copies
00010  * of the software, derivative works or modified versions, and any portions
00011  * thereof, and both notices must appear in supporting documentation.
00012  *
00013  * Any User of the software ("User"), by accessing and using it, agrees to the
00014  * terms and conditions set forth herein, and hereby grants back to Hewlett-
00015  * Packard Development Company, L.P. and its affiliated companies ("HP") a
00016  * non-exclusive, unrestricted, royalty-free right and license to copy,
00017  * modify, distribute copies, create derivate works and publicly display and
00018  * use, any changes, modifications, enhancements or extensions made to the
00019  * software by User, including but not limited to those affording
00020  * compatibility with other hardware or software, but excluding pre-existing
00021  * software applications that may incorporate the software.  User further
00022  * agrees to use its best efforts to inform HP of any such changes,
00023  * modifications, enhancements or extensions.
00024  *
00025  * Correspondence should be provided to HP at:
00026  *
00027  * Director of Intellectual Property Licensing
00028  * Office of Strategy and Technology
00029  * Hewlett-Packard Company
00030  * 1501 Page Mill Road
00031  * Palo Alto, California  94304
00032  *
00033  * The software may be further distributed by User (but not offered for
00034  * sale or transferred for compensation) to third parties, under the
00035  * condition that such third parties agree to abide by the terms and
00036  * conditions of this license.
00037  *
00038  * THE SOFTWARE IS PROVIDED "AS IS" WITH ANY AND ALL ERRORS AND DEFECTS
00039  * AND USER ACKNOWLEDGES THAT THE SOFTWARE MAY CONTAIN ERRORS AND DEFECTS.
00040  * HP DISCLAIMS ALL WARRANTIES WITH REGARD TO THE SOFTWARE, INCLUDING ALL
00041  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS.   IN NO EVENT SHALL
00042  * HP BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES
00043  * OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
00044  * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER ACTION, ARISING
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00046  *
00047  ***************************************************************************/
00048 
00049 #ifndef CORE_H_
00050 #define CORE_H_
00051 
00052 #include "XML_Parse.h"
00053 #include "logic.h"
00054 #include "parameter.h"
00055 #include "array.h"
00056 #include "interconnect.h"
00057 #include "basic_components.h"
00058 
00059 class BranchPredictor :public McPATComponent {
00060   public:
00061 
00062         ParseXML *XML;
00063         int  ithCore;
00064         InputParameter interface_ip;
00065         CoreDynParam  coredynp;
00066         double clockRate,executionTime;
00067         double scktRatio, chip_PR_overhead, macro_PR_overhead;
00068         ArrayST * globalBPT;
00069         ArrayST * L1_localBPT;
00070         ArrayST * L2_localBPT;
00071         ArrayST * chooser;
00072         ArrayST * RAS;
00073 
00074         BranchPredictor(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_);
00075     void computeEnergy(bool is_tdp=true);
00076     void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00077         ~BranchPredictor();
00078 
00079         //Added for SST
00080         void SSTcomputeEnergy(bool is_tdp=true, double branch_read=0, double branch_write=0, double RAS_read=0, double RAS_write=0);
00081         ArrayST* SSTreturnGlobalBPT(){return globalBPT;}
00082         ArrayST* SSTreturnL1BPT(){return L1_localBPT;}
00083         ArrayST* SSTreturnChooser(){return chooser;}
00084         ArrayST* SSTreturnRAS(){return RAS;}
00085 };
00086 
00087 
00088 class InstFetchU :public McPATComponent {
00089   public:
00090 
00091         ParseXML *XML;
00092         int  ithCore;
00093         InputParameter interface_ip;
00094         CoreDynParam  coredynp;
00095         double clockRate,executionTime;
00096         double scktRatio, chip_PR_overhead, macro_PR_overhead;
00097         InstCache icache;
00098         ArrayST * IB;
00099         ArrayST * BTB;
00100         BranchPredictor * BPT;
00101 
00102         InstFetchU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_);
00103     void computeEnergy(bool is_tdp=true);
00104     void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00105         ~InstFetchU();
00106 
00107         //Added for SST
00108         void SSTcomputeEnergy(bool is_tdp=true, double il1_read_accesses=0, double il1_read_misses=0, double IB_read=0, double IB_write=0, double BTB_read=0, double BTB_write=0);
00109         InstCache SSTreturnIcache(){return icache;}
00110         ArrayST* SSTreturnIB(){return IB;}
00111         ArrayST* SSTreturnBTB(){return BTB;}
00112         BranchPredictor* SSTreturnBPT(){return BPT;}
00113 };
00114 
00115 
00116 class SchedulerU :public McPATComponent {
00117   public:
00118 
00119         ParseXML *XML;
00120         int  ithCore;
00121         InputParameter interface_ip;
00122         CoreDynParam  coredynp;
00123         double clockRate,executionTime;
00124         double scktRatio, chip_PR_overhead, macro_PR_overhead;
00125         double Iw_height, fp_Iw_height,ROB_height;
00126         ArrayST         * int_inst_window;
00127         ArrayST         * fp_inst_window;
00128         ArrayST         * ROB;
00129     selection_logic * instruction_selection;
00130 
00131     SchedulerU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_);
00132     void computeEnergy(bool is_tdp=true);
00133     void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00134         ~SchedulerU();
00135 
00136         //Added for SST
00137         void SSTcomputeEnergy(bool is_tdp=true, double int_win_read=0, double int_win_write=0, double fp_win_read=0, double fp_win_write=0, double ROB_read=0, double ROB_write=0);
00138         ArrayST* SSTreturnIntWindow(){return int_inst_window;}
00139         ArrayST* SSTreturnFpWindow(){return fp_inst_window;}
00140         ArrayST* SSTreturnROB(){return ROB;}
00141         selection_logic* SSTreturnInstSelection(){return instruction_selection;}
00142 };
00143 
00144 class RENAMINGU :public McPATComponent {
00145   public:
00146 
00147         ParseXML *XML;
00148         int  ithCore;
00149         InputParameter interface_ip;
00150         double clockRate,executionTime;
00151         CoreDynParam  coredynp;
00152         ArrayST * iFRAT;
00153         ArrayST * fFRAT;
00154         ArrayST * iRRAT;
00155         ArrayST * fRRAT;
00156         ArrayST * ifreeL;
00157         ArrayST * ffreeL;
00158         dep_resource_conflict_check * idcl;
00159         dep_resource_conflict_check * fdcl;
00160 
00161 
00162         RENAMINGU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_, const CoreDynParam & dyn_p_);
00163     void computeEnergy(bool is_tdp=true);
00164     void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00165         ~RENAMINGU();
00166 
00167         //Added for SST
00168         void SSTcomputeEnergy(bool is_tdp=true, double iFRAT_read=0, double iFRAT_write=0, double iFRAT_search=0, double fFRAT_read=0, double fFRAT_write=0, double fFRAT_search=0, double iRRAT_write=0, double fRRAT_write=0, double ifreeL_read=0, double ifreeL_write=0, double ffreeL_read=0, double ffreeL_write=0, double idcl_read=0, double fdcl_read=0);
00169         ArrayST* SSTreturnIFRAT(){return iFRAT;}
00170         ArrayST* SSTreturnFFRAT(){return fFRAT;}
00171         ArrayST* SSTreturnIRRAT(){return iRRAT;}
00172         ArrayST* SSTreturnFRRAT(){return fRRAT;}
00173         ArrayST* SSTreturnIfreeL(){return ifreeL;}
00174         ArrayST* SSTreturnFfreeL(){return ffreeL;}
00175         dep_resource_conflict_check* SSTreturnIDCL(){return idcl;}
00176         dep_resource_conflict_check* SSTreturnFDCL(){return fdcl;}
00177 };
00178         
00179 
00180 class LoadStoreU :public McPATComponent {
00181   public:
00182 
00183         ParseXML *XML;
00184         int  ithCore;
00185         InputParameter interface_ip;
00186         CoreDynParam  coredynp;
00187         double clockRate,executionTime;
00188         double scktRatio, chip_PR_overhead, macro_PR_overhead;
00189         double lsq_height;
00190         DataCache dcache;
00191         ArrayST * LSQ;//it is actually the store queue but for inorder processors it serves as both loadQ and StoreQ
00192         ArrayST * LoadQ;
00193 
00194         LoadStoreU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_);
00195     void computeEnergy(bool is_tdp=true);
00196     void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00197         ~LoadStoreU();
00198 
00199         //Added for SST
00200         void SSTcomputeEnergy(bool is_tdp=true, double dl1_read=0, double dl1_readmiss=0, double dl1_write=0, double dl1_writemiss=0, double LSQ_read=0, double LSQ_write=0);
00201         DataCache SSTreturnDcache(){return dcache;}
00202         ArrayST* SSTreturnLSQ(){return LSQ;}
00203         ArrayST* SSTreturnLoadQ(){return LoadQ;}
00204 };
00205 
00206 class MemManU :public McPATComponent {
00207   public:
00208 
00209         ParseXML *XML;
00210         int  ithCore;
00211         InputParameter interface_ip;
00212         CoreDynParam  coredynp;
00213         double clockRate,executionTime;
00214         double scktRatio, chip_PR_overhead, macro_PR_overhead;
00215         ArrayST * itlb;
00216         ArrayST * dtlb;
00217 
00218         MemManU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_);
00219     void computeEnergy(bool is_tdp=true);
00220     void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00221         ~MemManU();
00222 
00223         //Added for SST
00224         void SSTcomputeEnergy(bool is_tdp=true, double itlb_read=0, double itlb_readmiss=0, double dtlb_read=0, double dtlb_readmiss=0);
00225         ArrayST* SSTreturnITLB(){return itlb;}
00226         ArrayST* SSTreturnDTLB(){return dtlb;}
00227 };
00228         
00229 
00230 class RegFU :public McPATComponent {
00231   public:
00232 
00233         ParseXML *XML;
00234         int  ithCore;
00235         InputParameter interface_ip;
00236         CoreDynParam  coredynp;
00237         double clockRate,executionTime;
00238         double scktRatio, chip_PR_overhead, macro_PR_overhead;
00239         double int_regfile_height, fp_regfile_height;
00240         ArrayST * IRF;
00241         ArrayST * FRF;
00242         ArrayST * RFWIN;
00243 
00244         RegFU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_);
00245     void computeEnergy(bool is_tdp=true);
00246     void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00247         ~RegFU();
00248 
00249         //Added for SST
00250         void SSTcomputeEnergy(bool is_tdp=true, double int_regfile_reads=0, double int_regfile_writes=0, double float_regfile_reads=0, double float_regfile_writes=0, double RFWIN_read=0, double RFWIN_write=0);
00251         ArrayST* SSTreturnIRF(){return IRF;}
00252         ArrayST* SSTreturnFRF(){return FRF;}
00253         ArrayST* SSTreturnRFWIN(){return RFWIN;}
00254 };
00255 
00256 class EXECU :public McPATComponent {
00257   public:
00258 
00259         ParseXML *XML;
00260         int  ithCore;
00261         InputParameter interface_ip;
00262         double clockRate,executionTime;
00263         double scktRatio, chip_PR_overhead, macro_PR_overhead;
00264         double lsq_height;
00265         CoreDynParam  coredynp;
00266         RegFU          * rfu;
00267         SchedulerU     * scheu;
00268     FunctionalUnit * fp_u;
00269     FunctionalUnit * exeu;
00270         interconnect * int_bypass;
00271         interconnect * intTagBypass;
00272         interconnect * fp_bypass;
00273         interconnect * fpTagBypass;
00274 
00275         McPATComponent  bypass;
00276 
00277         EXECU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_, double lsq_height_,const CoreDynParam & dyn_p_);
00278     void computeEnergy(bool is_tdp=true);
00279         void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00280         ~EXECU();
00281 
00282         //Added for SST
00283         void SSTcomputeEnergy(bool is_tdp=true, double bypass_access=0);
00284         RegFU* SSTreturnRFU(){return rfu;}
00285         SchedulerU* SSTreturnSCHEU(){return scheu;}
00286         FunctionalUnit* SSTreturnFPU(){return fp_u;}
00287         FunctionalUnit* SSTreturnEXEU(){return exeu;}
00288         interconnect* SSTreturnIntBy(){return int_bypass;}
00289         interconnect* SSTreturnIntTagBy(){return intTagBypass;}
00290         interconnect* SSTreturnFpBy(){return fp_bypass;}
00291         interconnect* SSTreturnFpTagBy(){return fpTagBypass;}
00292         McPATComponent SSTreturnBy(){return bypass;}
00293 };
00294 
00295 
00296 class Core :public McPATComponent {
00297   public:
00298 
00299         ParseXML *XML;
00300         int  ithCore;
00301         InputParameter interface_ip;
00302         double clockRate,executionTime;
00303         double scktRatio, chip_PR_overhead, macro_PR_overhead;
00304         InstFetchU * ifu;
00305         LoadStoreU * lsu;
00306         MemManU    * mmu;
00307         EXECU      * exu;
00308         RENAMINGU  * rnu;
00309     Pipeline   * corepipe;
00310     UndiffCore * undiffCore;
00311     CoreDynParam  coredynp;
00312     //full_decoder      inst_decoder;
00313     //clock_network     clockNetwork;
00314         Core(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_);
00315         void set_core_param();
00316         void computeEnergy(bool is_tdp=true);
00317         void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
00318         ~Core();
00319 
00320         //Added for SST
00321         InstFetchU* SSTreturnIFU(){return ifu;}
00322         LoadStoreU* SSTreturnLSU(){return lsu;}
00323         MemManU* SSTreturnMMU(){return mmu;}
00324         EXECU* SSTreturnEXU(){return exu;}
00325         RENAMINGU* SSTreturnRNU(){return rnu;}
00326         Pipeline* SSTreturnPIPE(){return corepipe;}
00327 };
00328 
00329 #endif /* CORE_H_ */

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