00001 /*------------------------------------------------------------------------- 00002 * ORION 2.0 00003 * 00004 * Copyright 2009 00005 * Princeton University, and Regents of the University of California 00006 * All Rights Reserved 00007 * 00008 * 00009 * ORION 2.0 was developed by Bin Li at Princeton University and Kambiz Samadi at 00010 * University of California, San Diego. ORION 2.0 was built on top of ORION 1.0. 00011 * ORION 1.0 was developed by Hangsheng Wang, Xinping Zhu and Xuning Chen at 00012 * Princeton University. 00013 * 00014 * If your use of this software contributes to a published paper, we 00015 * request that you cite our paper that appears on our website 00016 * http://www.princeton.edu/~peh/orion.html 00017 * 00018 * Permission to use, copy, and modify this software and its documentation is 00019 * granted only under the following terms and conditions. Both the 00020 * above copyright notice and this permission notice must appear in all copies 00021 * of the software, derivative works or modified versions, and any portions 00022 * thereof, and both notices must appear in supporting documentation. 00023 * 00024 * This software may be distributed (but not offered for sale or transferred 00025 * for compensation) to third parties, provided such third parties agree to 00026 * abide by the terms and conditions of this notice. 00027 * 00028 * This software is distributed in the hope that it will be useful to the 00029 * community, but WITHOUT ANY WARRANTY; without even the implied warranty of 00030 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 00031 * 00032 *-----------------------------------------------------------------------*/ 00033 00034 #ifndef _SIM_PORT_H 00035 #define _SIM_PORT_H 00036 00037 /*Technology related parameters */ 00038 #define PARM_TECH_POINT 65 00039 #define PARM_TRANSISTOR_TYPE NVT /* transistor type, HVT, NVT, or LVT */ 00040 #define PARM_Vdd 1.2 00041 #define PARM_Freq 1.0e9 00042 00043 /* router module parameters */ 00044 /* general parameters */ 00045 #define PARM_in_port 8 /* # of router input ports */ 00046 #define PARM_cache_in_port 0 /* # of cache input ports */ 00047 #define PARM_mc_in_port 0 /* # of memory controller input ports */ 00048 #define PARM_io_in_port 0 /* # of I/O device input ports */ 00049 #define PARM_out_port 8 00050 #define PARM_cache_out_port 0 /* # of cache output ports */ 00051 #define PARM_mc_out_port 0 /* # of memory controller output ports */ 00052 #define PARM_io_out_port 0 /* # of I/O device output ports */ 00053 #define PARM_flit_width 128 /* flit width in bits */ 00054 00055 /* virtual channel parameters */ 00056 #define PARM_v_class 1 /* # of total message classes */ 00057 #define PARM_v_channel 2 /* # of virtual channels per virtual message class*/ 00058 #define PARM_cache_class 0 /* # of cache port virtual classes */ 00059 #define PARM_mc_class 0 /* # of memory controller port virtual classes */ 00060 #define PARM_io_class 0 /* # of I/O device port virtual classes */ 00061 /* ?? */ 00062 #define PARM_in_share_buf 0 /* do input virtual channels physically share buffers? */ 00063 #define PARM_out_share_buf 0 /* do output virtual channels physically share buffers? */ 00064 /* ?? */ 00065 #define PARM_in_share_switch 1 /* do input virtual channels share crossbar input ports? */ 00066 #define PARM_out_share_switch 1 /* do output virtual channels share crossbar output ports? */ 00067 00068 /* crossbar parameters */ 00069 #define PARM_crossbar_model MULTREE_CROSSBAR /* crossbar model type MATRIX_CROSSBAR or MULTREE_CROSSBAR*/ 00070 #define PARM_crsbar_degree 4 /* crossbar mux degree */ 00071 #define PARM_connect_type TRISTATE_GATE /* crossbar connector type TRISTATE_GATE or TRANS_GATE */ 00072 #define PARM_trans_type NP_GATE /* crossbar transmission gate type */ 00073 #define PARM_crossbar_in_len 0 /* crossbar input line length, if known */ 00074 #define PARM_crossbar_out_len 0 /* crossbar output line length, if known */ 00075 #define PARM_xb_in_seg 0 00076 #define PARM_xb_out_seg 0 00077 /* HACK HACK HACK */ 00078 #define PARM_exp_xb_model SIM_NO_MODEL /* the other parameter is MATRIX_CROSSBAR */ 00079 #define PARM_exp_in_seg 2 00080 #define PARM_exp_out_seg 2 00081 00082 /* input buffer parameters */ 00083 #define PARM_in_buf 1 /* have input buffer? */ 00084 #define PARM_in_buf_set 5 00085 #define PARM_in_buf_rport 1 /* # of read ports */ 00086 #define PARM_in_buffer_type SRAM /*buffer model type, SRAM or REGISTER*/ 00087 00088 #define PARM_cache_in_buf 0 00089 #define PARM_cache_in_buf_set 0 00090 #define PARM_cache_in_buf_rport 0 00091 00092 #define PARM_mc_in_buf 0 00093 #define PARM_mc_in_buf_set 0 00094 #define PARM_mc_in_buf_rport 0 00095 00096 #define PARM_io_in_buf 0 00097 #define PARM_io_in_buf_set 0 00098 #define PARM_io_in_buf_rport 0 00099 00100 /* output buffer parameters */ 00101 #define PARM_out_buf 0 00102 #define PARM_out_buf_set 1 00103 #define PARM_out_buf_wport 1 00104 #define PARM_out_buffer_type SRAM /*buffer model type, SRAM or REGISTER*/ 00105 00106 /* central buffer parameters */ 00107 #define PARM_central_buf 0 /* have central buffer? */ 00108 #define PARM_cbuf_set 2560 /* # of rows */ 00109 #define PARM_cbuf_rport 2 /* # of read ports */ 00110 #define PARM_cbuf_wport 2 /* # of write ports */ 00111 #define PARM_cbuf_width 4 /* # of flits in one row */ 00112 #define PARM_pipe_depth 4 /* # of banks */ 00113 00114 /* array parameters shared by various buffers */ 00115 #define PARM_wordline_model CACHE_RW_WORDLINE 00116 #define PARM_bitline_model RW_BITLINE 00117 #define PARM_mem_model NORMAL_MEM 00118 #define PARM_row_dec_model GENERIC_DEC 00119 #define PARM_row_dec_pre_model SINGLE_OTHER 00120 #define PARM_col_dec_model SIM_NO_MODEL 00121 #define PARM_col_dec_pre_model SIM_NO_MODEL 00122 #define PARM_mux_model SIM_NO_MODEL 00123 #define PARM_outdrv_model REG_OUTDRV 00124 00125 /* these 3 should be changed together */ 00126 /* use double-ended bitline because the array is too large */ 00127 #define PARM_data_end 2 00128 #define PARM_amp_model GENERIC_AMP 00129 #define PARM_bitline_pre_model EQU_BITLINE 00130 //#define PARM_data_end 1 00131 //#define PARM_amp_model SIM_NO_MODEL 00132 //#define PARM_bitline_pre_model SINGLE_OTHER 00133 00134 /* switch allocator arbiter parameters */ 00135 #define PARM_sw_in_arb_model RR_ARBITER /* input side arbiter model type, MATRIX_ARBITER , RR_ARBITER, QUEUE_ARBITER*/ 00136 #define PARM_sw_in_arb_ff_model NEG_DFF /* input side arbiter flip-flop model type */ 00137 #define PARM_sw_out_arb_model RR_ARBITER /* output side arbiter model type, MATRIX_ARBITER */ 00138 #define PARM_sw_out_arb_ff_model NEG_DFF /* output side arbiter flip-flop model type */ 00139 00140 /* virtual channel allocator arbiter parameters */ 00141 #define PARM_vc_allocator_type TWO_STAGE_ARB /*vc allocator type, ONE_STAGE_ARB, TWO_STAGE_ARB, VC_SELECT*/ 00142 #define PARM_vc_in_arb_model RR_ARBITER /*input side arbiter model type for TWO_STAGE_ARB. MATRIX_ARBITER, RR_ARBITER, QUEUE_ARBITER*/ 00143 #define PARM_vc_in_arb_ff_model NEG_DFF /* input side arbiter flip-flop model type */ 00144 #define PARM_vc_out_arb_model RR_ARBITER /*output side arbiter model type (for both ONE_STAGE_ARB and TWO_STAGE_ARB). MATRIX_ARBITER, RR_ARBITER, QUEUE_ARBITER */ 00145 #define PARM_vc_out_arb_ff_model NEG_DFF /* output side arbiter flip-flop model type */ 00146 #define PARM_vc_select_buf_type REGISTER /* vc_select buffer type, SRAM or REGISTER */ 00147 00148 /*link wire parameters*/ 00149 #define WIRE_LAYER_TYPE INTERMEDIATE /*wire layer type, INTERMEDIATE or GLOBAL*/ 00150 #define PARM_width_spacing DWIDTH_DSPACE /*choices are SWIDTH_SSPACE, SWIDTH_DSPACE, DWIDTH_SSPACE, DWIDTH_DSPACE*/ 00151 #define PARM_buffering_scheme MIN_DELAY /*choices are MIN_DELAY, STAGGERED */ 00152 #define PARM_shielding FALSE /*choices are TRUE, FALSE */ 00153 00154 /*clock power parameters*/ 00155 #define PARM_pipelined 1 /*1 means the router is pipelined, 0 means not*/ 00156 #define PARM_H_tree_clock 1 /*1 means calculate H_tree_clock power, 0 means not calculate H_tree_clock*/ 00157 #define PARM_router_diagonal 626 /*router diagonal in micro-meter */ 00158 00159 /* RF module parameters */ 00160 #define PARM_read_port 1 00161 #define PARM_write_port 1 00162 #define PARM_n_regs 64 00163 #define PARM_reg_width 32 00164 00165 #define PARM_ndwl 1 00166 #define PARM_ndbl 1 00167 #define PARM_nspd 1 00168 00169 #define PARM_POWER_STATS 1 00170 00171 #endif /* _SIM_PORT_H */