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00025 #if !defined(PPC_405_H)
00026 #define PPC_405_H
00027
00028 #include "ppc4xx.h"
00029
00030
00031 typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
00032 struct ppc4xx_bd_info_t {
00033 uint32_t bi_memstart;
00034 uint32_t bi_memsize;
00035 uint32_t bi_flashstart;
00036 uint32_t bi_flashsize;
00037 uint32_t bi_flashoffset;
00038 uint32_t bi_sramstart;
00039 uint32_t bi_sramsize;
00040 uint32_t bi_bootflags;
00041 uint32_t bi_ipaddr;
00042 uint8_t bi_enetaddr[6];
00043 uint16_t bi_ethspeed;
00044 uint32_t bi_intfreq;
00045 uint32_t bi_busfreq;
00046 uint32_t bi_baudrate;
00047 uint8_t bi_s_version[4];
00048 uint8_t bi_r_version[32];
00049 uint32_t bi_procfreq;
00050 uint32_t bi_plb_busfreq;
00051 uint32_t bi_pci_busfreq;
00052 uint8_t bi_pci_enetaddr[6];
00053 uint32_t bi_pci_enetaddr2[6];
00054 uint32_t bi_opbfreq;
00055 uint32_t bi_iic_fast[2];
00056 };
00057
00058
00059 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
00060 uint32_t flags);
00061
00062
00063 void ppc4xx_plb_init (CPUState *env);
00064
00065 void ppc4xx_pob_init (CPUState *env);
00066
00067 void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
00068 target_phys_addr_t offset);
00069
00070 void ppc405_ebc_init (CPUState *env);
00071
00072 void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]);
00073
00074 void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
00075 target_phys_addr_t offset);
00076
00077 void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
00078 target_phys_addr_t offset, qemu_irq irq,
00079 CharDriverState *chr);
00080
00081 void ppc405_ocm_init (CPUState *env, unsigned long offset);
00082
00083 void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
00084 target_phys_addr_t offset, qemu_irq irq);
00085
00086 void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
00087 target_phys_addr_t offset, qemu_irq irq[5]);
00088
00089 void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]);
00090
00091 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
00092 target_phys_addr_t ram_sizes[4],
00093 uint32_t sysclk, qemu_irq **picp,
00094 ram_addr_t *offsetp, int do_init);
00095 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
00096 target_phys_addr_t ram_sizes[2],
00097 uint32_t sysclk, qemu_irq **picp,
00098 ram_addr_t *offsetp, int do_init);
00099
00100 CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2],
00101 target_phys_addr_t ram_sizes[2],
00102 uint32_t sysclk, qemu_irq **picp,
00103 ram_addr_t *offsetp);
00104
00105 #endif