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00024 #ifndef DEF2
00025 #define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs, 0)
00026 #endif
00027
00028
00029 DEF2(end, 0, 0, 0, 0)
00030 DEF2(nop, 0, 0, 0, 0)
00031 DEF2(nop1, 0, 0, 1, 0)
00032 DEF2(nop2, 0, 0, 2, 0)
00033 DEF2(nop3, 0, 0, 3, 0)
00034 DEF2(nopn, 0, 0, 1, 0)
00035
00036 DEF2(discard, 1, 0, 0, 0)
00037
00038 DEF2(set_label, 0, 0, 1, 0)
00039 DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS)
00040 DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
00041 DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
00042
00043 DEF2(mov_i32, 1, 1, 0, 0)
00044 DEF2(movi_i32, 1, 0, 1, 0)
00045
00046 DEF2(ld8u_i32, 1, 1, 1, 0)
00047 DEF2(ld8s_i32, 1, 1, 1, 0)
00048 DEF2(ld16u_i32, 1, 1, 1, 0)
00049 DEF2(ld16s_i32, 1, 1, 1, 0)
00050 DEF2(ld_i32, 1, 1, 1, 0)
00051 DEF2(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
00052 DEF2(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
00053 DEF2(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
00054
00055 DEF2(add_i32, 1, 2, 0, 0)
00056 DEF2(sub_i32, 1, 2, 0, 0)
00057 DEF2(mul_i32, 1, 2, 0, 0)
00058 #ifdef TCG_TARGET_HAS_div_i32
00059 DEF2(div_i32, 1, 2, 0, 0)
00060 DEF2(divu_i32, 1, 2, 0, 0)
00061 DEF2(rem_i32, 1, 2, 0, 0)
00062 DEF2(remu_i32, 1, 2, 0, 0)
00063 #else
00064 DEF2(div2_i32, 2, 3, 0, 0)
00065 DEF2(divu2_i32, 2, 3, 0, 0)
00066 #endif
00067 DEF2(and_i32, 1, 2, 0, 0)
00068 DEF2(or_i32, 1, 2, 0, 0)
00069 DEF2(xor_i32, 1, 2, 0, 0)
00070
00071 DEF2(shl_i32, 1, 2, 0, 0)
00072 DEF2(shr_i32, 1, 2, 0, 0)
00073 DEF2(sar_i32, 1, 2, 0, 0)
00074
00075 DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
00076 #if TCG_TARGET_REG_BITS == 32
00077 DEF2(add2_i32, 2, 4, 0, 0)
00078 DEF2(sub2_i32, 2, 4, 0, 0)
00079 DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
00080 DEF2(mulu2_i32, 2, 2, 0, 0)
00081 #endif
00082 #ifdef TCG_TARGET_HAS_ext8s_i32
00083 DEF2(ext8s_i32, 1, 1, 0, 0)
00084 #endif
00085 #ifdef TCG_TARGET_HAS_ext16s_i32
00086 DEF2(ext16s_i32, 1, 1, 0, 0)
00087 #endif
00088 #ifdef TCG_TARGET_HAS_bswap_i32
00089 DEF2(bswap_i32, 1, 1, 0, 0)
00090 #endif
00091
00092 #if TCG_TARGET_REG_BITS == 64
00093 DEF2(mov_i64, 1, 1, 0, 0)
00094 DEF2(movi_i64, 1, 0, 1, 0)
00095
00096 DEF2(ld8u_i64, 1, 1, 1, 0)
00097 DEF2(ld8s_i64, 1, 1, 1, 0)
00098 DEF2(ld16u_i64, 1, 1, 1, 0)
00099 DEF2(ld16s_i64, 1, 1, 1, 0)
00100 DEF2(ld32u_i64, 1, 1, 1, 0)
00101 DEF2(ld32s_i64, 1, 1, 1, 0)
00102 DEF2(ld_i64, 1, 1, 1, 0)
00103 DEF2(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
00104 DEF2(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
00105 DEF2(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
00106 DEF2(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
00107
00108 DEF2(add_i64, 1, 2, 0, 0)
00109 DEF2(sub_i64, 1, 2, 0, 0)
00110 DEF2(mul_i64, 1, 2, 0, 0)
00111 #ifdef TCG_TARGET_HAS_div_i64
00112 DEF2(div_i64, 1, 2, 0, 0)
00113 DEF2(divu_i64, 1, 2, 0, 0)
00114 DEF2(rem_i64, 1, 2, 0, 0)
00115 DEF2(remu_i64, 1, 2, 0, 0)
00116 #else
00117 DEF2(div2_i64, 2, 3, 0, 0)
00118 DEF2(divu2_i64, 2, 3, 0, 0)
00119 #endif
00120 DEF2(and_i64, 1, 2, 0, 0)
00121 DEF2(or_i64, 1, 2, 0, 0)
00122 DEF2(xor_i64, 1, 2, 0, 0)
00123
00124 DEF2(shl_i64, 1, 2, 0, 0)
00125 DEF2(shr_i64, 1, 2, 0, 0)
00126 DEF2(sar_i64, 1, 2, 0, 0)
00127
00128 DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
00129 #ifdef TCG_TARGET_HAS_ext8s_i64
00130 DEF2(ext8s_i64, 1, 1, 0, 0)
00131 #endif
00132 #ifdef TCG_TARGET_HAS_ext16s_i64
00133 DEF2(ext16s_i64, 1, 1, 0, 0)
00134 #endif
00135 #ifdef TCG_TARGET_HAS_ext32s_i64
00136 DEF2(ext32s_i64, 1, 1, 0, 0)
00137 #endif
00138 #ifdef TCG_TARGET_HAS_bswap_i64
00139 DEF2(bswap_i64, 1, 1, 0, 0)
00140 #endif
00141 #endif
00142 #ifdef TCG_TARGET_HAS_neg_i32
00143 DEF2(neg_i32, 1, 1, 0, 0)
00144 #endif
00145 #ifdef TCG_TARGET_HAS_neg_i64
00146 DEF2(neg_i64, 1, 1, 0, 0)
00147 #endif
00148
00149
00150 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
00151 DEF2(debug_insn_start, 0, 0, 2, 0)
00152 #else
00153 DEF2(debug_insn_start, 0, 0, 1, 0)
00154 #endif
00155 DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
00156 DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
00157
00158
00159 #if TCG_TARGET_REG_BITS == 32
00160 #if TARGET_LONG_BITS == 32
00161 DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00162 #else
00163 DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00164 #endif
00165 #if TARGET_LONG_BITS == 32
00166 DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00167 #else
00168 DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00169 #endif
00170 #if TARGET_LONG_BITS == 32
00171 DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00172 #else
00173 DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00174 #endif
00175 #if TARGET_LONG_BITS == 32
00176 DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00177 #else
00178 DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00179 #endif
00180 #if TARGET_LONG_BITS == 32
00181 DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00182 #else
00183 DEF2(qemu_ld32u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00184 #endif
00185 #if TARGET_LONG_BITS == 32
00186 DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00187 #else
00188 DEF2(qemu_ld32s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00189 #endif
00190 #if TARGET_LONG_BITS == 32
00191 DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00192 #else
00193 DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00194 #endif
00195
00196 #if TARGET_LONG_BITS == 32
00197 DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00198 #else
00199 DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00200 #endif
00201 #if TARGET_LONG_BITS == 32
00202 DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00203 #else
00204 DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00205 #endif
00206 #if TARGET_LONG_BITS == 32
00207 DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00208 #else
00209 DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00210 #endif
00211 #if TARGET_LONG_BITS == 32
00212 DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00213 #else
00214 DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00215 #endif
00216
00217 #else
00218
00219 DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00220 DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00221 DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00222 DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00223 DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00224 DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00225 DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00226
00227 DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00228 DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00229 DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00230 DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
00231
00232 #endif
00233
00234 #undef DEF2