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00020 #ifndef _CPU_SH4_H
00021 #define _CPU_SH4_H
00022
00023 #include "config.h"
00024
00025 #define TARGET_LONG_BITS 32
00026 #define TARGET_HAS_ICE 1
00027
00028 #define ELF_MACHINE EM_SH
00029
00030
00031 #define SH_CPU_SH7750 (1 << 0)
00032 #define SH_CPU_SH7750S (1 << 1)
00033 #define SH_CPU_SH7750R (1 << 2)
00034 #define SH_CPU_SH7751 (1 << 3)
00035 #define SH_CPU_SH7751R (1 << 4)
00036 #define SH_CPU_SH7785 (1 << 5)
00037 #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
00038 #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
00039
00040 #include "cpu-defs.h"
00041
00042 #include "softfloat.h"
00043
00044 #define TARGET_PAGE_BITS 12
00045
00046 #define SR_MD (1 << 30)
00047 #define SR_RB (1 << 29)
00048 #define SR_BL (1 << 28)
00049 #define SR_FD (1 << 15)
00050 #define SR_M (1 << 9)
00051 #define SR_Q (1 << 8)
00052 #define SR_I3 (1 << 7)
00053 #define SR_I2 (1 << 6)
00054 #define SR_I1 (1 << 5)
00055 #define SR_I0 (1 << 4)
00056 #define SR_S (1 << 1)
00057 #define SR_T (1 << 0)
00058
00059 #define FPSCR_FR (1 << 21)
00060 #define FPSCR_SZ (1 << 20)
00061 #define FPSCR_PR (1 << 19)
00062 #define FPSCR_DN (1 << 18)
00063 #define DELAY_SLOT (1 << 0)
00064 #define DELAY_SLOT_CONDITIONAL (1 << 1)
00065 #define DELAY_SLOT_TRUE (1 << 2)
00066 #define DELAY_SLOT_CLEARME (1 << 3)
00067
00068
00069
00070
00071
00072
00073
00074
00075 typedef struct tlb_t {
00076 uint8_t asid;
00077 uint32_t vpn;
00078 uint8_t v;
00079 uint32_t ppn;
00080 uint8_t sz;
00081 uint32_t size;
00082 uint8_t sh;
00083 uint8_t c;
00084 uint8_t pr;
00085 uint8_t d;
00086 uint8_t wt;
00087 uint8_t sa;
00088 uint8_t tc;
00089 } tlb_t;
00090
00091 #define UTLB_SIZE 64
00092 #define ITLB_SIZE 4
00093
00094 #define NB_MMU_MODES 2
00095
00096 enum sh_features {
00097 SH_FEATURE_SH4A = 1,
00098 SH_FEATURE_BCR3_AND_BCR4 = 2,
00099 };
00100
00101 typedef struct CPUSH4State {
00102 int id;
00103
00104 uint32_t flags;
00105 uint32_t gregs[24];
00106 float32 fregs[32];
00107 uint32_t sr;
00108 uint32_t ssr;
00109 uint32_t spc;
00110 uint32_t gbr;
00111 uint32_t vbr;
00112 uint32_t sgr;
00113 uint32_t dbr;
00114 uint32_t pc;
00115 uint32_t delayed_pc;
00116 uint32_t mach;
00117 uint32_t macl;
00118 uint32_t pr;
00119 uint32_t fpscr;
00120 uint32_t fpul;
00121
00122
00123 float_status fp_status;
00124
00125
00126 uint32_t features;
00127
00128
00129 uint32_t mmucr;
00130 uint32_t pteh;
00131 uint32_t ptel;
00132 uint32_t ptea;
00133 uint32_t ttb;
00134 uint32_t tea;
00135 uint32_t tra;
00136 uint32_t expevt;
00137 uint32_t intevt;
00138
00139 uint32_t pvr;
00140 uint32_t prr;
00141 uint32_t cvr;
00142
00143 uint32_t ldst;
00144
00145 CPU_COMMON tlb_t utlb[UTLB_SIZE];
00146 tlb_t itlb[ITLB_SIZE];
00147 void *intc_handle;
00148 int intr_at_halt;
00149 } CPUSH4State;
00150
00151 CPUSH4State *cpu_sh4_init(const char *cpu_model);
00152 int cpu_sh4_exec(CPUSH4State * s);
00153 int cpu_sh4_signal_handler(int host_signum, void *pinfo,
00154 void *puc);
00155 int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
00156 int mmu_idx, int is_softmmu);
00157 void do_interrupt(CPUSH4State * env);
00158
00159 void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
00160 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
00161 uint32_t mem_value);
00162
00163 static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls)
00164 {
00165 env->gbr = newtls;
00166 }
00167
00168 void cpu_load_tlb(CPUSH4State * env);
00169
00170 #include "softfloat.h"
00171
00172 #define CPUState CPUSH4State
00173 #define cpu_init cpu_sh4_init
00174 #define cpu_exec cpu_sh4_exec
00175 #define cpu_gen_code cpu_sh4_gen_code
00176 #define cpu_signal_handler cpu_sh4_signal_handler
00177 #define cpu_list sh4_cpu_list
00178
00179
00180 #define MMU_MODE0_SUFFIX _kernel
00181 #define MMU_MODE1_SUFFIX _user
00182 #define MMU_USER_IDX 1
00183 static inline int cpu_mmu_index (CPUState *env)
00184 {
00185 return (env->sr & SR_MD) == 0 ? 1 : 0;
00186 }
00187
00188 #if defined(CONFIG_USER_ONLY)
00189 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
00190 {
00191 if (newsp)
00192 env->gregs[15] = newsp;
00193 env->gregs[0] = 0;
00194 }
00195 #endif
00196
00197 #include "cpu-all.h"
00198 #include "exec-all.h"
00199
00200
00201 enum {
00202
00203 ACCESS_PRIV = 0x01,
00204
00205 ACCESS_WRITE = 0x02,
00206
00207 ACCESS_CODE = 0x10,
00208 ACCESS_INT = 0x20
00209 };
00210
00211
00212 #define MMUCR 0x1F000010
00213 #define MMUCR_AT (1<<0)
00214 #define MMUCR_SV (1<<8)
00215 #define MMUCR_URC_BITS (6)
00216 #define MMUCR_URC_OFFSET (10)
00217 #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
00218 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
00219 static inline int cpu_mmucr_urc (uint32_t mmucr)
00220 {
00221 return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
00222 }
00223
00224
00225 #define PTEH_ASID_BITS (8)
00226 #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
00227 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
00228 #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
00229 #define PTEH_VPN_BITS (22)
00230 #define PTEH_VPN_OFFSET (10)
00231 #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
00232 #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
00233 static inline int cpu_pteh_vpn (uint32_t pteh)
00234 {
00235 return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
00236 }
00237
00238
00239 #define PTEL_V (1 << 8)
00240 #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
00241 #define PTEL_C (1 << 3)
00242 #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
00243 #define PTEL_D (1 << 2)
00244 #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
00245 #define PTEL_SH (1 << 1)
00246 #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
00247 #define PTEL_WT (1 << 0)
00248 #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
00249
00250 #define PTEL_SZ_HIGH_OFFSET (7)
00251 #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
00252 #define PTEL_SZ_LOW_OFFSET (4)
00253 #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
00254 static inline int cpu_ptel_sz (uint32_t ptel)
00255 {
00256 int sz;
00257 sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
00258 sz <<= 1;
00259 sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
00260 return sz;
00261 }
00262
00263 #define PTEL_PPN_BITS (19)
00264 #define PTEL_PPN_OFFSET (10)
00265 #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
00266 #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
00267 static inline int cpu_ptel_ppn (uint32_t ptel)
00268 {
00269 return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
00270 }
00271
00272 #define PTEL_PR_BITS (2)
00273 #define PTEL_PR_OFFSET (5)
00274 #define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
00275 #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
00276 static inline int cpu_ptel_pr (uint32_t ptel)
00277 {
00278 return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
00279 }
00280
00281
00282 #define PTEA_SA_BITS (3)
00283 #define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
00284 #define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
00285 #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
00286 #define PTEA_TC (1 << 3)
00287 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
00288
00289 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
00290 {
00291 env->pc = tb->pc;
00292 env->flags = tb->flags;
00293 }
00294
00295 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
00296 target_ulong *cs_base, int *flags)
00297 {
00298 *pc = env->pc;
00299 *cs_base = 0;
00300 *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
00301 | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME))
00302 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))
00303 | (env->sr & (SR_MD | SR_RB))
00304 | (env->sr & SR_FD);
00305 }
00306
00307 #endif