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00024 #define TCG_TARGET_SPARC 1
00025
00026 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
00027 #define TCG_TARGET_REG_BITS 64
00028 #else
00029 #define TCG_TARGET_REG_BITS 32
00030 #endif
00031
00032 #define TCG_TARGET_WORDS_BIGENDIAN
00033
00034 #define TCG_TARGET_NB_REGS 32
00035
00036 enum {
00037 TCG_REG_G0 = 0,
00038 TCG_REG_G1,
00039 TCG_REG_G2,
00040 TCG_REG_G3,
00041 TCG_REG_G4,
00042 TCG_REG_G5,
00043 TCG_REG_G6,
00044 TCG_REG_G7,
00045 TCG_REG_O0,
00046 TCG_REG_O1,
00047 TCG_REG_O2,
00048 TCG_REG_O3,
00049 TCG_REG_O4,
00050 TCG_REG_O5,
00051 TCG_REG_O6,
00052 TCG_REG_O7,
00053 TCG_REG_L0,
00054 TCG_REG_L1,
00055 TCG_REG_L2,
00056 TCG_REG_L3,
00057 TCG_REG_L4,
00058 TCG_REG_L5,
00059 TCG_REG_L6,
00060 TCG_REG_L7,
00061 TCG_REG_I0,
00062 TCG_REG_I1,
00063 TCG_REG_I2,
00064 TCG_REG_I3,
00065 TCG_REG_I4,
00066 TCG_REG_I5,
00067 TCG_REG_I6,
00068 TCG_REG_I7,
00069 };
00070
00071 #define TCG_CT_CONST_S11 0x100
00072 #define TCG_CT_CONST_S13 0x200
00073
00074
00075 #define TCG_REG_CALL_STACK TCG_REG_I6
00076 #ifdef __arch64__
00077
00078 #define TCG_TARGET_STACK_MINFRAME (176 + 2 * (int)sizeof(long))
00079 #define TCG_TARGET_CALL_STACK_OFFSET (2047 + TCG_TARGET_STACK_MINFRAME)
00080 #define TCG_TARGET_STACK_ALIGN 16
00081 #else
00082
00083 #define TCG_TARGET_STACK_MINFRAME (92 + (2 + 1) * (int)sizeof(long))
00084 #define TCG_TARGET_CALL_STACK_OFFSET TCG_TARGET_STACK_MINFRAME
00085 #define TCG_TARGET_STACK_ALIGN 8
00086 #endif
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096 #ifdef HOST_SOLARIS
00097 #define TCG_AREG0 TCG_REG_G2
00098 #define TCG_AREG1 TCG_REG_G3
00099 #define TCG_AREG2 TCG_REG_G4
00100 #define TCG_AREG3 TCG_REG_G5
00101 #define TCG_AREG4 TCG_REG_G6
00102 #elif defined(__sparc_v9__)
00103 #define TCG_AREG0 TCG_REG_G5
00104 #define TCG_AREG1 TCG_REG_G6
00105 #define TCG_AREG2 TCG_REG_G7
00106 #else
00107 #define TCG_AREG0 TCG_REG_G6
00108 #define TCG_AREG1 TCG_REG_G1
00109 #define TCG_AREG2 TCG_REG_G2
00110 #define TCG_AREG3 TCG_REG_G3
00111 #endif
00112
00113 static inline void flush_icache_range(unsigned long start, unsigned long stop)
00114 {
00115 unsigned long p;
00116
00117 p = start & ~(8UL - 1UL);
00118 stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
00119
00120 for (; p < stop; p += 8)
00121 __asm__ __volatile__("flush\t%0" : : "r" (p));
00122 }