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00013 #ifndef COMPONENTS_TRIG_NIC_H
00014 #define COMPONENTS_TRIG_NIC_H
00015
00016 #include <queue>
00017 #include <map>
00018
00019 #include "sst/elements/SS_router/SS_router/RtrIF.h"
00020 #include "sst/elements/portals4_sm/trig_cpu/portals_types.h"
00021 #include "trig_nic_event.h"
00022
00023 using namespace SST;
00024
00025 struct MessageStream {
00026 void* start;
00027 int current_offset;
00028 int remaining_length;
00029 ptl_handle_ct_t ct_handle;
00030 };
00031
00032 class trig_nic : public RtrIF {
00033
00034 private:
00035
00036 Link* cpu_link;
00037
00038 Link* self_link;
00039
00040
00041 Link* ptl_link;
00042 Link* dma_link;
00043
00044 int msg_latency;
00045 int ptl_latency;
00046 int ptl_msg_latency;
00047 int rtr_q_size;
00048 int rtr_q_max_size;
00049
00050 int timing_set;
00051 int latency_ct_post;
00052 int latency_ct_host_update;
00053 int ptl_unit_latency;
00054
00055 int additional_atomic_latency;
00056
00057
00058 #define MAX_PORTAL_TABLE_ENTRY 32
00059 ptl_entry_t* ptl_table[MAX_PORTAL_TABLE_ENTRY];
00060
00061 #define MAX_CT_EVENTS 32
00062 ptl_int_ct_t ptl_ct_events[MAX_CT_EVENTS];
00063
00064 std::queue<ptl_int_trig_op_t*> already_triggered_q;
00065
00066
00067
00068 std::queue<trig_nic_event*> pio_q;
00069 std::queue<trig_nic_event*> dma_q;
00070 std::queue<ptl_int_dma_t*> dma_req_q;
00071 std::queue<trig_nic_event*> dma_hdr_q;
00072
00073
00074
00075
00076
00077 int dma_q_max_size;
00078
00079 typedef union {
00080 int64_t int_val;
00081 double dbl_val;
00082 } atomic_cache_entry;
00083
00084 std::map<int,MessageStream*> streams;
00085 std::map<unsigned long,atomic_cache_entry*> atomic_cache;
00086
00087 ptl_int_dma_t* dma_req;
00088 bool dma_in_progress;
00089
00090 bool rr_dma;
00091 bool new_dma;
00092 bool send_recv;
00093
00094 bool send_atomic_from_cache;
00095
00096 public:
00097 trig_nic( ComponentId_t id, Params_t& params );
00098
00099 virtual int Finish() {
00100 return 0;
00101 }
00102
00103 virtual int Setup() {
00104 return 0;
00105 }
00106
00107 private:
00108
00109
00110 RtrEvent* nextToRtr;
00111
00112 bool clock_handler(Cycle_t cycle);
00113 void processCPUEvent( Event* e);
00114 void processPtlEvent( Event* e);
00115 void processDMAEvent( Event* e);
00116
00117 void setTimingParams(int set);
00118
00119 inline bool PtlCTCheckThresh(ptl_handle_ct_t ct_handle, ptl_size_t test) {
00120
00121 if ( test == 0 ) return true;
00122
00123 if ( (ptl_ct_events[ct_handle].ct_event.success +
00124 ptl_ct_events[ct_handle].ct_event.failure ) >= test ) {
00125
00126
00127
00128 return true;
00129 }
00130 return false;
00131
00132 }
00133
00134 void scheduleUpdateHostCT(ptl_handle_ct_t ct_handle);
00135 void scheduleCTInc(ptl_handle_ct_t ct_handle, SimTime_t delay);
00136
00137 double computeDoubleAtomic(unsigned long addr, double value, ptl_op_t op);
00138 int64_t computeIntAtomic(unsigned long addr, int64_t value, ptl_op_t op);
00139
00140 };
00141
00142 #endif