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00048 #ifndef __DECODER_H__
00049 #define __DECODER_H__
00050
00051 #include "area.h"
00052 #include "McPATcomponent.h"
00053 #include "parameter.h"
00054 #include <vector>
00055
00056 using namespace std;
00057
00058
00059 class Decoder : public McPATComponent
00060 {
00061 public:
00062 Decoder(
00063 int _num_dec_signals,
00064 bool flag_way_select,
00065 double _C_ld_dec_out,
00066 double _R_wire_dec_out,
00067 bool fully_assoc_,
00068 bool is_dram_,
00069 bool is_wl_tr_,
00070 const Area & cell_);
00071
00072 bool exist;
00073 int num_in_signals;
00074 double C_ld_dec_out;
00075 double R_wire_dec_out;
00076 int num_gates;
00077 int num_gates_min;
00078 double w_dec_n[MAX_NUMBER_GATES_STAGE];
00079 double w_dec_p[MAX_NUMBER_GATES_STAGE];
00080 double delay;
00081 powerDef power;
00082 bool fully_assoc;
00083 bool is_dram;
00084 bool is_wl_tr;
00085 const Area & cell;
00086
00087
00088 void compute_widths();
00089 void compute_area();
00090 double compute_delays(double inrisetime);
00091 };
00092
00093
00094
00095 class PredecBlk : public McPATComponent
00096 {
00097 public:
00098 PredecBlk(
00099 int num_dec_signals,
00100 Decoder * dec,
00101 double C_wire_predec_blk_out,
00102 double R_wire_predec_blk_out,
00103 int num_dec_per_predec,
00104 bool is_dram_,
00105 bool is_blk1);
00106
00107 Decoder * dec;
00108 bool exist;
00109 int number_input_addr_bits;
00110 double C_ld_predec_blk_out;
00111 double R_wire_predec_blk_out;
00112 int branch_effort_nand2_gate_output;
00113 int branch_effort_nand3_gate_output;
00114 bool flag_two_unique_paths;
00115 int flag_L2_gate;
00116 int number_inputs_L1_gate;
00117 int number_gates_L1_nand2_path;
00118 int number_gates_L1_nand3_path;
00119 int number_gates_L2;
00120 int min_number_gates_L1;
00121 int min_number_gates_L2;
00122 int num_L1_active_nand2_path;
00123 int num_L1_active_nand3_path;
00124 double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE];
00125 double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE];
00126 double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE];
00127 double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE];
00128 double w_L2_n[MAX_NUMBER_GATES_STAGE];
00129 double w_L2_p[MAX_NUMBER_GATES_STAGE];
00130 double delay_nand2_path;
00131 double delay_nand3_path;
00132 powerDef power_nand2_path;
00133 powerDef power_nand3_path;
00134 powerDef power_L2;
00135
00136 bool is_dram_;
00137
00138 void compute_widths();
00139 void compute_area();
00140 pair<double, double> compute_delays(pair<double, double> inrisetime);
00141
00142 };
00143
00144
00145 class PredecBlkDrv : public McPATComponent
00146 {
00147 public:
00148 PredecBlkDrv(
00149 int way_select,
00150 PredecBlk * blk_,
00151 bool is_dram);
00152
00153 int flag_driver_exists;
00154 int number_input_addr_bits;
00155 int number_gates_nand2_path;
00156 int number_gates_nand3_path;
00157 int min_number_gates;
00158 int num_buffers_driving_1_nand2_load;
00159 int num_buffers_driving_2_nand2_load;
00160 int num_buffers_driving_4_nand2_load;
00161 int num_buffers_driving_2_nand3_load;
00162 int num_buffers_driving_8_nand3_load;
00163 int num_buffers_nand3_path;
00164 double c_load_nand2_path_out;
00165 double c_load_nand3_path_out;
00166 double r_load_nand2_path_out;
00167 double r_load_nand3_path_out;
00168 double width_nand2_path_n[MAX_NUMBER_GATES_STAGE];
00169 double width_nand2_path_p[MAX_NUMBER_GATES_STAGE];
00170 double width_nand3_path_n[MAX_NUMBER_GATES_STAGE];
00171 double width_nand3_path_p[MAX_NUMBER_GATES_STAGE];
00172 double delay_nand2_path;
00173 double delay_nand3_path;
00174 powerDef power_nand2_path;
00175 powerDef power_nand3_path;
00176
00177 PredecBlk * blk;
00178 Decoder * dec;
00179 bool is_dram_;
00180 int way_select;
00181
00182 void compute_widths();
00183 void compute_area();
00184 pair<double, double> compute_delays(
00185 double inrisetime_nand2_path,
00186 double inrisetime_nand3_path);
00187
00188 inline int num_addr_bits_nand2_path()
00189 {
00190 return num_buffers_driving_1_nand2_load +
00191 num_buffers_driving_2_nand2_load +
00192 num_buffers_driving_4_nand2_load;
00193 }
00194 inline int num_addr_bits_nand3_path()
00195 {
00196 return num_buffers_driving_2_nand3_load +
00197 num_buffers_driving_8_nand3_load;
00198 }
00199 double get_rdOp_dynamic_E(int num_act_mats_hor_dir);
00200 };
00201
00202
00203
00204 class Predec : public McPATComponent
00205 {
00206 public:
00207 Predec(
00208 PredecBlkDrv * drv1,
00209 PredecBlkDrv * drv2);
00210
00211 double compute_delays(double inrisetime);
00212
00213 PredecBlk * blk1;
00214 PredecBlk * blk2;
00215 PredecBlkDrv * drv1;
00216 PredecBlkDrv * drv2;
00217
00218 powerDef block_power;
00219 powerDef driver_power;
00220
00221 private:
00222
00223 pair<double, double> get_max_delay_before_decoder(
00224 pair<double, double> input_pair1,
00225 pair<double, double> input_pair2);
00226 };
00227
00228
00229
00230 class Driver : public McPATComponent
00231 {
00232 public:
00233 Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram);
00234
00235 int number_gates;
00236 int min_number_gates;
00237 double width_n[MAX_NUMBER_GATES_STAGE];
00238 double width_p[MAX_NUMBER_GATES_STAGE];
00239 double c_gate_load;
00240 double c_wire_load;
00241 double r_wire_load;
00242 double delay;
00243 powerDef power;
00244 bool is_dram_;
00245
00246 void compute_widths();
00247 double compute_delay(double inrisetime);
00248 };
00249
00250
00251 #endif