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sst/core/techModels/libMcPATbeta06/basic_components.h

00001 /*****************************************************************************
00002  *                                McPAT
00003  *                      SOFTWARE LICENSE AGREEMENT
00004  *            Copyright 2009 Hewlett-Packard Development Company, L.P.
00005  *                          All Rights Reserved
00006  *
00007  * Permission to use, copy, and modify this software and its documentation is
00008  * hereby granted only under the following terms and conditions.  Both the
00009  * above copyright notice and this permission notice must appear in all copies
00010  * of the software, derivative works or modified versions, and any portions
00011  * thereof, and both notices must appear in supporting documentation.
00012  *
00013  * Any User of the software ("User"), by accessing and using it, agrees to the
00014  * terms and conditions set forth herein, and hereby grants back to Hewlett-
00015  * Packard Development Company, L.P. and its affiliated companies ("HP") a
00016  * non-exclusive, unrestricted, royalty-free right and license to copy,
00017  * modify, distribute copies, create derivate works and publicly display and
00018  * use, any changes, modifications, enhancements or extensions made to the
00019  * software by User, including but not limited to those affording
00020  * compatibility with other hardware or software, but excluding pre-existing
00021  * software applications that may incorporate the software.  User further
00022  * agrees to use its best efforts to inform HP of any such changes,
00023  * modifications, enhancements or extensions.
00024  *
00025  * Correspondence should be provided to HP at:
00026  *
00027  * Director of Intellectual Property Licensing
00028  * Office of Strategy and Technology
00029  * Hewlett-Packard Company
00030  * 1501 Page Mill Road
00031  * Palo Alto, California  94304
00032  *
00033  * The software may be further distributed by User (but not offered for
00034  * sale or transferred for compensation) to third parties, under the
00035  * condition that such third parties agree to abide by the terms and
00036  * conditions of this license.
00037  *
00038  * THE SOFTWARE IS PROVIDED "AS IS" WITH ANY AND ALL ERRORS AND DEFECTS
00039  * AND USER ACKNOWLEDGES THAT THE SOFTWARE MAY CONTAIN ERRORS AND DEFECTS.
00040  * HP DISCLAIMS ALL WARRANTIES WITH REGARD TO THE SOFTWARE, INCLUDING ALL
00041  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS.   IN NO EVENT SHALL
00042  * HP BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES
00043  * OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
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00045  * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE SOFTWARE.
00046  *
00047  ***************************************************************************/
00048 
00049 #ifndef BASIC_COMPONENTS_H_
00050 #define BASIC_COMPONENTS_H_
00051 
00052 #include "XML_Parse.h"
00053 #include "parameter.h"
00054 #include "array.h"
00055 #include <vector>
00056 
00057 typedef struct{
00058   //params
00059   ArrayST* caches;
00060   ArrayST* missb;
00061   ArrayST* ifb;
00062   ArrayST* prefetchb;
00063   ArrayST* wbb;
00064   uca_org_t result_caches, result_missb, result_ifb, result_prefetchb, result_wbb;
00065   //stats
00066   int total_accesses;
00067   int read_accesses;
00068   int write_accesses;
00069   int total_hits;
00070   int total_misses;
00071   int read_hits;
00072   int write_hits;
00073   int read_misses;
00074   int write_misses;
00075   int replacements;
00076   int write_backs;
00077   int miss_buffer_access;
00078   int fill_buffer_accesses;
00079   int prefetch_buffer_accesses;
00080   int prefetch_buffer_writes;
00081   int prefetch_buffer_reads;
00082   int prefetch_buffer_hits;
00083   int wbb_writes;
00084   int wbb_reads;
00085   powerDef tot_power, max_power;
00086   double area, maxPower, runtimeDynamicPower;
00087 } cache_processor;
00088 
00089 enum FU_type {
00090     FPU,
00091     ALU
00092 };
00093 
00094 enum Core_type {
00095         OOO,
00096         Inorder
00097 };
00098 
00099 enum Renaming_type {
00100     RAMbased,
00101         CAMbased
00102 };
00103 
00104 enum Scheduler_type {
00105     PhysicalRegFile,
00106         ReservationStation
00107 };
00108 
00109 enum cache_level{
00110     L2,
00111     L3,
00112     L1Directory,
00113     L2Directory
00114 };
00115 
00116 enum Dir_type{
00117         ST,
00118         DC,
00119         NonDir
00120 
00121 };
00122 class CoreDynParam {
00123 public:
00124         CoreDynParam(){};
00125         CoreDynParam(ParseXML *XML_interface, int ithCore_);
00126         //    :XML(XML_interface),
00127         //     ithCore(ithCore_)
00128         //     core_ty(inorder),
00129         //     rm_ty(CAMbased),
00130         //     scheu_ty(PhysicalRegFile),
00131         //     clockRate(1e9),//1GHz
00132         //     arch_ireg_width(32),
00133         //     arch_freg_width(32),
00134         //     phy_ireg_width(128),
00135         //     phy_freg_width(128),
00136         //     perThreadState(8),
00137         //     globalCheckpoint(32),
00138         //     instructionLength(32){};
00139         //ParseXML * XML;
00140     enum Core_type  core_ty;
00141         enum Renaming_type rm_ty;
00142     enum Scheduler_type scheu_ty;
00143     double clockRate,executionTime;
00144     int  arch_ireg_width, arch_freg_width, phy_ireg_width, phy_freg_width;
00145     int  num_IRF_entry, num_FRF_entry, num_ifreelist_entries, num_ffreelist_entries;
00146     int  fetchW, decodeW,issueW, commitW, predictionW, fp_issueW, fp_decodeW;
00147     int  perThreadState, globalCheckpoint, instruction_length, pc_width, opcode_length;
00148     int  num_hthreads, pipeline_stages;
00149     int  int_data_width, fp_data_width,v_address_width, p_address_width;
00150     bool regWindowing,multithreaded;
00151     ~CoreDynParam(){};
00152 };
00153 
00154 class CacheDynParam {
00155 public:
00156         CacheDynParam(){};
00157         CacheDynParam(ParseXML *XML_interface, int ithCache_);
00158     string name;
00159         enum Dir_type    dir_ty;
00160         double clockRate,executionTime;
00161     int    capacity, blockW, assoc, nbanks;
00162     double throughput, latency;
00163     int missb_size, fu_size, prefetchb_size, wbb_size;
00164     ~CacheDynParam(){};
00165 };
00166 
00167 class MCParam {
00168 public:
00169         MCParam(){};
00170         MCParam(ParseXML *XML_interface, int ithCache_);
00171     string name;
00172     double  clockRate;
00173     //  double mcTEPowerperGhz;
00174     //  double mcPHYperGbit;
00175     //  double area;
00176     int    llcBlockSize, dataBusWidth, addressBusWidth;
00177     int    opcodeW;
00178     int    peakDataTransferRate,memAccesses, llcBlocksize; //e.g 800M for DDR2-800M
00179     int    memRank,num_channels;
00180     double executionTime, reads, writes;
00181 
00182     ~MCParam(){};
00183 };
00184 
00185 class NoCParam {
00186 public:
00187         NoCParam(){};
00188         NoCParam(ParseXML *XML_interface, int ithCache_);
00189     string name;
00190     double  clockRate;
00191     int    flit_size, input_ports, output_ports, virtual_channel_per_port,input_buffer_entries_per_vc;
00192     int    horizontal_nodes,vertical_nodes, total_nodes;
00193     double executionTime, total_access, link_throughput,link_latency;
00194     bool   has_global_link;
00195 
00196     ~NoCParam(){};
00197 };
00198 
00199 class ProcParam {
00200 public:
00201         ProcParam(){};
00202         ProcParam(ParseXML *XML_interface, int ithCache_);
00203     string name;
00204     int  numCore, numL2, numL3, numNOC, numL1Dir, numL2Dir;
00205     bool homoCore, homoL2, homoL3, homoNOC, homoL1Dir, homoL2Dir;
00206 
00207     ~ProcParam(){};
00208 };
00209 
00210 #endif /* BASIC_COMPONENTS_H_ */

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