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00049 #ifndef __TIME_H__
00050 #define __TIME_H__
00051
00052 #include "area.h"
00053
00054 typedef struct {
00055 int subbanks;
00056 double access_time,cycle_time;
00057 double senseext_scale;
00058 powerDef total_power;
00059 int best_Ndwl,best_Ndbl, best_data_deg_bitline_muxing;
00060 int best_Ndsam_lev_1, best_Ndsam_lev_2;
00061 double max_leakage_power, max_access_time, max_cycle_time, max_dynamic_power, max_dynamic_energy;
00062 double min_leakage_power, min_access_time, min_cycle_time, min_dynamic_power, min_dynamic_energy;
00063 double best_Nspd;
00064 int best_Ntwl,best_Ntbl, best_tag_deg_bitline_muxing;
00065 int best_Ntsam_lev_1, best_Ntsam_lev_2;
00066 double best_Ntspd;
00067 int best_muxover;
00068 powerDef total_routing_power;
00069 powerDef total_power_without_routing, total_power_allbanks;
00070 double subbank_address_routing_delay;
00071 powerDef subbank_address_routing_power;
00072 double decoder_delay_data,decoder_delay_tag;
00073 powerDef decoder_power_data,decoder_power_tag;
00074 double dec_data_driver,dec_data_3to8,dec_data_inv;
00075 double dec_tag_driver,dec_tag_3to8,dec_tag_inv;
00076 double wordline_delay_data,wordline_delay_tag;
00077 powerDef wordline_power_data,wordline_power_tag;
00078 double bitline_delay_data,bitline_delay_tag;
00079 powerDef bitline_power_data,bitline_power_tag;
00080 double sense_amp_delay_data,sense_amp_delay_tag;
00081 powerDef sense_amp_power_data,sense_amp_power_tag;
00082 double total_out_driver_delay_data;
00083 powerDef total_out_driver_power_data;
00084 double compare_part_delay;
00085 double drive_mux_delay;
00086 double selb_delay;
00087 powerDef compare_part_power, drive_mux_power, selb_power;
00088 double data_output_delay;
00089 powerDef data_output_power;
00090 double drive_valid_delay;
00091 powerDef drive_valid_power;
00092 double precharge_delay;
00093 int data_nor_inputs;
00094 int tag_nor_inputs;
00095 } result_type;
00096
00097
00098 struct mem_array
00099 {
00100 int Ndwl;
00101 int Ndbl;
00102 double Nspd;
00103 int deg_bitline_muxing;
00104 int Ndsam_lev_1;
00105 int Ndsam_lev_2;
00106 double access_time;
00107 double cycle_time;
00108 double multisubbank_interleave_cycle_time;
00109 double area_ram_cells;
00110 double area;
00111 powerDef power;
00112 double delay_senseamp_mux_decoder;
00113 double delay_before_subarray_output_driver;
00114 double delay_from_subarray_output_driver_to_output;
00115 double height;
00116 double width;
00117
00118 static bool lt(const mem_array * m1, const mem_array * m2)
00119 {
00120 if (m1->Nspd < m2->Nspd) return true;
00121 else if (m1->Nspd > m2->Nspd) return false;
00122 else if (m1->Ndwl < m2->Ndwl) return true;
00123 else if (m1->Ndwl > m2->Ndwl) return false;
00124 else if (m1->Ndbl < m2->Ndbl) return true;
00125 else if (m1->Ndbl > m2->Ndbl) return false;
00126 else if (m1->deg_bitline_muxing < m2->deg_bitline_muxing) return true;
00127 else if (m1->deg_bitline_muxing > m2->deg_bitline_muxing) return false;
00128 else if (m1->Ndsam_lev_1 < m2->Ndsam_lev_1) return true;
00129 else if (m1->Ndsam_lev_1 > m2->Ndsam_lev_1) return false;
00130 else if (m1->Ndsam_lev_2 < m2->Ndsam_lev_2) return true;
00131 else return false;
00132 }
00133
00134 };
00135
00136
00137 typedef struct {
00138 int tag_array_index;
00139 int data_array_index;
00140 list<mem_array *>::iterator tag_array_iter;
00141 list<mem_array *>::iterator data_array_iter;
00142 double access_time;
00143 double cycle_time;
00144 double area;
00145 double efficiency;
00146 powerDef total_power;
00147 } solution;
00148
00149
00150 bool calculate_time(
00151 bool is_tag,
00152 int pure_ram,
00153 double Nspd,
00154 unsigned int Ndwl,
00155 unsigned int Ndbl,
00156 unsigned int Ndcm,
00157 unsigned int Ndsam_lev_1,
00158 unsigned int Ndsam_lev_2,
00159 mem_array *ptr_array,
00160 int flag_results_populate,
00161 results_mem_array *ptr_results,
00162 final_results *ptr_fin_res,
00163 const ArrayEdgeToBankEdgeHtreeSizing & arr_edge_to_bank_edge_htree_sizing,
00164 const BankHtreeSizing & bank_htree_sizing,
00165 bool is_main_mem);
00166
00167
00168 void do_it(final_results *fin_res);
00169 void init_tech_params(double tech, bool is_tag);
00170
00171
00172 struct calc_time_mt_wrapper_struct
00173 {
00174 uint32_t tid;
00175 bool is_tag;
00176 bool pure_ram;
00177 bool is_main_mem;
00178 double Nspd_min;
00179
00180 list<mem_array *> data_arr;
00181 list<mem_array *> tag_arr;
00182 const ArrayEdgeToBankEdgeHtreeSizing * ptr_arr_edge_to_bank_edge_htree_sizing;
00183 const BankHtreeSizing * ptr_bank_htree_sizing;
00184 };
00185
00186 void *calc_time_mt_wrapper(void * void_obj);
00187
00188 #endif