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00020 #include "config.h"
00021 #include "dyngen-exec.h"
00022
00023
00024 #ifdef TARGET_X86_64
00025 #define TARGET_LONG_BITS 64
00026 #else
00027 #define TARGET_LONG_BITS 32
00028 #endif
00029
00030 #include "cpu-defs.h"
00031
00032 register struct CPUX86State *env asm(AREG0);
00033
00034 #include "qemu-common.h"
00035 #include "qemu-log.h"
00036
00037 #define EAX (env->regs[R_EAX])
00038 #define ECX (env->regs[R_ECX])
00039 #define EDX (env->regs[R_EDX])
00040 #define EBX (env->regs[R_EBX])
00041 #define ESP (env->regs[R_ESP])
00042 #define EBP (env->regs[R_EBP])
00043 #define ESI (env->regs[R_ESI])
00044 #define EDI (env->regs[R_EDI])
00045 #define EIP (env->eip)
00046 #define DF (env->df)
00047
00048 #define CC_SRC (env->cc_src)
00049 #define CC_DST (env->cc_dst)
00050 #define CC_OP (env->cc_op)
00051
00052
00053 #define FT0 (env->ft0)
00054 #define ST0 (env->fpregs[env->fpstt].d)
00055 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
00056 #define ST1 ST(1)
00057
00058 #include "cpu.h"
00059 #include "exec-all.h"
00060
00061
00062 void do_interrupt(int intno, int is_int, int error_code,
00063 target_ulong next_eip, int is_hw);
00064 void do_interrupt_user(int intno, int is_int, int error_code,
00065 target_ulong next_eip);
00066 void QEMU_NORETURN raise_exception_err(int exception_index, int error_code);
00067 void QEMU_NORETURN raise_exception(int exception_index);
00068 void do_smm_enter(void);
00069
00070
00071 static inline target_long lshift(target_long x, int n)
00072 {
00073 if (n >= 0)
00074 return x << n;
00075 else
00076 return x >> (-n);
00077 }
00078
00079 #include "helper.h"
00080
00081 static inline void svm_check_intercept(uint32_t type)
00082 {
00083 helper_svm_check_intercept_param(type, 0);
00084 }
00085
00086 #if !defined(CONFIG_USER_ONLY)
00087
00088 #include "softmmu_exec.h"
00089
00090 #endif
00091
00092 #ifdef USE_X86LDOUBLE
00093
00094 #define floatx_to_int32 floatx80_to_int32
00095 #define floatx_to_int64 floatx80_to_int64
00096 #define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
00097 #define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
00098 #define int32_to_floatx int32_to_floatx80
00099 #define int64_to_floatx int64_to_floatx80
00100 #define float32_to_floatx float32_to_floatx80
00101 #define float64_to_floatx float64_to_floatx80
00102 #define floatx_to_float32 floatx80_to_float32
00103 #define floatx_to_float64 floatx80_to_float64
00104 #define floatx_abs floatx80_abs
00105 #define floatx_chs floatx80_chs
00106 #define floatx_round_to_int floatx80_round_to_int
00107 #define floatx_compare floatx80_compare
00108 #define floatx_compare_quiet floatx80_compare_quiet
00109 #else
00110 #define floatx_to_int32 float64_to_int32
00111 #define floatx_to_int64 float64_to_int64
00112 #define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
00113 #define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
00114 #define int32_to_floatx int32_to_float64
00115 #define int64_to_floatx int64_to_float64
00116 #define float32_to_floatx float32_to_float64
00117 #define float64_to_floatx(x, e) (x)
00118 #define floatx_to_float32 float64_to_float32
00119 #define floatx_to_float64(x, e) (x)
00120 #define floatx_abs float64_abs
00121 #define floatx_chs float64_chs
00122 #define floatx_round_to_int float64_round_to_int
00123 #define floatx_compare float64_compare
00124 #define floatx_compare_quiet float64_compare_quiet
00125 #endif
00126
00127 #define RC_MASK 0xc00
00128 #define RC_NEAR 0x000
00129 #define RC_DOWN 0x400
00130 #define RC_UP 0x800
00131 #define RC_CHOP 0xc00
00132
00133 #define MAXTAN 9223372036854775808.0
00134
00135 #ifdef USE_X86LDOUBLE
00136
00137
00138 typedef union {
00139 long double d;
00140 struct {
00141 unsigned long long lower;
00142 unsigned short upper;
00143 } l;
00144 } CPU86_LDoubleU;
00145
00146
00147 #define MAXEXPD 0x7fff
00148 #define EXPBIAS 16383
00149 #define EXPD(fp) (fp.l.upper & 0x7fff)
00150 #define SIGND(fp) ((fp.l.upper) & 0x8000)
00151 #define MANTD(fp) (fp.l.lower)
00152 #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
00153
00154 #else
00155
00156
00157 typedef union {
00158 double d;
00159 #if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
00160 struct {
00161 uint32_t lower;
00162 int32_t upper;
00163 } l;
00164 #else
00165 struct {
00166 int32_t upper;
00167 uint32_t lower;
00168 } l;
00169 #endif
00170 #ifndef __arm__
00171 int64_t ll;
00172 #endif
00173 } CPU86_LDoubleU;
00174
00175
00176 #define MAXEXPD 0x7ff
00177 #define EXPBIAS 1023
00178 #define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF)
00179 #define SIGND(fp) ((fp.l.upper) & 0x80000000)
00180 #ifdef __arm__
00181 #define MANTD(fp) (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32))
00182 #else
00183 #define MANTD(fp) (fp.ll & ((1LL << 52) - 1))
00184 #endif
00185 #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20)
00186 #endif
00187
00188 static inline void fpush(void)
00189 {
00190 env->fpstt = (env->fpstt - 1) & 7;
00191 env->fptags[env->fpstt] = 0;
00192 }
00193
00194 static inline void fpop(void)
00195 {
00196 env->fptags[env->fpstt] = 1;
00197 env->fpstt = (env->fpstt + 1) & 7;
00198 }
00199
00200 #ifndef USE_X86LDOUBLE
00201 static inline CPU86_LDouble helper_fldt(target_ulong ptr)
00202 {
00203 CPU86_LDoubleU temp;
00204 int upper, e;
00205 uint64_t ll;
00206
00207
00208 upper = lduw(ptr + 8);
00209
00210 e = (upper & 0x7fff) - 16383 + EXPBIAS;
00211 e |= (upper >> 4) & 0x800;
00212 ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1);
00213 #ifdef __arm__
00214 temp.l.upper = (e << 20) | (ll >> 32);
00215 temp.l.lower = ll;
00216 #else
00217 temp.ll = ll | ((uint64_t)e << 52);
00218 #endif
00219 return temp.d;
00220 }
00221
00222 static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
00223 {
00224 CPU86_LDoubleU temp;
00225 int e;
00226
00227 temp.d = f;
00228
00229 stq(ptr, (MANTD(temp) << 11) | (1LL << 63));
00230
00231 e = EXPD(temp) - EXPBIAS + 16383;
00232 e |= SIGND(temp) >> 16;
00233 stw(ptr + 8, e);
00234 }
00235 #else
00236
00237
00238
00239 static inline CPU86_LDouble helper_fldt(target_ulong ptr)
00240 {
00241 CPU86_LDoubleU temp;
00242
00243 temp.l.lower = ldq(ptr);
00244 temp.l.upper = lduw(ptr + 8);
00245 return temp.d;
00246 }
00247
00248 static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
00249 {
00250 CPU86_LDoubleU temp;
00251
00252 temp.d = f;
00253 stq(ptr, temp.l.lower);
00254 stw(ptr + 8, temp.l.upper);
00255 }
00256
00257 #endif
00258
00259 #define FPUS_IE (1 << 0)
00260 #define FPUS_DE (1 << 1)
00261 #define FPUS_ZE (1 << 2)
00262 #define FPUS_OE (1 << 3)
00263 #define FPUS_UE (1 << 4)
00264 #define FPUS_PE (1 << 5)
00265 #define FPUS_SF (1 << 6)
00266 #define FPUS_SE (1 << 7)
00267 #define FPUS_B (1 << 15)
00268
00269 #define FPUC_EM 0x3f
00270
00271 static inline uint32_t compute_eflags(void)
00272 {
00273 return env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
00274 }
00275
00276
00277 static inline void load_eflags(int eflags, int update_mask)
00278 {
00279 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
00280 DF = 1 - (2 * ((eflags >> 10) & 1));
00281 env->eflags = (env->eflags & ~update_mask) |
00282 (eflags & update_mask) | 0x2;
00283 }
00284
00285 static inline void env_to_regs(void)
00286 {
00287 #ifdef reg_EAX
00288 EAX = env->regs[R_EAX];
00289 #endif
00290 #ifdef reg_ECX
00291 ECX = env->regs[R_ECX];
00292 #endif
00293 #ifdef reg_EDX
00294 EDX = env->regs[R_EDX];
00295 #endif
00296 #ifdef reg_EBX
00297 EBX = env->regs[R_EBX];
00298 #endif
00299 #ifdef reg_ESP
00300 ESP = env->regs[R_ESP];
00301 #endif
00302 #ifdef reg_EBP
00303 EBP = env->regs[R_EBP];
00304 #endif
00305 #ifdef reg_ESI
00306 ESI = env->regs[R_ESI];
00307 #endif
00308 #ifdef reg_EDI
00309 EDI = env->regs[R_EDI];
00310 #endif
00311 }
00312
00313 static inline void regs_to_env(void)
00314 {
00315 #ifdef reg_EAX
00316 env->regs[R_EAX] = EAX;
00317 #endif
00318 #ifdef reg_ECX
00319 env->regs[R_ECX] = ECX;
00320 #endif
00321 #ifdef reg_EDX
00322 env->regs[R_EDX] = EDX;
00323 #endif
00324 #ifdef reg_EBX
00325 env->regs[R_EBX] = EBX;
00326 #endif
00327 #ifdef reg_ESP
00328 env->regs[R_ESP] = ESP;
00329 #endif
00330 #ifdef reg_EBP
00331 env->regs[R_EBP] = EBP;
00332 #endif
00333 #ifdef reg_ESI
00334 env->regs[R_ESI] = ESI;
00335 #endif
00336 #ifdef reg_EDI
00337 env->regs[R_EDI] = EDI;
00338 #endif
00339 }
00340
00341 static inline int cpu_halted(CPUState *env) {
00342
00343 if (!env->halted)
00344 return 0;
00345
00346 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
00347 (env->eflags & IF_MASK)) ||
00348 (env->interrupt_request & CPU_INTERRUPT_NMI)) {
00349 env->halted = 0;
00350 return 0;
00351 }
00352 return EXCP_HALTED;
00353 }
00354
00355
00356
00357 static inline void cpu_load_efer(CPUState *env, uint64_t val)
00358 {
00359 env->efer = val;
00360 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
00361 if (env->efer & MSR_EFER_LMA)
00362 env->hflags |= HF_LMA_MASK;
00363 if (env->efer & MSR_EFER_SVME)
00364 env->hflags |= HF_SVME_MASK;
00365 }