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sst/core/techModels/libMcPATbeta/cacti_interface.h

00001 /*------------------------------------------------------------
00002  *                              CACTI 6.5
00003  *         Copyright 2008 Hewlett-Packard Development Corporation
00004  *                         All Rights Reserved
00005  *
00006  * Permission to use, copy, and modify this software and its documentation is
00007  * hereby granted only under the following terms and conditions.  Both the
00008  * above copyright notice and this permission notice must appear in all copies
00009  * of the software, derivative works or modified versions, and any portions
00010  * thereof, and both notices must appear in supporting documentation.
00011  *
00012  * Users of this software agree to the terms and conditions set forth herein, and
00013  * hereby grant back to Hewlett-Packard Company and its affiliated companies ("HP")
00014  * a non-exclusive, unrestricted, royalty-free right and license under any changes,
00015  * enhancements or extensions  made to the core functions of the software, including
00016  * but not limited to those affording compatibility with other hardware or software
00017  * environments, but excluding applications which incorporate this software.
00018  * Users further agree to use their best efforts to return to HP any such changes,
00019  * enhancements or extensions that they make and inform HP of noteworthy uses of
00020  * this software.  Correspondence should be provided to HP at:
00021  *
00022  *                       Director of Intellectual Property Licensing
00023  *                       Office of Strategy and Technology
00024  *                       Hewlett-Packard Company
00025  *                       1501 Page Mill Road
00026  *                       Palo Alto, California  94304
00027  *
00028  * This software may be distributed (but not offered for sale or transferred
00029  * for compensation) to third parties, provided such third parties agree to
00030  * abide by the terms and conditions of this notice.
00031  *
00032  * THE SOFTWARE IS PROVIDED "AS IS" AND HP DISCLAIMS ALL
00033  * WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
00034  * OF MERCHANTABILITY AND FITNESS.   IN NO EVENT SHALL HP
00035  * CORPORATION BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
00036  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
00037  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS
00038  * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
00039  * SOFTWARE.
00040  *------------------------------------------------------------*/
00041 
00042 
00043 
00044 #ifndef __CACTI_INTERFACE_H__
00045 #define __CACTI_INTERFACE_H__
00046 
00047 #include <map>
00048 #include <string>
00049 #include <vector>
00050 #include <list>
00051 #include <iostream>
00052 #include "const.h"
00053 
00054 using namespace std;
00055 
00056 
00057 class min_values_t;
00058 class mem_array;
00059 class uca_org_t;
00060 
00061 
00062 class powerComponents
00063 {
00064   public:
00065     double dynamic;
00066     double leakage;
00067     double gate_leakage;
00068     double short_circuit;
00069     double longer_channel_leakage;
00070 
00071     powerComponents() : dynamic(0), leakage(0), gate_leakage(0), short_circuit(0), longer_channel_leakage(0)  { }
00072     powerComponents(const powerComponents & obj) { *this = obj; }
00073     powerComponents & operator=(const powerComponents & rhs)
00074     {
00075       dynamic = rhs.dynamic;
00076       leakage = rhs.leakage;
00077       gate_leakage  = rhs.gate_leakage;
00078       short_circuit = rhs.short_circuit;
00079       longer_channel_leakage = rhs.longer_channel_leakage;
00080       return *this;
00081     }
00082     void reset() { dynamic = 0; leakage = 0; gate_leakage = 0; short_circuit = 0;longer_channel_leakage = 0;}
00083 
00084     friend powerComponents operator+(const powerComponents & x, const powerComponents & y);
00085     friend powerComponents operator*(const powerComponents & x, double const * const y);
00086 };
00087 
00088 
00089 
00090 class powerDef
00091 {
00092   public:
00093     powerComponents readOp;
00094     powerComponents writeOp;
00095     powerComponents searchOp;//Sheng: for CAM and FA
00096 
00097     powerDef() : readOp(), writeOp(), searchOp() { }
00098     void reset() { readOp.reset(); writeOp.reset(); searchOp.reset();}
00099 
00100     friend powerDef operator+(const powerDef & x, const powerDef & y);
00101     friend powerDef operator*(const powerDef & x, double const * const y);
00102 };
00103 
00104 enum Wire_type
00105 {
00106     Global /* gloabl wires with repeaters */,
00107     Global_5 /* 5% delay penalty */,
00108     Global_10 /* 10% delay penalty */,
00109     Global_20 /* 20% delay penalty */,
00110     Global_30 /* 30% delay penalty */,
00111     Low_swing /* differential low power wires with high area overhead */,
00112     Semi_global /* mid-level wires with repeaters*/,
00113     Transmission /* tranmission lines with high area overhead */,
00114     Optical /* optical wires */,
00115     Invalid_wtype
00116 };
00117 
00118 
00119 
00120 class InputParameter
00121 {
00122   public:
00123     void parse_cfg(const string & infile);
00124 
00125     bool error_checking();  // return false if the input parameters are problematic
00126     void display_ip();
00127 
00128     unsigned int cache_sz;  // in bytes
00129     unsigned int line_sz;
00130     unsigned int assoc;
00131     unsigned int nbanks;
00132     unsigned int out_w;// == nr_bits_out
00133     bool     specific_tag;
00134     unsigned int tag_w;
00135     unsigned int access_mode;
00136     unsigned int obj_func_dyn_energy;
00137     unsigned int obj_func_dyn_power;
00138     unsigned int obj_func_leak_power;
00139     unsigned int obj_func_cycle_t;
00140 
00141     double   F_sz_nm;          // feature size in nm
00142     double   F_sz_um;          // feature size in um
00143     unsigned int num_rw_ports;
00144     unsigned int num_rd_ports;
00145     unsigned int num_wr_ports;
00146     unsigned int num_se_rd_ports;  // number of single ended read ports
00147     unsigned int num_search_ports;  // Sheng: number of search ports for CAM
00148     bool     is_main_mem;
00149     bool     is_cache;
00150     bool     pure_ram;
00151     bool     pure_cam;
00152     bool     rpters_in_htree;  // if there are repeaters in htree segment
00153     unsigned int ver_htree_wires_over_array;
00154     unsigned int broadcast_addr_din_over_ver_htrees;
00155     unsigned int temp;
00156 
00157     unsigned int ram_cell_tech_type;
00158     unsigned int peri_global_tech_type;
00159     unsigned int data_arr_ram_cell_tech_type;
00160     unsigned int data_arr_peri_global_tech_type;
00161     unsigned int tag_arr_ram_cell_tech_type;
00162     unsigned int tag_arr_peri_global_tech_type;
00163 
00164     unsigned int burst_len;
00165     unsigned int int_prefetch_w;
00166     unsigned int page_sz_bits;
00167 
00168     unsigned int ic_proj_type;      // interconnect_projection_type
00169     unsigned int wire_is_mat_type;  // wire_inside_mat_type
00170     unsigned int wire_os_mat_type; // wire_outside_mat_type
00171     enum Wire_type wt;
00172     int force_wiretype;
00173     bool print_input_args;
00174     unsigned int nuca_cache_sz; // TODO
00175     int ndbl, ndwl, nspd, ndsam1, ndsam2, ndcm;
00176     bool force_cache_config;
00177 
00178     int cache_level;
00179     int cores;
00180     int nuca_bank_count;
00181     int force_nuca_bank;
00182 
00183     int delay_wt, dynamic_power_wt, leakage_power_wt,
00184         cycle_time_wt, area_wt;
00185     int delay_wt_nuca, dynamic_power_wt_nuca, leakage_power_wt_nuca,
00186         cycle_time_wt_nuca, area_wt_nuca;
00187 
00188     int delay_dev, dynamic_power_dev, leakage_power_dev,
00189         cycle_time_dev, area_dev;
00190     int delay_dev_nuca, dynamic_power_dev_nuca, leakage_power_dev_nuca,
00191         cycle_time_dev_nuca, area_dev_nuca;
00192     int ed; //ED or ED2 optimization
00193     int nuca;
00194 
00195     bool     fast_access;
00196     unsigned int block_sz;  // bytes
00197     unsigned int tag_assoc;
00198     unsigned int data_assoc;
00199     bool     is_seq_acc;
00200     bool     fully_assoc;
00201     unsigned int nsets;  // == number_of_sets
00202     int print_detail;
00203 
00204 
00205     bool     add_ecc_b_;
00206   //parameters for design constraint
00207   double throughput;
00208   double latency;
00209   bool pipelinable;
00210   int pipeline_stages;
00211   int per_stage_vector;
00212   bool with_clock_grid;
00213   /* ----- SoM ----- */
00214   bool opt_for_clk;
00215   // For smaller array structures, McPAT (Cacti) fails modeling.
00216   // We use emperical data to scale the array size.
00217   double size_scaling;
00218   /* ----- EoM ----- */
00219 };
00220 
00221 
00222 typedef struct{
00223   int Ndwl;
00224   int Ndbl;
00225   double Nspd;
00226   int deg_bl_muxing;
00227   int Ndsam_lev_1;
00228   int Ndsam_lev_2;
00229   int number_activated_mats_horizontal_direction;
00230   int number_subbanks;
00231   int page_size_in_bits;
00232   double delay_route_to_bank;
00233   double delay_crossbar;
00234   double delay_addr_din_horizontal_htree;
00235   double delay_addr_din_vertical_htree;
00236   double delay_row_predecode_driver_and_block;
00237   double delay_row_decoder;
00238   double delay_bitlines;
00239   double delay_sense_amp;
00240   double delay_subarray_output_driver;
00241   double delay_bit_mux_predecode_driver_and_block;
00242   double delay_bit_mux_decoder;
00243   double delay_senseamp_mux_lev_1_predecode_driver_and_block;
00244   double delay_senseamp_mux_lev_1_decoder;
00245   double delay_senseamp_mux_lev_2_predecode_driver_and_block;
00246   double delay_senseamp_mux_lev_2_decoder;
00247   double delay_input_htree;
00248   double delay_output_htree;
00249   double delay_dout_vertical_htree;
00250   double delay_dout_horizontal_htree;
00251   double delay_comparator;
00252   double access_time;
00253   double cycle_time;
00254   double multisubbank_interleave_cycle_time;
00255   double delay_request_network;
00256   double delay_inside_mat;
00257   double delay_reply_network;
00258   double trcd;
00259   double cas_latency;
00260   double precharge_delay;
00261   powerDef power_routing_to_bank;
00262   powerDef power_addr_input_htree;
00263   powerDef power_data_input_htree;
00264   powerDef power_data_output_htree;
00265   powerDef power_addr_horizontal_htree;
00266   powerDef power_datain_horizontal_htree;
00267   powerDef power_dataout_horizontal_htree;
00268   powerDef power_addr_vertical_htree;
00269   powerDef power_datain_vertical_htree;
00270   powerDef power_row_predecoder_drivers;
00271   powerDef power_row_predecoder_blocks;
00272   powerDef power_row_decoders;
00273   powerDef power_bit_mux_predecoder_drivers;
00274   powerDef power_bit_mux_predecoder_blocks;
00275   powerDef power_bit_mux_decoders;
00276   powerDef power_senseamp_mux_lev_1_predecoder_drivers;
00277   powerDef power_senseamp_mux_lev_1_predecoder_blocks;
00278   powerDef power_senseamp_mux_lev_1_decoders;
00279   powerDef power_senseamp_mux_lev_2_predecoder_drivers;
00280   powerDef power_senseamp_mux_lev_2_predecoder_blocks;
00281   powerDef power_senseamp_mux_lev_2_decoders;
00282   powerDef power_bitlines;
00283   powerDef power_sense_amps;
00284   powerDef power_prechg_eq_drivers;
00285   powerDef power_output_drivers_at_subarray;
00286   powerDef power_dataout_vertical_htree;
00287   powerDef power_comparators;
00288   powerDef power_crossbar;
00289   powerDef total_power;
00290   double area;
00291   double all_banks_height;
00292   double all_banks_width;
00293   double bank_height;
00294   double bank_width;
00295   double subarray_memory_cell_area_height;
00296   double subarray_memory_cell_area_width;
00297   double mat_height;
00298   double mat_width;
00299   double routing_area_height_within_bank;
00300   double routing_area_width_within_bank;
00301   double area_efficiency;
00302 //  double perc_power_dyn_routing_to_bank;
00303 //  double perc_power_dyn_addr_horizontal_htree;
00304 //  double perc_power_dyn_datain_horizontal_htree;
00305 //  double perc_power_dyn_dataout_horizontal_htree;
00306 //  double perc_power_dyn_addr_vertical_htree;
00307 //  double perc_power_dyn_datain_vertical_htree;
00308 //  double perc_power_dyn_row_predecoder_drivers;
00309 //  double perc_power_dyn_row_predecoder_blocks;
00310 //  double perc_power_dyn_row_decoders;
00311 //  double perc_power_dyn_bit_mux_predecoder_drivers;
00312 //  double perc_power_dyn_bit_mux_predecoder_blocks;
00313 //  double perc_power_dyn_bit_mux_decoders;
00314 //  double perc_power_dyn_senseamp_mux_lev_1_predecoder_drivers;
00315 //  double perc_power_dyn_senseamp_mux_lev_1_predecoder_blocks;
00316 //  double perc_power_dyn_senseamp_mux_lev_1_decoders;
00317 //  double perc_power_dyn_senseamp_mux_lev_2_predecoder_drivers;
00318 //  double perc_power_dyn_senseamp_mux_lev_2_predecoder_blocks;
00319 //  double perc_power_dyn_senseamp_mux_lev_2_decoders;
00320 //  double perc_power_dyn_bitlines;
00321 //  double perc_power_dyn_sense_amps;
00322 //  double perc_power_dyn_prechg_eq_drivers;
00323 //  double perc_power_dyn_subarray_output_drivers;
00324 //  double perc_power_dyn_dataout_vertical_htree;
00325 //  double perc_power_dyn_comparators;
00326 //  double perc_power_dyn_crossbar;
00327 //  double perc_power_dyn_spent_outside_mats;
00328 //  double perc_power_leak_routing_to_bank;
00329 //  double perc_power_leak_addr_horizontal_htree;
00330 //  double perc_power_leak_datain_horizontal_htree;
00331 //  double perc_power_leak_dataout_horizontal_htree;
00332 //  double perc_power_leak_addr_vertical_htree;
00333 //  double perc_power_leak_datain_vertical_htree;
00334 //  double perc_power_leak_row_predecoder_drivers;
00335 //  double perc_power_leak_row_predecoder_blocks;
00336 //  double perc_power_leak_row_decoders;
00337 //  double perc_power_leak_bit_mux_predecoder_drivers;
00338 //  double perc_power_leak_bit_mux_predecoder_blocks;
00339 //  double perc_power_leak_bit_mux_decoders;
00340 //  double perc_power_leak_senseamp_mux_lev_1_predecoder_drivers;
00341 //  double perc_power_leak_senseamp_mux_lev_1_predecoder_blocks;
00342 //  double perc_power_leak_senseamp_mux_lev_1_decoders;
00343 //  double perc_power_leak_senseamp_mux_lev_2_predecoder_drivers;
00344 //  double perc_power_leak_senseamp_mux_lev_2_predecoder_blocks;
00345 //  double perc_power_leak_senseamp_mux_lev_2_decoders;
00346 //  double perc_power_leak_bitlines;
00347 //  double perc_power_leak_sense_amps;
00348 //  double perc_power_leak_prechg_eq_drivers;
00349 //  double perc_power_leak_subarray_output_drivers;
00350 //  double perc_power_leak_dataout_vertical_htree;
00351 //  double perc_power_leak_comparators;
00352 //  double perc_power_leak_crossbar;
00353 //  double perc_leak_mats;
00354 //  double perc_active_mats;
00355   double refresh_power;
00356   double dram_refresh_period;
00357   double dram_array_availability;
00358   double dyn_read_energy_from_closed_page;
00359   double dyn_read_energy_from_open_page;
00360   double leak_power_subbank_closed_page;
00361   double leak_power_subbank_open_page;
00362   double leak_power_request_and_reply_networks;
00363   double activate_energy;
00364   double read_energy;
00365   double write_energy;
00366   double precharge_energy;
00367 } results_mem_array;
00368 
00369 
00370 class uca_org_t
00371 {
00372   public:
00373     mem_array * tag_array2;
00374     mem_array * data_array2;
00375     double access_time;
00376     double cycle_time;
00377     double area;
00378     double area_efficiency;
00379     powerDef power;
00380     double leak_power_with_sleep_transistors_in_mats;
00381     double cache_ht;
00382     double cache_len;
00383     char file_n[100];
00384     double vdd_periph_global;
00385     bool valid;
00386     results_mem_array tag_array;
00387     results_mem_array data_array;
00388 
00389     uca_org_t();
00390     void find_delay();
00391     void find_energy();
00392     void find_area();
00393     void find_cyc();
00394     void adjust_area();//for McPAT only to adjust routing overhead
00395     void cleanup();
00396     ~uca_org_t(){};
00397 };
00398 
00399 /* ----- SoM SST ----- */
00400 void SSTreconfigure(InputParameter *local_interface, uca_org_t *fin_res);
00401 //uca_org_t cacti_interface();
00402 /* ----- EoM ----- */
00403 
00404 
00405 uca_org_t cacti_interface(const string & infile_name);
00406 //McPAT's plain interface, please keep !!!
00407 uca_org_t cacti_interface(InputParameter * const local_interface);
00408 //McPAT's plain interface, please keep !!!
00409 uca_org_t init_interface(InputParameter * const local_interface);
00410 //McPAT's plain interface, please keep !!!
00411 uca_org_t cacti_interface(
00412             int cache_size,
00413             int line_size,
00414             int associativity,
00415             int rw_ports,
00416             int excl_read_ports,
00417             int excl_write_ports,
00418             int single_ended_read_ports,
00419             int search_ports,
00420             int banks,
00421             double tech_node,
00422             int output_width,
00423             int specific_tag,
00424             int tag_width,
00425             int access_mode,
00426             int cache,
00427             int main_mem,
00428             int obj_func_delay,
00429             int obj_func_dynamic_power,
00430             int obj_func_leakage_power,
00431             int obj_func_area,
00432             int obj_func_cycle_time,
00433             int dev_func_delay,
00434             int dev_func_dynamic_power,
00435             int dev_func_leakage_power,
00436             int dev_func_area,
00437             int dev_func_cycle_time,
00438             int temp,
00439             int data_arr_ram_cell_tech_flavor_in,
00440             int data_arr_peri_global_tech_flavor_in,
00441             int tag_arr_ram_cell_tech_flavor_in,
00442             int tag_arr_peri_global_tech_flavor_in,
00443             int interconnect_projection_type_in,
00444             int wire_inside_mat_type_in,
00445             int wire_outside_mat_type_in,
00446             int REPEATERS_IN_HTREE_SEGMENTS_in,
00447             int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in,
00448             int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in,
00449             int PAGE_SIZE_BITS_in,
00450             int BURST_LENGTH_in,
00451             int INTERNAL_PREFETCH_WIDTH_in,
00452             int force_wiretype,
00453             int wiretype,
00454             int force_config,
00455             int ndwl,
00456             int ndbl,
00457             int nspd,
00458             int ndcm,
00459             int ndsam1,
00460             int ndsam2,
00461             int ecc);
00462 //    int cache_size,
00463 //    int line_size,
00464 //    int associativity,
00465 //    int rw_ports,
00466 //    int excl_read_ports,
00467 //    int excl_write_ports,
00468 //    int single_ended_read_ports,
00469 //    int banks,
00470 //    double tech_node,
00471 //    int output_width,
00472 //    int specific_tag,
00473 //    int tag_width,
00474 //    int access_mode,
00475 //    int cache,
00476 //    int main_mem,
00477 //    int obj_func_delay,
00478 //    int obj_func_dynamic_power,
00479 //    int obj_func_leakage_power,
00480 //    int obj_func_area,
00481 //    int obj_func_cycle_time,
00482 //    int dev_func_delay,
00483 //    int dev_func_dynamic_power,
00484 //    int dev_func_leakage_power,
00485 //    int dev_func_area,
00486 //    int dev_func_cycle_time,
00487 //    int temp,
00488 //    int data_arr_ram_cell_tech_flavor_in,
00489 //    int data_arr_peri_global_tech_flavor_in,
00490 //    int tag_arr_ram_cell_tech_flavor_in,
00491 //    int tag_arr_peri_global_tech_flavor_in,
00492 //    int interconnect_projection_type_in,
00493 //    int wire_inside_mat_type_in,
00494 //    int wire_outside_mat_type_in,
00495 //    int REPEATERS_IN_HTREE_SEGMENTS_in,
00496 //    int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in,
00497 //    int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in,
00498 ////    double MAXAREACONSTRAINT_PERC_in,
00499 ////    double MAXACCTIMECONSTRAINT_PERC_in,
00500 ////    double MAX_PERC_DIFF_IN_DELAY_FROM_BEST_DELAY_REPEATER_SOLUTION_in,
00501 //    int PAGE_SIZE_BITS_in,
00502 //    int BURST_LENGTH_in,
00503 //    int INTERNAL_PREFETCH_WIDTH_in);
00504 
00505 //Naveen's interface
00506 uca_org_t cacti_interface(
00507     int cache_size,
00508     int line_size,
00509     int associativity,
00510     int rw_ports,
00511     int excl_read_ports,
00512     int excl_write_ports,
00513     int single_ended_read_ports,
00514     int banks,
00515     double tech_node,
00516     int page_sz,
00517     int burst_length,
00518     int pre_width,
00519     int output_width,
00520     int specific_tag,
00521     int tag_width,
00522     int access_mode, //0 normal, 1 seq, 2 fast
00523     int cache, //scratch ram or cache
00524     int main_mem,
00525     int obj_func_delay,
00526     int obj_func_dynamic_power,
00527     int obj_func_leakage_power,
00528     int obj_func_area,
00529     int obj_func_cycle_time,
00530     int dev_func_delay,
00531     int dev_func_dynamic_power,
00532     int dev_func_leakage_power,
00533     int dev_func_area,
00534     int dev_func_cycle_time,
00535     int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate
00536     int temp,
00537     int wt, //0 - default(search across everything), 1 - global, 2 - 5% delay penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing
00538     int data_arr_ram_cell_tech_flavor_in,
00539     int data_arr_peri_global_tech_flavor_in,
00540     int tag_arr_ram_cell_tech_flavor_in,
00541     int tag_arr_peri_global_tech_flavor_in,
00542     int interconnect_projection_type_in, // 0 - aggressive, 1 - normal
00543     int wire_inside_mat_type_in,
00544     int wire_outside_mat_type_in,
00545     int is_nuca, // 0 - UCA, 1 - NUCA
00546     int core_count,
00547     int cache_level, // 0 - L2, 1 - L3
00548     int nuca_bank_count,
00549     int nuca_obj_func_delay,
00550     int nuca_obj_func_dynamic_power,
00551     int nuca_obj_func_leakage_power,
00552     int nuca_obj_func_area,
00553     int nuca_obj_func_cycle_time,
00554     int nuca_dev_func_delay,
00555     int nuca_dev_func_dynamic_power,
00556     int nuca_dev_func_leakage_power,
00557     int nuca_dev_func_area,
00558     int nuca_dev_func_cycle_time,
00559     int REPEATERS_IN_HTREE_SEGMENTS_in,//TODO for now only wires with repeaters are supported
00560     int p_input);
00561 
00562 class mem_array
00563 {
00564   public:
00565   /* ----- SoM ----- */
00566   int    Ndcm;
00567   /* ----- EoM ----- */
00568   int    Ndwl;
00569   int    Ndbl;
00570   double Nspd;
00571   int    deg_bl_muxing;
00572   int    Ndsam_lev_1;
00573   int    Ndsam_lev_2;
00574   double access_time;
00575   double cycle_time;
00576   double multisubbank_interleave_cycle_time;
00577   double area_ram_cells;
00578   double area;
00579   powerDef power;
00580   double delay_senseamp_mux_decoder;
00581   double delay_before_subarray_output_driver;
00582   double delay_from_subarray_output_driver_to_output;
00583   double height;
00584   double width;
00585 
00586   double mat_height;
00587   double mat_length;
00588   double subarray_length;
00589   double subarray_height;
00590 
00591   double delay_route_to_bank,
00592          delay_input_htree,
00593          delay_row_predecode_driver_and_block,
00594          delay_row_decoder,
00595          delay_bitlines,
00596          delay_sense_amp,
00597          delay_subarray_output_driver,
00598          delay_dout_htree,
00599          delay_comparator,
00600          delay_matchlines;
00601 
00602   double all_banks_height,
00603          all_banks_width,
00604          area_efficiency;
00605 
00606   powerDef power_routing_to_bank;
00607   powerDef power_addr_input_htree;
00608   powerDef power_data_input_htree;
00609   powerDef power_data_output_htree;
00610   powerDef power_htree_in_search;
00611   powerDef power_htree_out_search;
00612   powerDef power_row_predecoder_drivers;
00613   powerDef power_row_predecoder_blocks;
00614   powerDef power_row_decoders;
00615   powerDef power_bit_mux_predecoder_drivers;
00616   powerDef power_bit_mux_predecoder_blocks;
00617   powerDef power_bit_mux_decoders;
00618   powerDef power_senseamp_mux_lev_1_predecoder_drivers;
00619   powerDef power_senseamp_mux_lev_1_predecoder_blocks;
00620   powerDef power_senseamp_mux_lev_1_decoders;
00621   powerDef power_senseamp_mux_lev_2_predecoder_drivers;
00622   powerDef power_senseamp_mux_lev_2_predecoder_blocks;
00623   powerDef power_senseamp_mux_lev_2_decoders;
00624   powerDef power_bitlines;
00625   powerDef power_sense_amps;
00626   powerDef power_prechg_eq_drivers;
00627   powerDef power_output_drivers_at_subarray;
00628   powerDef power_dataout_vertical_htree;
00629   powerDef power_comparators;
00630 
00631   powerDef power_cam_bitline_precharge_eq_drv;
00632   powerDef power_searchline;
00633   powerDef power_searchline_precharge;
00634   powerDef power_matchlines;
00635   powerDef power_matchline_precharge;
00636   powerDef power_matchline_to_wordline_drv;
00637 
00638   min_values_t *arr_min;
00639   enum Wire_type wt;
00640 
00641   // dram stats
00642   double activate_energy, read_energy, write_energy, precharge_energy,
00643   refresh_power, leak_power_subbank_closed_page, leak_power_subbank_open_page,
00644   leak_power_request_and_reply_networks;
00645 
00646   double precharge_delay;
00647 
00648   static bool lt(const mem_array * m1, const mem_array * m2);
00649 };
00650 
00651 
00652 #endif

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