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sst/elements/mcopteron/MemoryModel.h

00001 
00002 #ifndef MEMORYMODEL_H
00003 #define MEMORYMODEL_H
00004 
00005 #include <OpteronDefs.h>
00006 //#include <CycleTracker.h>
00007 
00008 //-------------------------------------------------------------------
00009 /// @brief Memory model class
00010 ///
00011 /// Memory model should:
00012 /// - keep track of how many loads and stores are outstanding in order
00013 ///   to stall if buffers are full
00014 /// - should sample st2ld hist on a load to see if load is satisfied
00015 ///   from store buffer
00016 /// - should use memory hierarchy probabilities to sim memory access
00017 ///   and report latency
00018 /// - TODO: currently, memory model is not doing anything with ld-ld
00019 ///   and st-st distances, maybe it should. It does keep the mem queue
00020 ///   and stalls accordingly if mem ops happen close to each other, but
00021 ///   this might not capture the true distribution
00022 //-------------------------------------------------------------------
00023 class MemoryModel
00024 {
00025    // Memory operation types
00026    enum MemOpType {MEMLOAD, MEMSTORE};
00027    
00028    // Various constant costs
00029    class Cost {
00030      public:
00031       static const unsigned int LoadAfterLoad = 1;
00032       static const unsigned int LoadFromSTB = 2;
00033       static const unsigned int AverageStoreLatency = 25;
00034       static const unsigned int StoreAfterStore = 2;
00035    };
00036    
00037    class Config {
00038      public:
00039       static const unsigned int StoreBufferSize = 8;
00040    };
00041    
00042    /// Memory operation list node type
00043    struct MemoryOp 
00044    {
00045       InstructionCount insnNum;
00046       Address address;
00047       unsigned int numBytes;
00048       CycleCount issueCycle;
00049       CycleCount satisfiedCycle;
00050       MemOpType op;
00051       struct MemoryOp *next;
00052    };
00053 
00054  public:
00055    MemoryModel();
00056    ~MemoryModel();
00057    void initLatencies(unsigned int latTLB, unsigned int latL1, unsigned int latL2, 
00058                       unsigned int latL3, unsigned int latMem);
00059    void initProbabilities(double pSTBHit, double pL1Hit, double pL2Hit, double pL3Hit,
00060                           double pTLBMiss, double pICHit, double pIL2Hit, double pIL3Hit,
00061                           double pITLBMiss);
00062    void getDataLoadStats(unsigned long long *numLoads,
00063                          unsigned long long *numSTBHits,
00064                          unsigned long long *numL1Hits,
00065                          unsigned long long *numL2Hits,
00066                          unsigned long long *numL3Hits,
00067                          unsigned long long *numMemoryHits,
00068                          unsigned long long *numTLBMisses);
00069    void getInstLoadStats(unsigned long long *numILoads,
00070                          unsigned long long *numICHits,
00071                          unsigned long long *numIL2Hits,
00072                          unsigned long long *numIMemoryHits,
00073                          unsigned long long *numITLBMisses);
00074    void getStoreStats(unsigned long long *numStores );
00075    CycleCount serveLoad(CycleCount currentCycle, Address address,
00076                         unsigned int numBytes);
00077    CycleCount serveILoad(CycleCount currentCycle, Address address,
00078                          unsigned int numBytes);
00079    CycleCount serveStore(CycleCount currentCycle, Address address,
00080                          unsigned int numBytes);
00081  private:
00082    int addToMemoryQ(CycleCount whenSatisfied, MemOpType type);
00083    unsigned int numberInMemoryQ(MemOpType memOp);
00084    double purgeMemoryQ(CycleCount upToCycle);
00085 
00086    MemoryOp *memQHead, *memQTail, *lastLoad, *lastStore;
00087    unsigned int numLoadsInQ, numStoresInQ;
00088    unsigned int latencyL1, latencyL2, latencyL3, latencyMem, latencyTLB;
00089    double pSTBHit, pL1Hit, pL2Hit, pL3Hit, pTLBMiss, pICHit, pIL2Hit, pIL3Hit, pITLBMiss;
00090    unsigned long long numL1Hits, numL2Hits, numL3Hits, numMemoryHits, numTLBMisses;
00091    unsigned long long numICHits, numIL2Hits, numIL3Hits, numIMemoryHits, numITLBMisses;
00092    unsigned long long numSTBHits, numStores, numLoads, numILoads;
00093 };
00094 
00095 #endif

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