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sst/core/techModels/libMcPATbeta/decoder.h

00001 /*------------------------------------------------------------
00002  *                              CACTI 6.5
00003  *         Copyright 2008 Hewlett-Packard Development Corporation
00004  *                         All Rights Reserved
00005  *
00006  * Permission to use, copy, and modify this software and its documentation is
00007  * hereby granted only under the following terms and conditions.  Both the
00008  * above copyright notice and this permission notice must appear in all copies
00009  * of the software, derivative works or modified versions, and any portions
00010  * thereof, and both notices must appear in supporting documentation.
00011  *
00012  * Users of this software agree to the terms and conditions set forth herein, and
00013  * hereby grant back to Hewlett-Packard Company and its affiliated companies ("HP")
00014  * a non-exclusive, unrestricted, royalty-free right and license under any changes,
00015  * enhancements or extensions  made to the core functions of the software, including
00016  * but not limited to those affording compatibility with other hardware or software
00017  * environments, but excluding applications which incorporate this software.
00018  * Users further agree to use their best efforts to return to HP any such changes,
00019  * enhancements or extensions that they make and inform HP of noteworthy uses of
00020  * this software.  Correspondence should be provided to HP at:
00021  *
00022  *                       Director of Intellectual Property Licensing
00023  *                       Office of Strategy and Technology
00024  *                       Hewlett-Packard Company
00025  *                       1501 Page Mill Road
00026  *                       Palo Alto, California  94304
00027  *
00028  * This software may be distributed (but not offered for sale or transferred
00029  * for compensation) to third parties, provided such third parties agree to
00030  * abide by the terms and conditions of this notice.
00031  *
00032  * THE SOFTWARE IS PROVIDED "AS IS" AND HP DISCLAIMS ALL
00033  * WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
00034  * OF MERCHANTABILITY AND FITNESS.   IN NO EVENT SHALL HP
00035  * CORPORATION BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
00036  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
00037  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS
00038  * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
00039  * SOFTWARE.
00040  *------------------------------------------------------------*/
00041 
00042 
00043 #ifndef __DECODER_H__
00044 #define __DECODER_H__
00045 
00046 #include "area.h"
00047 #include "McPATcomponent.h"
00048 #include "parameter.h"
00049 #include <vector>
00050 
00051 using namespace std;
00052 
00053 
00054 class Decoder : public McPATComponent
00055 {
00056   public:
00057     Decoder(
00058         int _num_dec_signals,
00059         bool flag_way_select,
00060         double _C_ld_dec_out,
00061         double _R_wire_dec_out,
00062         bool fully_assoc_,
00063         bool is_dram_,
00064         bool is_wl_tr_,
00065         const Area & cell_);
00066 
00067     bool   exist;
00068     int    num_in_signals;
00069     double C_ld_dec_out;
00070     double R_wire_dec_out;
00071     int    num_gates;
00072     int    num_gates_min;
00073     double w_dec_n[MAX_NUMBER_GATES_STAGE];
00074     double w_dec_p[MAX_NUMBER_GATES_STAGE];
00075     double delay;
00076     //powerDef power;
00077     bool   fully_assoc;
00078     bool   is_dram;
00079     bool   is_wl_tr;
00080     const  Area & cell;
00081 
00082 
00083     void   compute_widths();
00084     void   compute_area();
00085     double compute_delays(double inrisetime);  // return outrisetime
00086     /*---SoM SST----*/
00087     void SSTleakage_feedback(double temperature);
00088     /*---EoM SST----*/
00089 };
00090 
00091 
00092 
00093 class PredecBlk : public McPATComponent
00094 {
00095  public:
00096   PredecBlk(
00097       int num_dec_signals,
00098       Decoder * dec,
00099       double C_wire_predec_blk_out,
00100       double R_wire_predec_blk_out,
00101       int    num_dec_per_predec,
00102       bool   is_dram_,
00103       bool   is_blk1);
00104 
00105   Decoder * dec;
00106   bool exist;
00107   int number_input_addr_bits;
00108   double C_ld_predec_blk_out;
00109   double R_wire_predec_blk_out;
00110   int branch_effort_nand2_gate_output;
00111   int branch_effort_nand3_gate_output;
00112   bool   flag_two_unique_paths;
00113   int flag_L2_gate;
00114   int number_inputs_L1_gate;
00115   int number_gates_L1_nand2_path;
00116   int number_gates_L1_nand3_path;
00117   int number_gates_L2;
00118   int min_number_gates_L1;
00119   int min_number_gates_L2;
00120   int num_L1_active_nand2_path;
00121   int num_L1_active_nand3_path;
00122   double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE];
00123   double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE];
00124   double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE];
00125   double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE];
00126   double w_L2_n[MAX_NUMBER_GATES_STAGE];
00127   double w_L2_p[MAX_NUMBER_GATES_STAGE];
00128   double delay_nand2_path;
00129   double delay_nand3_path;
00130   powerDef power_nand2_path;
00131   powerDef power_nand3_path;
00132   powerDef power_L2;
00133 
00134   bool is_dram_;
00135 
00136   void compute_widths();
00137   void compute_area();
00138   pair<double, double> compute_delays(pair<double, double> inrisetime); // <nand2, nand3>
00139   // return <outrise_nand2, outrise_nand3>
00140 
00141      /*---SoM SST----*/
00142     void SSTleakage_feedback(double temperature);
00143     /*---EoM SST----*/
00144 
00145 };
00146 
00147 
00148 class PredecBlkDrv : public McPATComponent
00149 {
00150  public:
00151   PredecBlkDrv(
00152       int   way_select,
00153       PredecBlk * blk_,
00154       bool  is_dram);
00155 
00156   int flag_driver_exists;
00157   int number_input_addr_bits;
00158   int number_gates_nand2_path;
00159   int number_gates_nand3_path;
00160   int min_number_gates;
00161   int num_buffers_driving_1_nand2_load;
00162   int num_buffers_driving_2_nand2_load;
00163   int num_buffers_driving_4_nand2_load;
00164   int num_buffers_driving_2_nand3_load;
00165   int num_buffers_driving_8_nand3_load;
00166   int num_buffers_nand3_path;
00167   double c_load_nand2_path_out;
00168   double c_load_nand3_path_out;
00169   double r_load_nand2_path_out;
00170   double r_load_nand3_path_out;
00171   double width_nand2_path_n[MAX_NUMBER_GATES_STAGE];
00172   double width_nand2_path_p[MAX_NUMBER_GATES_STAGE];
00173   double width_nand3_path_n[MAX_NUMBER_GATES_STAGE];
00174   double width_nand3_path_p[MAX_NUMBER_GATES_STAGE];
00175   double delay_nand2_path;
00176   double delay_nand3_path;
00177   powerDef power_nand2_path;
00178   powerDef power_nand3_path;
00179 
00180   PredecBlk * blk;
00181   Decoder   * dec;
00182   bool  is_dram_;
00183   int   way_select;
00184 
00185   void compute_widths();
00186   void compute_area();
00187   pair<double, double> compute_delays(
00188       double inrisetime_nand2_path,
00189       double inrisetime_nand3_path);  // return <outrise_nand2, outrise_nand3>
00190 
00191   inline int num_addr_bits_nand2_path()
00192   {
00193     return num_buffers_driving_1_nand2_load +
00194            num_buffers_driving_2_nand2_load +
00195            num_buffers_driving_4_nand2_load;
00196   }
00197   inline int num_addr_bits_nand3_path()
00198   {
00199     return num_buffers_driving_2_nand3_load +
00200            num_buffers_driving_8_nand3_load;
00201   }
00202   double get_rdOp_dynamic_E(int num_act_mats_hor_dir);
00203 
00204    /*---SoM SST----*/
00205     void SSTleakage_feedback(double temperature);
00206     /*---EoM SST----*/
00207 
00208 };
00209 
00210 
00211 
00212 class Predec : public McPATComponent
00213 {
00214   public:
00215     Predec(
00216         PredecBlkDrv * drv1,
00217         PredecBlkDrv * drv2);
00218 
00219     double compute_delays(double inrisetime);  // return outrisetime
00220 
00221     PredecBlk    * blk1;
00222     PredecBlk    * blk2;
00223     PredecBlkDrv * drv1;
00224     PredecBlkDrv * drv2;
00225 
00226     powerDef block_power;
00227     powerDef driver_power;
00228 
00229      /*---SoM SST----*/
00230     void SSTleakage_feedback(double temperature);
00231     /*---EoM SST----*/
00232 
00233 
00234   private:
00235     // returns <delay, risetime>
00236     pair<double, double> get_max_delay_before_decoder(
00237         pair<double, double> input_pair1,
00238         pair<double, double> input_pair2);
00239 };
00240 
00241 
00242 
00243 class Driver : public McPATComponent
00244 {
00245  public:
00246   Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram);
00247 
00248   int    number_gates;
00249   int    min_number_gates;
00250   double width_n[MAX_NUMBER_GATES_STAGE];
00251   double width_p[MAX_NUMBER_GATES_STAGE];
00252   double c_gate_load;
00253   double c_wire_load;
00254   double r_wire_load;
00255   double delay;
00256   powerDef power;
00257   bool   is_dram_;
00258 
00259   void   compute_widths();
00260   double compute_delay(double inrisetime);
00261 };
00262 
00263 
00264 #endif

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