00001 /*------------------------------------------------------------------------- 00002 * ORION 2.0 00003 * 00004 * Copyright 2009 00005 * Princeton University, and Regents of the University of California 00006 * All Rights Reserved 00007 * 00008 * 00009 * ORION 2.0 was developed by Bin Li at Princeton University and Kambiz Samadi at 00010 * University of California, San Diego. ORION 2.0 was built on top of ORION 1.0. 00011 * ORION 1.0 was developed by Hangsheng Wang, Xinping Zhu and Xuning Chen at 00012 * Princeton University. 00013 * 00014 * If your use of this software contributes to a published paper, we 00015 * request that you cite our paper that appears on our website 00016 * http://www.princeton.edu/~peh/orion.html 00017 * 00018 * Permission to use, copy, and modify this software and its documentation is 00019 * granted only under the following terms and conditions. Both the 00020 * above copyright notice and this permission notice must appear in all copies 00021 * of the software, derivative works or modified versions, and any portions 00022 * thereof, and both notices must appear in supporting documentation. 00023 * 00024 * This software may be distributed (but not offered for sale or transferred 00025 * for compensation) to third parties, provided such third parties agree to 00026 * abide by the terms and conditions of this notice. 00027 * 00028 * This software is distributed in the hope that it will be useful to the 00029 * community, but WITHOUT ANY WARRANTY; without even the implied warranty of 00030 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 00031 * 00032 *-----------------------------------------------------------------------*/ 00033 00034 #ifndef _SIM_PORT_H 00035 #define _SIM_PORT_H 00036 00037 #include "SIM_router.h" 00038 00039 /* Technology node and operating freq and voltage */ 00040 #define PARM_Freq (1e9) 00041 #define PARM_Vdd (1.0) 00042 #define PARM_TECH_POINT (65) 00043 #define PARM_TRANSISTOR_TYPE (NVT) /* transistor type, HVT, NVT, or LVT */ 00044 /* End Technology node and operating freq and voltage */ 00045 00046 #define PARM_POWER_STATS 1 00047 00048 /* RF module parameters */ 00049 #define PARM_read_port 1 00050 #define PARM_write_port 1 00051 #define PARM_n_regs 64 00052 #define PARM_reg_width 32 00053 00054 #define PARM_ndwl 1 00055 #define PARM_ndbl 1 00056 #define PARM_nspd 1 00057 00058 /* router module parameters */ 00059 /* general parameters */ 00060 #define PARM_in_port 7 /* # of network input ports */ 00061 #define PARM_cache_in_port 0 /* # of cache input ports */ 00062 #define PARM_mc_in_port 0 /* # of memory controller input ports */ 00063 #define PARM_io_in_port 0 /* # of I/O device input ports */ 00064 #define PARM_out_port 7 /* # of network output ports */ 00065 #define PARM_cache_out_port 0 /* # of cache output ports */ 00066 #define PARM_mc_out_port 0 /* # of memory controller output ports */ 00067 #define PARM_io_out_port 0 /* # of I/O device output ports */ 00068 #define PARM_flit_width 32 /* flit width in bits */ 00069 00070 /* virtual channel parameters */ 00071 #define PARM_v_channel 1 /* # of network port virtual channels */ 00072 #define PARM_v_class 0 /* # of total virtual classes */ 00073 #define PARM_cache_class 0 /* # of cache port virtual classes */ 00074 #define PARM_mc_class 0 /* # of memory controller port virtual classes */ 00075 #define PARM_io_class 0 /* # of I/O device port virtual classes */ 00076 /* ?? */ 00077 #define PARM_in_share_buf 1 /* do input virtual channels physically share buffers? */ 00078 #define PARM_out_share_buf 1 /* do output virtual channels physically share buffers? */ 00079 /* ?? */ 00080 #define PARM_in_share_switch 1 /* do input virtual channels share crossbar input ports? */ 00081 #define PARM_out_share_switch 1 /* do output virtual channels share crossbar output ports? */ 00082 00083 /* crossbar parameters */ 00084 #define PARM_crossbar_model MULTREE_CROSSBAR/* crossbar model type */ 00085 #define PARM_crsbar_degree 4 /* crossbar mux degree */ 00086 #define PARM_connect_type TRANS_GATE /* crossbar connector type */ 00087 #define PARM_trans_type NP_GATE /* crossbar transmission gate type */ 00088 #define PARM_crossbar_in_len 0 /* crossbar input line length, if known */ 00089 #define PARM_crossbar_out_len 0 /* crossbar output line length, if known */ 00090 #define PARM_xb_in_seg 0 00091 #define PARM_xb_out_seg 0 00092 /* HACK HACK HACK */ 00093 #define PARM_exp_xb_model MATRIX_CROSSBAR 00094 #define PARM_exp_in_seg 2 00095 #define PARM_exp_out_seg 2 00096 00097 00098 /* input buffer parameters */ 00099 #define PARM_in_buf 1 /* have input buffer? */ 00100 #define PARM_in_buf_set 4 /* # of rows */ 00101 #define PARM_in_buf_rport 1 /* # of read ports */ 00102 00103 #define PARM_cache_in_buf 0 00104 #define PARM_cache_in_buf_set 0 00105 #define PARM_cache_in_buf_rport 0 00106 00107 #define PARM_mc_in_buf 0 00108 #define PARM_mc_in_buf_set 0 00109 #define PARM_mc_in_buf_rport 0 00110 00111 #define PARM_io_in_buf 0 00112 #define PARM_io_in_buf_set 0 00113 #define PARM_io_in_buf_rport 0 00114 00115 /* output buffer parameters */ 00116 #define PARM_out_buf 0 00117 #define PARM_out_buf_set 16 00118 #define PARM_out_buf_wport 1 00119 00120 /* central buffer parameters */ 00121 #define PARM_central_buf 0 /* have central buffer? */ 00122 #define PARM_cbuf_set 2560 /* # of rows */ 00123 #define PARM_cbuf_rport 2 /* # of read ports */ 00124 #define PARM_cbuf_wport 2 /* # of write ports */ 00125 #define PARM_cbuf_width 4 /* # of flits in one row */ 00126 #define PARM_pipe_depth 4 /* # of banks */ 00127 00128 /* array parameters shared by various buffers */ 00129 #define PARM_wordline_model CACHE_RW_WORDLINE 00130 #define PARM_bitline_model RW_BITLINE 00131 #define PARM_mem_model NORMAL_MEM 00132 #define PARM_row_dec_model GENERIC_DEC 00133 #define PARM_row_dec_pre_model SINGLE_OTHER 00134 #define PARM_col_dec_model SIM_NO_MODEL 00135 #define PARM_col_dec_pre_model SIM_NO_MODEL 00136 #define PARM_mux_model SIM_NO_MODEL 00137 #define PARM_outdrv_model REG_OUTDRV 00138 00139 /* these 3 should be changed together */ 00140 /* use double-ended bitline because the array is too large */ 00141 #define PARM_data_end 2 00142 #define PARM_amp_model GENERIC_AMP 00143 #define PARM_bitline_pre_model EQU_BITLINE 00144 //#define PARM_data_end 1 00145 //#define PARM_amp_model SIM_NO_MODEL 00146 //#define PARM_bitline_pre_model SINGLE_OTHER 00147 00148 /* arbiter parameters */ 00149 #define PARM_in_arb_model MATRIX_ARBITER /* input side arbiter model type */ 00150 #define PARM_in_arb_ff_model NEG_DFF /* input side arbiter flip-flop model type */ 00151 #define PARM_out_arb_model MATRIX_ARBITER /* output side arbiter model type */ 00152 #define PARM_out_arb_ff_model NEG_DFF /* output side arbiter flip-flop model type */ 00153 00154 #endif /* _SIM_PORT_H */