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00025 #define TCG_TARGET_ARM 1
00026
00027 #define TCG_TARGET_REG_BITS 32
00028 #undef TCG_TARGET_WORDS_BIGENDIAN
00029 #undef TCG_TARGET_HAS_div_i32
00030 #undef TCG_TARGET_HAS_div_i64
00031 #undef TCG_TARGET_HAS_bswap_i32
00032 #define TCG_TARGET_HAS_ext8s_i32
00033 #define TCG_TARGET_HAS_ext16s_i32
00034 #define TCG_TARGET_HAS_neg_i32
00035 #undef TCG_TARGET_HAS_neg_i64
00036 #undef TCG_TARGET_STACK_GROWSUP
00037
00038 enum {
00039 TCG_REG_R0 = 0,
00040 TCG_REG_R1,
00041 TCG_REG_R2,
00042 TCG_REG_R3,
00043 TCG_REG_R4,
00044 TCG_REG_R5,
00045 TCG_REG_R6,
00046 TCG_REG_R7,
00047 TCG_REG_R8,
00048 TCG_REG_R9,
00049 TCG_REG_R10,
00050 TCG_REG_R11,
00051 TCG_REG_R12,
00052 TCG_REG_R13,
00053 TCG_REG_R14,
00054 TCG_TARGET_NB_REGS
00055 };
00056
00057
00058 #define TCG_REG_CALL_STACK TCG_REG_R13
00059 #define TCG_TARGET_STACK_ALIGN 8
00060 #define TCG_TARGET_CALL_STACK_OFFSET 0
00061
00062 enum {
00063
00064 TCG_AREG0 = TCG_REG_R7,
00065 TCG_AREG1 = TCG_REG_R4,
00066 TCG_AREG2 = TCG_REG_R5,
00067 TCG_AREG3 = TCG_REG_R6,
00068 };
00069
00070 static inline void flush_icache_range(unsigned long start, unsigned long stop)
00071 {
00072 #if QEMU_GNUC_PREREQ(4, 1)
00073 void __clear_cache(char *beg, char *end);
00074 __clear_cache((char *) start, (char *) stop);
00075 #else
00076 register unsigned long _beg __asm ("a1") = start;
00077 register unsigned long _end __asm ("a2") = stop;
00078 register unsigned long _flg __asm ("a3") = 0;
00079 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
00080 #endif
00081 }