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sst/core/techModels/libMcPATbeta/XML_Parse.h

00001 /*****************************************************************************
00002  *                                McPAT
00003  *                      SOFTWARE LICENSE AGREEMENT
00004  *            Copyright 2009 Hewlett-Packard Development Company, L.P.
00005  *                          All Rights Reserved
00006  *
00007  * Permission to use, copy, and modify this software and its documentation is
00008  * hereby granted only under the following terms and conditions.  Both the
00009  * above copyright notice and this permission notice must appear in all copies
00010  * of the software, derivative works or modified versions, and any portions
00011  * thereof, and both notices must appear in supporting documentation.
00012  *
00013  * Any User of the software ("User"), by accessing and using it, agrees to the
00014  * terms and conditions set forth herein, and hereby grants back to Hewlett-
00015  * Packard Development Company, L.P. and its affiliated companies ("HP") a
00016  * non-exclusive, unrestricted, royalty-free right and license to copy,
00017  * modify, distribute copies, create derivate works and publicly display and
00018  * use, any changes, modifications, enhancements or extensions made to the
00019  * software by User, including but not limited to those affording
00020  * compatibility with other hardware or software, but excluding pre-existing
00021  * software applications that may incorporate the software.  User further
00022  * agrees to use its best efforts to inform HP of any such changes,
00023  * modifications, enhancements or extensions.
00024  *
00025  * Correspondence should be provided to HP at:
00026  *
00027  * Director of Intellectual Property Licensing
00028  * Office of Strategy and Technology
00029  * Hewlett-Packard Company
00030  * 1501 Page Mill Road
00031  * Palo Alto, California  94304
00032  *
00033  * The software may be further distributed by User (but not offered for
00034  * sale or transferred for compensation) to third parties, under the
00035  * condition that such third parties agree to abide by the terms and
00036  * conditions of this license.
00037  *
00038  * THE SOFTWARE IS PROVIDED "AS IS" WITH ANY AND ALL ERRORS AND DEFECTS
00039  * AND USER ACKNOWLEDGES THAT THE SOFTWARE MAY CONTAIN ERRORS AND DEFECTS.
00040  * HP DISCLAIMS ALL WARRANTIES WITH REGARD TO THE SOFTWARE, INCLUDING ALL
00041  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS.   IN NO EVENT SHALL
00042  * HP BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES
00043  * OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
00044  * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER ACTION, ARISING
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00046  *
00047  ***************************************************************************/
00048 
00049 #ifndef XML_PARSE_H_
00050 #define XML_PARSE_H_
00051 
00052 
00053 //#ifdef WIN32
00054 //#define _CRT_SECURE_NO_DEPRECATE
00055 //#endif
00056 
00057 #include <stdio.h>
00058 #include "xmlParser.h"
00059 #include <string.h>
00060 #include <iostream>
00061 using namespace std;
00062 
00063 /*
00064 void myfree(char *t); // {free(t);}
00065 ToXMLStringTool tx,tx2;
00066 */
00067 //all subnodes at the level of system.core(0-n)
00068 //cache_policy is added into cache property arrays;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
00069 
00070 typedef struct{
00071         int prediction_width;
00072         char prediction_scheme[20];
00073         int predictor_size;
00074         int predictor_entries;
00075         int local_predictor_size[20];
00076         int local_predictor_entries;
00077         int global_predictor_entries;
00078         int global_predictor_bits;
00079         int chooser_predictor_entries;
00080         int chooser_predictor_bits;
00081         double predictor_accesses;
00082 } predictor_systemcore;
00083 typedef struct{
00084         int number_entries;
00085         int cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
00086         double total_hits;
00087         double total_accesses;
00088         double total_misses;
00089         double conflicts;
00090 } itlb_systemcore;
00091 typedef struct{
00092         //params
00093         double icache_config[20];
00094         int buffer_sizes[20];
00095         int cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
00096         //stats
00097         double total_accesses;
00098         double read_accesses;
00099         double read_misses;
00100         double replacements;
00101         double read_hits;
00102         double total_hits;
00103         double total_misses;
00104         double miss_buffer_access;
00105         double fill_buffer_accesses;
00106         double prefetch_buffer_accesses;
00107         double prefetch_buffer_writes;
00108         double prefetch_buffer_reads;
00109         double prefetch_buffer_hits;
00110         double conflicts;
00111 } icache_systemcore;
00112 typedef struct{
00113         //params
00114         int number_entries;
00115         int cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
00116         //stats
00117         double total_accesses;
00118         double read_accesses;
00119         double write_accesses;
00120         double write_hits;
00121         double read_hits;
00122         double read_misses;
00123         double write_misses;
00124         double total_hits;
00125         double total_misses;
00126         double conflicts;
00127 } dtlb_systemcore;
00128 typedef struct{
00129         //params
00130         double dcache_config[20];
00131         int buffer_sizes[20];
00132         int cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
00133         //stats
00134         double total_accesses;
00135         double read_accesses;
00136         double write_accesses;
00137         double total_hits;
00138         double total_misses;
00139         double read_hits;
00140         double write_hits;
00141         double read_misses;
00142         double write_misses;
00143         double replacements;
00144         double write_backs;
00145         double miss_buffer_access;
00146         double fill_buffer_accesses;
00147         double prefetch_buffer_accesses;
00148         double prefetch_buffer_writes;
00149         double prefetch_buffer_reads;
00150         double prefetch_buffer_hits;
00151         double wbb_writes;
00152         double wbb_reads;
00153         double conflicts;
00154 } dcache_systemcore;
00155 typedef struct{
00156         //params
00157         int BTB_config[20];
00158         //stats
00159         double total_accesses;
00160         double read_accesses;
00161         double write_accesses;
00162         double total_hits;
00163         double total_misses;
00164         double read_hits;
00165         double write_hits;
00166         double read_misses;
00167         double write_misses;
00168         double replacements;
00169 } BTB_systemcore;
00170 typedef struct{
00171         //all params at the level of system.core(0-n)
00172         int clock_rate;
00173         bool opt_local;
00174         bool x86;
00175         int machine_bits;
00176         int virtual_address_width;
00177         int physical_address_width;
00178         int opcode_width;
00179         int micro_opcode_width;
00180         int instruction_length;
00181         int machine_type;
00182         int internal_datapath_width;
00183         int number_hardware_threads;
00184         int fetch_width;
00185         int number_instruction_fetch_ports;
00186         int decode_width;
00187         int issue_width;
00188         int peak_issue_width;
00189         int commit_width;
00190         int pipelines_per_core[20];
00191         int pipeline_depth[20];
00192         char FPU[20];
00193         char divider_multiplier[20];
00194         int ALU_per_core;
00195         double FPU_per_core;
00196         int MUL_per_core;
00197         int instruction_buffer_size;
00198         int decoded_stream_buffer_size;
00199         int instruction_window_scheme;
00200         int instruction_window_size;
00201         int fp_instruction_window_size;
00202         int ROB_size;
00203         int archi_Regs_IRF_size;
00204         int archi_Regs_FRF_size;
00205         int phy_Regs_IRF_size;
00206         int phy_Regs_FRF_size;
00207         int rename_scheme;
00208         int register_windows_size;
00209         char LSU_order[20];
00210         int store_buffer_size;
00211         int load_buffer_size;
00212         int memory_ports;
00213         char Dcache_dual_pump[20];
00214         int RAS_size;
00215         int fp_issue_width;
00216         int prediction_width;
00217         int number_of_BTB;
00218         int number_of_BPT;
00219 
00220         //all stats at the level of system.core(0-n)
00221         double total_instructions;
00222         double int_instructions;
00223         double fp_instructions;
00224         double branch_instructions;
00225         double branch_mispredictions;
00226         double committed_instructions;
00227         double committed_int_instructions;
00228         double committed_fp_instructions;
00229         double load_instructions;
00230         double store_instructions;
00231         double total_cycles;
00232         double idle_cycles;
00233         double busy_cycles;
00234         double instruction_buffer_reads;
00235         double instruction_buffer_write;
00236         double ROB_reads;
00237         double ROB_writes;
00238         double rename_accesses;
00239         double fp_rename_accesses;
00240         double rename_reads;
00241         double rename_writes;
00242         double fp_rename_reads;
00243         double fp_rename_writes;
00244         double inst_window_reads;
00245         double inst_window_writes;
00246         double inst_window_wakeup_accesses;
00247         double inst_window_selections;
00248         double fp_inst_window_reads;
00249         double fp_inst_window_writes;
00250         double fp_inst_window_wakeup_accesses;
00251         double fp_inst_window_selections;
00252         double archi_int_regfile_reads;
00253         double archi_float_regfile_reads;
00254         double phy_int_regfile_reads;
00255         double phy_float_regfile_reads;
00256         double phy_int_regfile_writes;
00257         double phy_float_regfile_writes;
00258         double archi_int_regfile_writes;
00259         double archi_float_regfile_writes;
00260         double int_regfile_reads;
00261         double float_regfile_reads;
00262         double int_regfile_writes;
00263         double float_regfile_writes;
00264         double windowed_reg_accesses;
00265         double windowed_reg_transports;
00266         double function_calls;
00267         double context_switches;
00268         double ialu_accesses;
00269         double fpu_accesses;
00270         double mul_accesses;
00271         double cdb_alu_accesses;
00272         double cdb_mul_accesses;
00273         double cdb_fpu_accesses;
00274         double load_buffer_reads;
00275         double load_buffer_writes;
00276         double load_buffer_cams;
00277         double store_buffer_reads;
00278         double store_buffer_writes;
00279         double store_buffer_cams;
00280         double store_buffer_forwards;
00281         double main_memory_access;
00282         double main_memory_read;
00283         double main_memory_write;
00284         double pipeline_duty_cycle;
00285 
00286         double IFU_duty_cycle ;
00287         double LSU_duty_cycle ;
00288         double MemManU_I_duty_cycle;
00289         double MemManU_D_duty_cycle ;
00290         double ALU_duty_cycle ;
00291         double MUL_duty_cycle ;
00292         double FPU_duty_cycle ;
00293         double ALU_cdb_duty_cycle ;
00294         double MUL_cdb_duty_cycle ;
00295         double FPU_cdb_duty_cycle ;
00296 
00297         //all subnodes at the level of system.core(0-n)
00298         predictor_systemcore predictor;
00299         itlb_systemcore itlb;
00300         icache_systemcore icache;
00301         dtlb_systemcore dtlb;
00302         dcache_systemcore dcache;
00303         BTB_systemcore BTB;
00304 
00305 } system_core;
00306 typedef struct{
00307         //params
00308         int Directory_type;
00309         double Dir_config[20];
00310         int buffer_sizes[20];
00311         int clockrate;
00312         int ports[20];
00313         int device_type;
00314         int cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
00315         char threeD_stack[20];
00316         //stats
00317         double total_accesses;
00318         double read_accesses;
00319         double write_accesses;
00320         double read_misses;
00321         double write_misses;
00322         double conflicts;
00323         double duty_cycle;
00324 } system_L1Directory;
00325 typedef struct{
00326         //params
00327         int Directory_type;
00328         double Dir_config[20];
00329         int buffer_sizes[20];
00330         int clockrate;
00331         int ports[20];
00332         int device_type;
00333         int cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
00334         char threeD_stack[20];
00335         //stats
00336         double total_accesses;
00337         double read_accesses;
00338         double write_accesses;
00339         double read_misses;
00340         double write_misses;
00341         double conflicts;
00342         double duty_cycle;
00343 } system_L2Directory;
00344 typedef struct{
00345         //params
00346         double L2_config[20];
00347         int clockrate;
00348         int ports[20];
00349         int device_type;
00350         int cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
00351         char threeD_stack[20];
00352         int buffer_sizes[20];
00353         //stats
00354         double total_accesses;
00355         double read_accesses;
00356         double write_accesses;
00357         double total_hits;
00358         double total_misses;
00359         double read_hits;
00360         double write_hits;
00361         double read_misses;
00362         double write_misses;
00363         double replacements;
00364         double write_backs;
00365         double miss_buffer_accesses;
00366         double fill_buffer_accesses;
00367         double prefetch_buffer_accesses;
00368         double prefetch_buffer_writes;
00369         double prefetch_buffer_reads;
00370         double prefetch_buffer_hits;
00371         double wbb_writes;
00372         double wbb_reads;
00373         double conflicts;
00374         double duty_cycle;
00375 } system_L2;
00376 typedef struct{
00377         //params
00378         double L3_config[20];
00379         int clockrate;
00380         int ports[20];
00381         int device_type;
00382         int cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
00383         char threeD_stack[20];
00384         int buffer_sizes[20];
00385         //stats
00386         double total_accesses;
00387         double read_accesses;
00388         double write_accesses;
00389         double total_hits;
00390         double total_misses;
00391         double read_hits;
00392         double write_hits;
00393         double read_misses;
00394         double write_misses;
00395         double replacements;
00396         double write_backs;
00397         double miss_buffer_accesses;
00398         double fill_buffer_accesses;
00399         double prefetch_buffer_accesses;
00400         double prefetch_buffer_writes;
00401         double prefetch_buffer_reads;
00402         double prefetch_buffer_hits;
00403         double wbb_writes;
00404         double wbb_reads;
00405         double conflicts;
00406         double duty_cycle;
00407 } system_L3;
00408 typedef struct{
00409         //params
00410         int number_of_inputs_of_crossbars;
00411         int number_of_outputs_of_crossbars;
00412         int flit_bits;
00413         int input_buffer_entries_per_port;
00414         int ports_of_input_buffer[20];
00415         //stats
00416         double crossbar_accesses;
00417 } xbar0_systemNoC;
00418 typedef struct{
00419         //params
00420         int clockrate;
00421         bool type;
00422         bool has_global_link;
00423         char topology[20];
00424         int horizontal_nodes;
00425         int vertical_nodes;
00426         int link_throughput;
00427         int link_latency;
00428         int input_ports;
00429         int output_ports;
00430         int virtual_channel_per_port;
00431         int flit_bits;
00432         int input_buffer_entries_per_vc;
00433         int ports_of_input_buffer[20];
00434         int dual_pump;
00435         int number_of_crossbars;
00436         char crossbar_type[20];
00437         char crosspoint_type[20];
00438         xbar0_systemNoC xbar0;
00439         int arbiter_type;
00440         double chip_coverage;
00441         /*----SST SoM-----*/
00442         double link_length;
00443         /*----SST EoM----*/
00444         //stats
00445         double total_accesses;
00446         double duty_cycle;
00447         double route_over_perc;
00448 } system_NoC;
00449 typedef struct{
00450         //params
00451         int mem_tech_node;
00452         int device_clock;
00453         int peak_transfer_rate;
00454         int internal_prefetch_of_DRAM_chip;
00455         int capacity_per_channel;
00456         int number_ranks;
00457         int num_banks_of_DRAM_chip;
00458         int Block_width_of_DRAM_chip;
00459         int output_width_of_DRAM_chip;
00460         int page_size_of_DRAM_chip;
00461         int burstlength_of_DRAM_chip;
00462         //stats
00463         double memory_accesses;
00464         double memory_reads;
00465         double memory_writes;
00466 } system_mem;
00467 typedef struct{
00468         //params
00469     int mc_clock;
00470         int peak_transfer_rate;
00471     int llc_line_length;
00472         int number_mcs;
00473         int memory_channels_per_mc;
00474         int number_ranks;
00475         int req_window_size_per_channel;
00476         int IO_buffer_size_per_channel;
00477         int databus_width;
00478         int addressbus_width;
00479         //stats
00480         double memory_accesses;
00481         double memory_reads;
00482         double memory_writes;
00483 } system_mc;
00484 
00485 typedef struct{
00486         //All number_of_* at the level of 'system' Ying 03/21/2009
00487         int number_of_cores;
00488         int number_of_L1Directories;
00489         int number_of_L2Directories;
00490         int number_of_L2s;
00491         bool Private_L2;
00492         int number_of_L3s;
00493         int number_of_NoCs;
00494         int number_of_dir_levels;
00495     int domain_size;
00496     int first_level_dir;
00497         // All params at the level of 'system'
00498         int homogeneous_cores;
00499         int homogeneous_L1Directories;
00500         int homogeneous_L2Directories;
00501         double core_tech_node;
00502         int target_core_clockrate;
00503         int target_chip_area;
00504         int temperature;
00505         int number_cache_levels;
00506         int L1_property;
00507         int L2_property;
00508         int homogeneous_L2s;
00509         int L3_property;
00510         int homogeneous_L3s;
00511         int homogeneous_NoCs;
00512         int homogeneous_ccs;
00513         int Max_area_deviation;
00514         int Max_power_deviation;
00515         int device_type;
00516         bool longer_channel_device;
00517         int opt_dynamic_power;
00518         int opt_lakage_power;
00519         int opt_clockrate;
00520         int opt_area;
00521         int interconnect_projection_type;
00522         int machine_bits;
00523         int virtual_address_width;
00524         int physical_address_width;
00525         int virtual_memory_page_size;
00526     double total_cycles;
00527         //system.core(0-n):3rd level
00528         system_core core[64];
00529         system_L1Directory L1Directory[64];
00530         system_L2Directory L2Directory[64];
00531         system_L2 L2[64];
00532         system_L3 L3[64];
00533     system_NoC NoC[64];
00534     system_mem mem;
00535         system_mc mc;
00536 } root_system;
00537 
00538 class ParseXML
00539 {
00540 public:
00541         void parse(char* filepath);
00542     void initialize();
00543 public:
00544         root_system sys;
00545 };
00546 
00547 
00548 #endif /* XML_PARSE_H_ */
00549 
00550 
00551 
00552 

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