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sst/elements/DRAMSimC/DRAMSimC.h

00001 // Copyright 2009-2010 Sandia Corporation. Under the terms
00002 // of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
00003 // Government retains certain rights in this software.
00004 // 
00005 // Copyright (c) 2009-2010, Sandia Corporation
00006 // All rights reserved.
00007 // 
00008 // This file is part of the SST software package. For license
00009 // information, see the LICENSE file in the top level directory of the
00010 // distribution.
00011 
00012 
00013 #ifndef _DRAMSIMC_H
00014 #define _DRAMSIMC_H
00015 
00016 #include <sst/core/log.h>
00017 #include <sst/core/event.h>
00018 #include <sst/core/introspectedComponent.h>
00019 #include <memoryChannel.h>
00020 #include <MemorySystem.h>
00021 
00022 
00023 using namespace std;
00024 using namespace SST;
00025 
00026 #ifndef DRAMSIMC_DBG
00027 #define DRAMSIMC_DBG 0
00028 #endif
00029 
00030 class DRAMSimC : public IntrospectedComponent {
00031 
00032     public: // functions
00033 
00034         DRAMSimC( ComponentId_t id, Params_t& params );
00035         int Finish();
00036 
00037     private: // types
00038 
00039         typedef MemoryChannel<uint64_t> memChan_t;
00040 
00041     private: // functions
00042 
00043         DRAMSimC( const DRAMSimC& c );
00044         bool clock( Cycle_t  );
00045 
00046         inline DRAMSim::TransactionType 
00047                         convertType( memChan_t::event_t::reqType_t type );
00048 
00049         void readData(uint id, uint64_t addr, uint64_t clockcycle);
00050         void writeData(uint id, uint64_t addr, uint64_t clockcycle);
00051         uint64_t getIntData(int dataID, int index);
00052 
00053         std::deque<Transaction> m_transQ;
00054         MemorySystem*           m_memorySystem;
00055         memChan_t*              m_memChan;
00056         std::string             m_printStats;
00057         Log< DRAMSIMC_DBG >&    m_dbg;
00058         Log<>&                  m_log;
00059 
00060 };
00061 
00062 inline DRAMSim::TransactionType 
00063             DRAMSimC::convertType( memChan_t::event_t::reqType_t type )
00064 {
00065     switch( type ) {
00066     case memChan_t::event_t::READ:
00067       return DRAMSim::DATA_READ;
00068     case memChan_t::event_t::WRITE:
00069       return DRAMSim::DATA_WRITE;
00070     default: ;
00071     }
00072     return (DRAMSim::TransactionType)-1;
00073 }
00074 
00075 #endif

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