00001 #ifndef SUN4M_H
00002 #define SUN4M_H
00003
00004
00005
00006
00007 void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq);
00008 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
00009 uint8_t *buf, int len, int is_write);
00010 static inline void sparc_iommu_memory_read(void *opaque,
00011 target_phys_addr_t addr,
00012 uint8_t *buf, int len)
00013 {
00014 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
00015 }
00016
00017 static inline void sparc_iommu_memory_write(void *opaque,
00018 target_phys_addr_t addr,
00019 uint8_t *buf, int len)
00020 {
00021 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
00022 }
00023
00024
00025 void tcx_init(target_phys_addr_t addr, uint8_t *vram_base,
00026 unsigned long vram_offset, int vram_size, int width, int height,
00027 int depth);
00028
00029
00030 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
00031 const uint32_t *intbit_to_level,
00032 qemu_irq **irq, qemu_irq **cpu_irq,
00033 qemu_irq **parent_irq, unsigned int cputimer);
00034 void slavio_pic_info(void *opaque);
00035 void slavio_irq_info(void *opaque);
00036
00037
00038 void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
00039 qemu_irq **parent_irq);
00040
00041
00042 void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
00043 qemu_irq *parent_irq);
00044 void sun4c_pic_info(void *opaque);
00045 void sun4c_irq_info(void *opaque);
00046
00047
00048 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
00049 qemu_irq *cpu_irqs, unsigned int num_cpus);
00050
00051
00052 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
00053 target_phys_addr_t aux1_base,
00054 target_phys_addr_t aux2_base, qemu_irq irq,
00055 qemu_irq cpu_halt, qemu_irq **fdc_tc);
00056 void slavio_set_power_fail(void *opaque, int power_failing);
00057
00058
00059 void cs_init(target_phys_addr_t base, int irq, void *intctl);
00060
00061
00062 #include "sparc32_dma.h"
00063
00064
00065 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
00066 qemu_irq irq, qemu_irq *reset);
00067
00068
00069 void *ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version);
00070
00071 #endif