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00020
00021 #ifndef CPU_CRIS_H
00022 #define CPU_CRIS_H
00023
00024 #define TARGET_LONG_BITS 32
00025
00026 #include "cpu-defs.h"
00027
00028 #define TARGET_HAS_ICE 1
00029
00030 #define ELF_MACHINE EM_CRIS
00031
00032 #define EXCP_NMI 1
00033 #define EXCP_GURU 2
00034 #define EXCP_BUSFAULT 3
00035 #define EXCP_IRQ 4
00036 #define EXCP_BREAK 5
00037
00038
00039 #define R_FP 8
00040 #define R_SP 14
00041 #define R_ACR 15
00042
00043
00044 #define PR_BZ 0
00045 #define PR_VR 1
00046 #define PR_PID 2
00047 #define PR_SRS 3
00048 #define PR_WZ 4
00049 #define PR_EXS 5
00050 #define PR_EDA 6
00051 #define PR_MOF 7
00052 #define PR_DZ 8
00053 #define PR_EBP 9
00054 #define PR_ERP 10
00055 #define PR_SRP 11
00056 #define PR_NRP 12
00057 #define PR_CCS 13
00058 #define PR_USP 14
00059 #define PR_SPC 15
00060
00061
00062 #define Q_FLAG 0x80000000
00063 #define M_FLAG 0x40000000
00064 #define S_FLAG 0x200
00065 #define R_FLAG 0x100
00066 #define P_FLAG 0x80
00067 #define U_FLAG 0x40
00068 #define P_FLAG 0x80
00069 #define U_FLAG 0x40
00070 #define I_FLAG 0x20
00071 #define X_FLAG 0x10
00072 #define N_FLAG 0x08
00073 #define Z_FLAG 0x04
00074 #define V_FLAG 0x02
00075 #define C_FLAG 0x01
00076 #define ALU_FLAGS 0x1F
00077
00078
00079 #define CC_CC 0
00080 #define CC_CS 1
00081 #define CC_NE 2
00082 #define CC_EQ 3
00083 #define CC_VC 4
00084 #define CC_VS 5
00085 #define CC_PL 6
00086 #define CC_MI 7
00087 #define CC_LS 8
00088 #define CC_HI 9
00089 #define CC_GE 10
00090 #define CC_LT 11
00091 #define CC_GT 12
00092 #define CC_LE 13
00093 #define CC_A 14
00094 #define CC_P 15
00095
00096
00097 #define F_DELAYSLOT 1
00098
00099 #define NB_MMU_MODES 2
00100
00101 typedef struct CPUCRISState {
00102 uint32_t regs[16];
00103
00104 uint32_t pregs[16];
00105
00106
00107 uint32_t pc;
00108
00109
00110 uint32_t ksp;
00111
00112
00113 int dslot;
00114 int btaken;
00115 uint32_t btarget;
00116
00117
00118 uint32_t cc_op;
00119 uint32_t cc_mask;
00120 uint32_t cc_dest;
00121 uint32_t cc_src;
00122 uint32_t cc_result;
00123
00124 int cc_size;
00125
00126 int cc_x;
00127
00128 int interrupt_vector;
00129 int fault_vector;
00130 int trap_vector;
00131
00132
00133
00134
00135
00136
00137
00138
00139 uint32_t sregs[4][16];
00140
00141
00142
00143
00144 uint32_t mmu_rand_lfsr;
00145
00146
00147
00148
00149
00150
00151
00152 struct
00153 {
00154 uint32_t hi;
00155 uint32_t lo;
00156 } tlbsets[2][4][16];
00157
00158 CPU_COMMON
00159 } CPUCRISState;
00160
00161 CPUCRISState *cpu_cris_init(const char *cpu_model);
00162 int cpu_cris_exec(CPUCRISState *s);
00163 void cpu_cris_close(CPUCRISState *s);
00164 void do_interrupt(CPUCRISState *env);
00165
00166
00167
00168 int cpu_cris_signal_handler(int host_signum, void *pinfo,
00169 void *puc);
00170
00171 enum {
00172 CC_OP_DYNAMIC,
00173 CC_OP_FLAGS,
00174 CC_OP_CMP,
00175 CC_OP_MOVE,
00176 CC_OP_ADD,
00177 CC_OP_ADDC,
00178 CC_OP_MCP,
00179 CC_OP_ADDU,
00180 CC_OP_SUB,
00181 CC_OP_SUBU,
00182 CC_OP_NEG,
00183 CC_OP_BTST,
00184 CC_OP_MULS,
00185 CC_OP_MULU,
00186 CC_OP_DSTEP,
00187 CC_OP_BOUND,
00188
00189 CC_OP_OR,
00190 CC_OP_AND,
00191 CC_OP_XOR,
00192 CC_OP_LSL,
00193 CC_OP_LSR,
00194 CC_OP_ASR,
00195 CC_OP_LZ
00196 };
00197
00198
00199 #define TARGET_PAGE_BITS 13
00200 #define MMAP_SHIFT TARGET_PAGE_BITS
00201
00202 #define CPUState CPUCRISState
00203 #define cpu_init cpu_cris_init
00204 #define cpu_exec cpu_cris_exec
00205 #define cpu_gen_code cpu_cris_gen_code
00206 #define cpu_signal_handler cpu_cris_signal_handler
00207
00208 #define CPU_SAVE_VERSION 1
00209
00210
00211 #define MMU_MODE0_SUFFIX _kernel
00212 #define MMU_MODE1_SUFFIX _user
00213 #define MMU_USER_IDX 1
00214 static inline int cpu_mmu_index (CPUState *env)
00215 {
00216 return !!(env->pregs[PR_CCS] & U_FLAG);
00217 }
00218
00219 int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
00220 int mmu_idx, int is_softmmu);
00221
00222 #if defined(CONFIG_USER_ONLY)
00223 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
00224 {
00225 if (newsp)
00226 env->regs[14] = newsp;
00227 env->regs[10] = 0;
00228 }
00229 #endif
00230
00231 static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
00232 {
00233 env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
00234 }
00235
00236
00237 #define SFR_RW_GC_CFG 0][0
00238 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
00239 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
00240 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
00241 #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
00242 #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
00243 #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
00244 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
00245
00246 #include "cpu-all.h"
00247 #include "exec-all.h"
00248
00249 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
00250 {
00251 env->pc = tb->pc;
00252 }
00253
00254 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
00255 target_ulong *cs_base, int *flags)
00256 {
00257 *pc = env->pc;
00258 *cs_base = 0;
00259 *flags = env->dslot |
00260 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG | X_FLAG));
00261 }
00262
00263 #endif