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00020 #ifndef hw_omap_h
00021 # define hw_omap_h "omap.h"
00022
00023 # define OMAP_EMIFS_BASE 0x00000000
00024 # define OMAP2_Q0_BASE 0x00000000
00025 # define OMAP_CS0_BASE 0x00000000
00026 # define OMAP_CS1_BASE 0x04000000
00027 # define OMAP_CS2_BASE 0x08000000
00028 # define OMAP_CS3_BASE 0x0c000000
00029 # define OMAP_EMIFF_BASE 0x10000000
00030 # define OMAP_IMIF_BASE 0x20000000
00031 # define OMAP_LOCALBUS_BASE 0x30000000
00032 # define OMAP2_Q1_BASE 0x40000000
00033 # define OMAP2_L4_BASE 0x48000000
00034 # define OMAP2_SRAM_BASE 0x40200000
00035 # define OMAP2_L3_BASE 0x68000000
00036 # define OMAP2_Q2_BASE 0x80000000
00037 # define OMAP2_Q3_BASE 0xc0000000
00038 # define OMAP_MPUI_BASE 0xe1000000
00039
00040 # define OMAP730_SRAM_SIZE 0x00032000
00041 # define OMAP15XX_SRAM_SIZE 0x00030000
00042 # define OMAP16XX_SRAM_SIZE 0x00004000
00043 # define OMAP1611_SRAM_SIZE 0x0003e800
00044 # define OMAP242X_SRAM_SIZE 0x000a0000
00045 # define OMAP243X_SRAM_SIZE 0x00010000
00046 # define OMAP_CS0_SIZE 0x04000000
00047 # define OMAP_CS1_SIZE 0x04000000
00048 # define OMAP_CS2_SIZE 0x04000000
00049 # define OMAP_CS3_SIZE 0x04000000
00050
00051
00052 struct omap_mpu_state_s;
00053 typedef struct clk *omap_clk;
00054 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
00055 void omap_clk_init(struct omap_mpu_state_s *mpu);
00056 void omap_clk_adduser(struct clk *clk, qemu_irq user);
00057 void omap_clk_get(omap_clk clk);
00058 void omap_clk_put(omap_clk clk);
00059 void omap_clk_onoff(omap_clk clk, int on);
00060 void omap_clk_canidle(omap_clk clk, int can);
00061 void omap_clk_setrate(omap_clk clk, int divide, int multiply);
00062 int64_t omap_clk_getrate(omap_clk clk);
00063 void omap_clk_reparent(omap_clk clk, omap_clk parent);
00064
00065
00066 struct omap_l4_s;
00067 struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);
00068
00069 struct omap_target_agent_s;
00070 struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs);
00071 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
00072 int iotype);
00073 # define l4_register_io_memory cpu_register_io_memory
00074
00075 struct omap_intr_handler_s;
00076 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
00077 unsigned long size, unsigned char nbanks, qemu_irq **pins,
00078 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
00079 struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
00080 int size, int nbanks, qemu_irq **pins,
00081 qemu_irq parent_irq, qemu_irq parent_fiq,
00082 omap_clk fclk, omap_clk iclk);
00083 void omap_inth_reset(struct omap_intr_handler_s *s);
00084
00085 struct omap_prcm_s;
00086 struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
00087 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
00088 struct omap_mpu_state_s *mpu);
00089
00090 struct omap_sysctl_s;
00091 struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
00092 omap_clk iclk, struct omap_mpu_state_s *mpu);
00093
00094 struct omap_sdrc_s;
00095 struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
00096
00097 struct omap_gpmc_s;
00098 struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
00099 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
00100 void (*base_upd)(void *opaque, target_phys_addr_t new),
00101 void (*unmap)(void *opaque), void *opaque);
00102
00103
00104
00105
00106
00107 # define OMAP_INT_CAMERA 1
00108 # define OMAP_INT_FIQ 3
00109 # define OMAP_INT_RTDX 6
00110 # define OMAP_INT_DSP_MMU_ABORT 7
00111 # define OMAP_INT_HOST 8
00112 # define OMAP_INT_ABORT 9
00113 # define OMAP_INT_BRIDGE_PRIV 13
00114 # define OMAP_INT_GPIO_BANK1 14
00115 # define OMAP_INT_UART3 15
00116 # define OMAP_INT_TIMER3 16
00117 # define OMAP_INT_DMA_CH0_6 19
00118 # define OMAP_INT_DMA_CH1_7 20
00119 # define OMAP_INT_DMA_CH2_8 21
00120 # define OMAP_INT_DMA_CH3 22
00121 # define OMAP_INT_DMA_CH4 23
00122 # define OMAP_INT_DMA_CH5 24
00123 # define OMAP_INT_DMA_LCD 25
00124 # define OMAP_INT_TIMER1 26
00125 # define OMAP_INT_WD_TIMER 27
00126 # define OMAP_INT_BRIDGE_PUB 28
00127 # define OMAP_INT_TIMER2 30
00128 # define OMAP_INT_LCD_CTRL 31
00129
00130
00131
00132
00133 # define OMAP_INT_15XX_IH2_IRQ 0
00134 # define OMAP_INT_15XX_LB_MMU 17
00135 # define OMAP_INT_15XX_LOCAL_BUS 29
00136
00137
00138
00139
00140 # define OMAP_INT_1510_SPI_TX 4
00141 # define OMAP_INT_1510_SPI_RX 5
00142 # define OMAP_INT_1510_DSP_MAILBOX1 10
00143 # define OMAP_INT_1510_DSP_MAILBOX2 11
00144
00145
00146
00147
00148 # define OMAP_INT_310_McBSP2_TX 4
00149 # define OMAP_INT_310_McBSP2_RX 5
00150 # define OMAP_INT_310_HSB_MAILBOX1 12
00151 # define OMAP_INT_310_HSAB_MMU 18
00152
00153
00154
00155
00156 # define OMAP_INT_1610_IH2_IRQ 0
00157 # define OMAP_INT_1610_IH2_FIQ 2
00158 # define OMAP_INT_1610_McBSP2_TX 4
00159 # define OMAP_INT_1610_McBSP2_RX 5
00160 # define OMAP_INT_1610_DSP_MAILBOX1 10
00161 # define OMAP_INT_1610_DSP_MAILBOX2 11
00162 # define OMAP_INT_1610_LCD_LINE 12
00163 # define OMAP_INT_1610_GPTIMER1 17
00164 # define OMAP_INT_1610_GPTIMER2 18
00165 # define OMAP_INT_1610_SSR_FIFO_0 29
00166
00167
00168
00169
00170 # define OMAP_INT_730_IH2_FIQ 0
00171 # define OMAP_INT_730_IH2_IRQ 1
00172 # define OMAP_INT_730_USB_NON_ISO 2
00173 # define OMAP_INT_730_USB_ISO 3
00174 # define OMAP_INT_730_ICR 4
00175 # define OMAP_INT_730_EAC 5
00176 # define OMAP_INT_730_GPIO_BANK1 6
00177 # define OMAP_INT_730_GPIO_BANK2 7
00178 # define OMAP_INT_730_GPIO_BANK3 8
00179 # define OMAP_INT_730_McBSP2TX 10
00180 # define OMAP_INT_730_McBSP2RX 11
00181 # define OMAP_INT_730_McBSP2RX_OVF 12
00182 # define OMAP_INT_730_LCD_LINE 14
00183 # define OMAP_INT_730_GSM_PROTECT 15
00184 # define OMAP_INT_730_TIMER3 16
00185 # define OMAP_INT_730_GPIO_BANK5 17
00186 # define OMAP_INT_730_GPIO_BANK6 18
00187 # define OMAP_INT_730_SPGIO_WR 29
00188
00189
00190
00191
00192 # define OMAP_INT_KEYBOARD 1
00193 # define OMAP_INT_uWireTX 2
00194 # define OMAP_INT_uWireRX 3
00195 # define OMAP_INT_I2C 4
00196 # define OMAP_INT_MPUIO 5
00197 # define OMAP_INT_USB_HHC_1 6
00198 # define OMAP_INT_McBSP3TX 10
00199 # define OMAP_INT_McBSP3RX 11
00200 # define OMAP_INT_McBSP1TX 12
00201 # define OMAP_INT_McBSP1RX 13
00202 # define OMAP_INT_UART1 14
00203 # define OMAP_INT_UART2 15
00204 # define OMAP_INT_USB_W2FC 20
00205 # define OMAP_INT_1WIRE 21
00206 # define OMAP_INT_OS_TIMER 22
00207 # define OMAP_INT_OQN 23
00208 # define OMAP_INT_GAUGE_32K 24
00209 # define OMAP_INT_RTC_TIMER 25
00210 # define OMAP_INT_RTC_ALARM 26
00211 # define OMAP_INT_DSP_MMU 28
00212
00213
00214
00215
00216 # define OMAP_INT_1510_BT_MCSI1TX 16
00217 # define OMAP_INT_1510_BT_MCSI1RX 17
00218 # define OMAP_INT_1510_SoSSI_MATCH 19
00219 # define OMAP_INT_1510_MEM_STICK 27
00220 # define OMAP_INT_1510_COM_SPI_RO 31
00221
00222
00223
00224
00225 # define OMAP_INT_310_FAC 0
00226 # define OMAP_INT_310_USB_HHC_2 7
00227 # define OMAP_INT_310_MCSI1_FE 16
00228 # define OMAP_INT_310_MCSI2_FE 17
00229 # define OMAP_INT_310_USB_W2FC_ISO 29
00230 # define OMAP_INT_310_USB_W2FC_NON_ISO 30
00231 # define OMAP_INT_310_McBSP2RX_OF 31
00232
00233
00234
00235
00236 # define OMAP_INT_1610_FAC 0
00237 # define OMAP_INT_1610_USB_HHC_2 7
00238 # define OMAP_INT_1610_USB_OTG 8
00239 # define OMAP_INT_1610_SoSSI 9
00240 # define OMAP_INT_1610_BT_MCSI1TX 16
00241 # define OMAP_INT_1610_BT_MCSI1RX 17
00242 # define OMAP_INT_1610_SoSSI_MATCH 19
00243 # define OMAP_INT_1610_MEM_STICK 27
00244 # define OMAP_INT_1610_McBSP2RX_OF 31
00245 # define OMAP_INT_1610_STI 32
00246 # define OMAP_INT_1610_STI_WAKEUP 33
00247 # define OMAP_INT_1610_GPTIMER3 34
00248 # define OMAP_INT_1610_GPTIMER4 35
00249 # define OMAP_INT_1610_GPTIMER5 36
00250 # define OMAP_INT_1610_GPTIMER6 37
00251 # define OMAP_INT_1610_GPTIMER7 38
00252 # define OMAP_INT_1610_GPTIMER8 39
00253 # define OMAP_INT_1610_GPIO_BANK2 40
00254 # define OMAP_INT_1610_GPIO_BANK3 41
00255 # define OMAP_INT_1610_MMC2 42
00256 # define OMAP_INT_1610_CF 43
00257 # define OMAP_INT_1610_WAKE_UP_REQ 46
00258 # define OMAP_INT_1610_GPIO_BANK4 48
00259 # define OMAP_INT_1610_SPI 49
00260 # define OMAP_INT_1610_DMA_CH6 53
00261 # define OMAP_INT_1610_DMA_CH7 54
00262 # define OMAP_INT_1610_DMA_CH8 55
00263 # define OMAP_INT_1610_DMA_CH9 56
00264 # define OMAP_INT_1610_DMA_CH10 57
00265 # define OMAP_INT_1610_DMA_CH11 58
00266 # define OMAP_INT_1610_DMA_CH12 59
00267 # define OMAP_INT_1610_DMA_CH13 60
00268 # define OMAP_INT_1610_DMA_CH14 61
00269 # define OMAP_INT_1610_DMA_CH15 62
00270 # define OMAP_INT_1610_NAND 63
00271
00272
00273
00274
00275 # define OMAP_INT_730_HW_ERRORS 0
00276 # define OMAP_INT_730_NFIQ_PWR_FAIL 1
00277 # define OMAP_INT_730_CFCD 2
00278 # define OMAP_INT_730_CFIREQ 3
00279 # define OMAP_INT_730_I2C 4
00280 # define OMAP_INT_730_PCC 5
00281 # define OMAP_INT_730_MPU_EXT_NIRQ 6
00282 # define OMAP_INT_730_SPI_100K_1 7
00283 # define OMAP_INT_730_SYREN_SPI 8
00284 # define OMAP_INT_730_VLYNQ 9
00285 # define OMAP_INT_730_GPIO_BANK4 10
00286 # define OMAP_INT_730_McBSP1TX 11
00287 # define OMAP_INT_730_McBSP1RX 12
00288 # define OMAP_INT_730_McBSP1RX_OF 13
00289 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
00290 # define OMAP_INT_730_UART_MODEM_1 15
00291 # define OMAP_INT_730_MCSI 16
00292 # define OMAP_INT_730_uWireTX 17
00293 # define OMAP_INT_730_uWireRX 18
00294 # define OMAP_INT_730_SMC_CD 19
00295 # define OMAP_INT_730_SMC_IREQ 20
00296 # define OMAP_INT_730_HDQ_1WIRE 21
00297 # define OMAP_INT_730_TIMER32K 22
00298 # define OMAP_INT_730_MMC_SDIO 23
00299 # define OMAP_INT_730_UPLD 24
00300 # define OMAP_INT_730_USB_HHC_1 27
00301 # define OMAP_INT_730_USB_HHC_2 28
00302 # define OMAP_INT_730_USB_GENI 29
00303 # define OMAP_INT_730_USB_OTG 30
00304 # define OMAP_INT_730_CAMERA_IF 31
00305 # define OMAP_INT_730_RNG 32
00306 # define OMAP_INT_730_DUAL_MODE_TIMER 33
00307 # define OMAP_INT_730_DBB_RF_EN 34
00308 # define OMAP_INT_730_MPUIO_KEYPAD 35
00309 # define OMAP_INT_730_SHA1_MD5 36
00310 # define OMAP_INT_730_SPI_100K_2 37
00311 # define OMAP_INT_730_RNG_IDLE 38
00312 # define OMAP_INT_730_MPUIO 39
00313 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
00314 # define OMAP_INT_730_LLPC_OE_FALLING 41
00315 # define OMAP_INT_730_LLPC_OE_RISING 42
00316 # define OMAP_INT_730_LLPC_VSYNC 43
00317 # define OMAP_INT_730_WAKE_UP_REQ 46
00318 # define OMAP_INT_730_DMA_CH6 53
00319 # define OMAP_INT_730_DMA_CH7 54
00320 # define OMAP_INT_730_DMA_CH8 55
00321 # define OMAP_INT_730_DMA_CH9 56
00322 # define OMAP_INT_730_DMA_CH10 57
00323 # define OMAP_INT_730_DMA_CH11 58
00324 # define OMAP_INT_730_DMA_CH12 59
00325 # define OMAP_INT_730_DMA_CH13 60
00326 # define OMAP_INT_730_DMA_CH14 61
00327 # define OMAP_INT_730_DMA_CH15 62
00328 # define OMAP_INT_730_NAND 63
00329
00330
00331
00332
00333 # define OMAP_INT_24XX_STI 4
00334 # define OMAP_INT_24XX_SYS_NIRQ 7
00335 # define OMAP_INT_24XX_L3_IRQ 10
00336 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11
00337 # define OMAP_INT_24XX_SDMA_IRQ0 12
00338 # define OMAP_INT_24XX_SDMA_IRQ1 13
00339 # define OMAP_INT_24XX_SDMA_IRQ2 14
00340 # define OMAP_INT_24XX_SDMA_IRQ3 15
00341 # define OMAP_INT_243X_MCBSP2_IRQ 16
00342 # define OMAP_INT_243X_MCBSP3_IRQ 17
00343 # define OMAP_INT_243X_MCBSP4_IRQ 18
00344 # define OMAP_INT_243X_MCBSP5_IRQ 19
00345 # define OMAP_INT_24XX_GPMC_IRQ 20
00346 # define OMAP_INT_24XX_GUFFAW_IRQ 21
00347 # define OMAP_INT_24XX_IVA_IRQ 22
00348 # define OMAP_INT_24XX_EAC_IRQ 23
00349 # define OMAP_INT_24XX_CAM_IRQ 24
00350 # define OMAP_INT_24XX_DSS_IRQ 25
00351 # define OMAP_INT_24XX_MAIL_U0_MPU 26
00352 # define OMAP_INT_24XX_DSP_UMA 27
00353 # define OMAP_INT_24XX_DSP_MMU 28
00354 # define OMAP_INT_24XX_GPIO_BANK1 29
00355 # define OMAP_INT_24XX_GPIO_BANK2 30
00356 # define OMAP_INT_24XX_GPIO_BANK3 31
00357 # define OMAP_INT_24XX_GPIO_BANK4 32
00358 # define OMAP_INT_243X_GPIO_BANK5 33
00359 # define OMAP_INT_24XX_MAIL_U3_MPU 34
00360 # define OMAP_INT_24XX_WDT3 35
00361 # define OMAP_INT_24XX_WDT4 36
00362 # define OMAP_INT_24XX_GPTIMER1 37
00363 # define OMAP_INT_24XX_GPTIMER2 38
00364 # define OMAP_INT_24XX_GPTIMER3 39
00365 # define OMAP_INT_24XX_GPTIMER4 40
00366 # define OMAP_INT_24XX_GPTIMER5 41
00367 # define OMAP_INT_24XX_GPTIMER6 42
00368 # define OMAP_INT_24XX_GPTIMER7 43
00369 # define OMAP_INT_24XX_GPTIMER8 44
00370 # define OMAP_INT_24XX_GPTIMER9 45
00371 # define OMAP_INT_24XX_GPTIMER10 46
00372 # define OMAP_INT_24XX_GPTIMER11 47
00373 # define OMAP_INT_24XX_GPTIMER12 48
00374 # define OMAP_INT_24XX_PKA_IRQ 50
00375 # define OMAP_INT_24XX_SHA1MD5_IRQ 51
00376 # define OMAP_INT_24XX_RNG_IRQ 52
00377 # define OMAP_INT_24XX_MG_IRQ 53
00378 # define OMAP_INT_24XX_I2C1_IRQ 56
00379 # define OMAP_INT_24XX_I2C2_IRQ 57
00380 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
00381 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
00382 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
00383 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
00384 # define OMAP_INT_243X_MCBSP1_IRQ 64
00385 # define OMAP_INT_24XX_MCSPI1_IRQ 65
00386 # define OMAP_INT_24XX_MCSPI2_IRQ 66
00387 # define OMAP_INT_24XX_SSI1_IRQ0 67
00388 # define OMAP_INT_24XX_SSI1_IRQ1 68
00389 # define OMAP_INT_24XX_SSI2_IRQ0 69
00390 # define OMAP_INT_24XX_SSI2_IRQ1 70
00391 # define OMAP_INT_24XX_SSI_GDD_IRQ 71
00392 # define OMAP_INT_24XX_UART1_IRQ 72
00393 # define OMAP_INT_24XX_UART2_IRQ 73
00394 # define OMAP_INT_24XX_UART3_IRQ 74
00395 # define OMAP_INT_24XX_USB_IRQ_GEN 75
00396 # define OMAP_INT_24XX_USB_IRQ_NISO 76
00397 # define OMAP_INT_24XX_USB_IRQ_ISO 77
00398 # define OMAP_INT_24XX_USB_IRQ_HGEN 78
00399 # define OMAP_INT_24XX_USB_IRQ_HSOF 79
00400 # define OMAP_INT_24XX_USB_IRQ_OTG 80
00401 # define OMAP_INT_24XX_VLYNQ_IRQ 81
00402 # define OMAP_INT_24XX_MMC_IRQ 83
00403 # define OMAP_INT_24XX_MS_IRQ 84
00404 # define OMAP_INT_24XX_FAC_IRQ 85
00405 # define OMAP_INT_24XX_MCSPI3_IRQ 91
00406 # define OMAP_INT_243X_HS_USB_MC 92
00407 # define OMAP_INT_243X_HS_USB_DMA 93
00408 # define OMAP_INT_243X_CARKIT 94
00409 # define OMAP_INT_34XX_GPTIMER12 95
00410
00411
00412 enum omap_dma_model {
00413 omap_dma_3_0,
00414 omap_dma_3_1,
00415 omap_dma_3_2,
00416 omap_dma_4,
00417 };
00418
00419 struct soc_dma_s;
00420 struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
00421 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
00422 enum omap_dma_model model);
00423 struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
00424 struct omap_mpu_state_s *mpu, int fifo,
00425 int chans, omap_clk iclk, omap_clk fclk);
00426 void omap_dma_reset(struct soc_dma_s *s);
00427
00428 struct dma_irq_map {
00429 int ih;
00430 int intr;
00431 };
00432
00433
00434 enum omap_dma_port {
00435 emiff = 0,
00436 emifs,
00437 imif,
00438 tipb,
00439 local,
00440 tipb_mpui,
00441 __omap_dma_port_last,
00442 };
00443
00444 typedef enum {
00445 constant = 0,
00446 post_incremented,
00447 single_index,
00448 double_index,
00449 } omap_dma_addressing_t;
00450
00451
00452 struct omap_dma_lcd_channel_s {
00453 enum omap_dma_port src;
00454 target_phys_addr_t src_f1_top;
00455 target_phys_addr_t src_f1_bottom;
00456 target_phys_addr_t src_f2_top;
00457 target_phys_addr_t src_f2_bottom;
00458
00459
00460 unsigned char brust_f1;
00461 unsigned char pack_f1;
00462 unsigned char data_type_f1;
00463 unsigned char brust_f2;
00464 unsigned char pack_f2;
00465 unsigned char data_type_f2;
00466 unsigned char end_prog;
00467 unsigned char repeat;
00468 unsigned char auto_init;
00469 unsigned char priority;
00470 unsigned char fs;
00471 unsigned char running;
00472 unsigned char bs;
00473 unsigned char omap_3_1_compatible_disable;
00474 unsigned char dst;
00475 unsigned char lch_type;
00476 int16_t element_index_f1;
00477 int16_t element_index_f2;
00478 int32_t frame_index_f1;
00479 int32_t frame_index_f2;
00480 uint16_t elements_f1;
00481 uint16_t frames_f1;
00482 uint16_t elements_f2;
00483 uint16_t frames_f2;
00484 omap_dma_addressing_t mode_f1;
00485 omap_dma_addressing_t mode_f2;
00486
00487
00488 int interrupts;
00489 int condition;
00490 int dual;
00491
00492 int current_frame;
00493 ram_addr_t phys_framebuffer[2];
00494 qemu_irq irq;
00495 struct omap_mpu_state_s *mpu;
00496 } *omap_dma_get_lcdch(struct soc_dma_s *s);
00497
00498
00499
00500
00501
00502 # define OMAP_DMA_NO_DEVICE 0
00503 # define OMAP_DMA_MCSI1_TX 1
00504 # define OMAP_DMA_MCSI1_RX 2
00505 # define OMAP_DMA_I2C_RX 3
00506 # define OMAP_DMA_I2C_TX 4
00507 # define OMAP_DMA_EXT_NDMA_REQ0 5
00508 # define OMAP_DMA_EXT_NDMA_REQ1 6
00509 # define OMAP_DMA_UWIRE_TX 7
00510 # define OMAP_DMA_MCBSP1_TX 8
00511 # define OMAP_DMA_MCBSP1_RX 9
00512 # define OMAP_DMA_MCBSP3_TX 10
00513 # define OMAP_DMA_MCBSP3_RX 11
00514 # define OMAP_DMA_UART1_TX 12
00515 # define OMAP_DMA_UART1_RX 13
00516 # define OMAP_DMA_UART2_TX 14
00517 # define OMAP_DMA_UART2_RX 15
00518 # define OMAP_DMA_MCBSP2_TX 16
00519 # define OMAP_DMA_MCBSP2_RX 17
00520 # define OMAP_DMA_UART3_TX 18
00521 # define OMAP_DMA_UART3_RX 19
00522 # define OMAP_DMA_CAMERA_IF_RX 20
00523 # define OMAP_DMA_MMC_TX 21
00524 # define OMAP_DMA_MMC_RX 22
00525 # define OMAP_DMA_NAND 23
00526 # define OMAP_DMA_IRQ_LCD_LINE 24
00527 # define OMAP_DMA_MEMORY_STICK 25
00528 # define OMAP_DMA_USB_W2FC_RX0 26
00529 # define OMAP_DMA_USB_W2FC_RX1 27
00530 # define OMAP_DMA_USB_W2FC_RX2 28
00531 # define OMAP_DMA_USB_W2FC_TX0 29
00532 # define OMAP_DMA_USB_W2FC_TX1 30
00533 # define OMAP_DMA_USB_W2FC_TX2 31
00534
00535
00536 # define OMAP_DMA_CRYPTO_DES_IN 32
00537 # define OMAP_DMA_SPI_TX 33
00538 # define OMAP_DMA_SPI_RX 34
00539 # define OMAP_DMA_CRYPTO_HASH 35
00540 # define OMAP_DMA_CCP_ATTN 36
00541 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
00542 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38
00543 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39
00544 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40
00545 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41
00546 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42
00547 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43
00548 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44
00549 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45
00550 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46
00551 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47
00552 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48
00553 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49
00554 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50
00555 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51
00556 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52
00557 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53
00558 # define OMAP_DMA_MMC2_TX 54
00559 # define OMAP_DMA_MMC2_RX 55
00560 # define OMAP_DMA_CRYPTO_DES_OUT 56
00561
00562
00563
00564
00565 # define OMAP24XX_DMA_NO_DEVICE 0
00566 # define OMAP24XX_DMA_XTI_DMA 1
00567 # define OMAP24XX_DMA_EXT_DMAREQ0 2
00568 # define OMAP24XX_DMA_EXT_DMAREQ1 3
00569 # define OMAP24XX_DMA_GPMC 4
00570 # define OMAP24XX_DMA_GFX 5
00571 # define OMAP24XX_DMA_DSS 6
00572 # define OMAP24XX_DMA_VLYNQ_TX 7
00573 # define OMAP24XX_DMA_CWT 8
00574 # define OMAP24XX_DMA_AES_TX 9
00575 # define OMAP24XX_DMA_AES_RX 10
00576 # define OMAP24XX_DMA_DES_TX 11
00577 # define OMAP24XX_DMA_DES_RX 12
00578 # define OMAP24XX_DMA_SHA1MD5_RX 13
00579 # define OMAP24XX_DMA_EXT_DMAREQ2 14
00580 # define OMAP24XX_DMA_EXT_DMAREQ3 15
00581 # define OMAP24XX_DMA_EXT_DMAREQ4 16
00582 # define OMAP24XX_DMA_EAC_AC_RD 17
00583 # define OMAP24XX_DMA_EAC_AC_WR 18
00584 # define OMAP24XX_DMA_EAC_MD_UL_RD 19
00585 # define OMAP24XX_DMA_EAC_MD_UL_WR 20
00586 # define OMAP24XX_DMA_EAC_MD_DL_RD 21
00587 # define OMAP24XX_DMA_EAC_MD_DL_WR 22
00588 # define OMAP24XX_DMA_EAC_BT_UL_RD 23
00589 # define OMAP24XX_DMA_EAC_BT_UL_WR 24
00590 # define OMAP24XX_DMA_EAC_BT_DL_RD 25
00591 # define OMAP24XX_DMA_EAC_BT_DL_WR 26
00592 # define OMAP24XX_DMA_I2C1_TX 27
00593 # define OMAP24XX_DMA_I2C1_RX 28
00594 # define OMAP24XX_DMA_I2C2_TX 29
00595 # define OMAP24XX_DMA_I2C2_RX 30
00596 # define OMAP24XX_DMA_MCBSP1_TX 31
00597 # define OMAP24XX_DMA_MCBSP1_RX 32
00598 # define OMAP24XX_DMA_MCBSP2_TX 33
00599 # define OMAP24XX_DMA_MCBSP2_RX 34
00600 # define OMAP24XX_DMA_SPI1_TX0 35
00601 # define OMAP24XX_DMA_SPI1_RX0 36
00602 # define OMAP24XX_DMA_SPI1_TX1 37
00603 # define OMAP24XX_DMA_SPI1_RX1 38
00604 # define OMAP24XX_DMA_SPI1_TX2 39
00605 # define OMAP24XX_DMA_SPI1_RX2 40
00606 # define OMAP24XX_DMA_SPI1_TX3 41
00607 # define OMAP24XX_DMA_SPI1_RX3 42
00608 # define OMAP24XX_DMA_SPI2_TX0 43
00609 # define OMAP24XX_DMA_SPI2_RX0 44
00610 # define OMAP24XX_DMA_SPI2_TX1 45
00611 # define OMAP24XX_DMA_SPI2_RX1 46
00612
00613 # define OMAP24XX_DMA_UART1_TX 49
00614 # define OMAP24XX_DMA_UART1_RX 50
00615 # define OMAP24XX_DMA_UART2_TX 51
00616 # define OMAP24XX_DMA_UART2_RX 52
00617 # define OMAP24XX_DMA_UART3_TX 53
00618 # define OMAP24XX_DMA_UART3_RX 54
00619 # define OMAP24XX_DMA_USB_W2FC_TX0 55
00620 # define OMAP24XX_DMA_USB_W2FC_RX0 56
00621 # define OMAP24XX_DMA_USB_W2FC_TX1 57
00622 # define OMAP24XX_DMA_USB_W2FC_RX1 58
00623 # define OMAP24XX_DMA_USB_W2FC_TX2 59
00624 # define OMAP24XX_DMA_USB_W2FC_RX2 60
00625 # define OMAP24XX_DMA_MMC1_TX 61
00626 # define OMAP24XX_DMA_MMC1_RX 62
00627 # define OMAP24XX_DMA_MS 63
00628 # define OMAP24XX_DMA_EXT_DMAREQ5 64
00629
00630
00631 struct omap_mpu_timer_s;
00632 struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
00633 qemu_irq irq, omap_clk clk);
00634
00635 struct omap_gp_timer_s;
00636 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
00637 qemu_irq irq, omap_clk fclk, omap_clk iclk);
00638
00639 struct omap_watchdog_timer_s;
00640 struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
00641 qemu_irq irq, omap_clk clk);
00642
00643 struct omap_32khz_timer_s;
00644 struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
00645 qemu_irq irq, omap_clk clk);
00646
00647 void omap_synctimer_init(struct omap_target_agent_s *ta,
00648 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
00649
00650 struct omap_tipb_bridge_s;
00651 struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
00652 qemu_irq abort_irq, omap_clk clk);
00653
00654 struct omap_uart_s;
00655 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
00656 qemu_irq irq, omap_clk fclk, omap_clk iclk,
00657 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
00658 struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
00659 qemu_irq irq, omap_clk fclk, omap_clk iclk,
00660 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
00661 void omap_uart_reset(struct omap_uart_s *s);
00662 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
00663
00664 struct omap_mpuio_s;
00665 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
00666 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
00667 omap_clk clk);
00668 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
00669 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
00670 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
00671
00672 struct omap_gpio_s;
00673 struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
00674 qemu_irq irq, omap_clk clk);
00675 qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
00676 void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler);
00677
00678 struct omap_gpif_s;
00679 struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
00680 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules);
00681 qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start);
00682 void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler);
00683
00684 struct uwire_slave_s {
00685 uint16_t (*receive)(void *opaque);
00686 void (*send)(void *opaque, uint16_t data);
00687 void *opaque;
00688 };
00689 struct omap_uwire_s;
00690 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
00691 qemu_irq *irq, qemu_irq dma, omap_clk clk);
00692 void omap_uwire_attach(struct omap_uwire_s *s,
00693 struct uwire_slave_s *slave, int chipselect);
00694
00695 struct omap_mcspi_s;
00696 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
00697 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
00698 void omap_mcspi_attach(struct omap_mcspi_s *s,
00699 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
00700 int chipselect);
00701
00702 struct omap_rtc_s;
00703 struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
00704 qemu_irq *irq, omap_clk clk);
00705
00706 struct i2s_codec_s {
00707 void *opaque;
00708
00709
00710
00711
00712 void (*set_rate)(void *opaque, int in, int out);
00713
00714 void (*tx_swallow)(void *opaque);
00715 qemu_irq rx_swallow;
00716 qemu_irq tx_start;
00717
00718 int tx_rate;
00719 int cts;
00720 int rx_rate;
00721 int rts;
00722
00723 struct i2s_fifo_s {
00724 uint8_t *fifo;
00725 int len;
00726 int start;
00727 int size;
00728 } in, out;
00729 };
00730 struct omap_mcbsp_s;
00731 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
00732 qemu_irq *irq, qemu_irq *dma, omap_clk clk);
00733 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave);
00734
00735 struct omap_lpg_s;
00736 struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
00737
00738 void omap_tap_init(struct omap_target_agent_s *ta,
00739 struct omap_mpu_state_s *mpu);
00740
00741 struct omap_eac_s;
00742 struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
00743 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
00744
00745
00746 struct omap_lcd_panel_s;
00747 void omap_lcdc_reset(struct omap_lcd_panel_s *s);
00748 struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
00749 struct omap_dma_lcd_channel_s *dma,
00750 ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
00751
00752
00753 struct rfbi_chip_s {
00754 void *opaque;
00755 void (*write)(void *opaque, int dc, uint16_t value);
00756 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
00757 uint16_t (*read)(void *opaque, int dc);
00758 };
00759 struct omap_dss_s;
00760 void omap_dss_reset(struct omap_dss_s *s);
00761 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
00762 target_phys_addr_t l3_base,
00763 qemu_irq irq, qemu_irq drq,
00764 omap_clk fck1, omap_clk fck2, omap_clk ck54m,
00765 omap_clk ick1, omap_clk ick2);
00766 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
00767
00768
00769 struct omap_mmc_s;
00770 struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
00771 BlockDriverState *bd,
00772 qemu_irq irq, qemu_irq dma[], omap_clk clk);
00773 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
00774 BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
00775 omap_clk fclk, omap_clk iclk);
00776 void omap_mmc_reset(struct omap_mmc_s *s);
00777 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
00778 void omap_mmc_enable(struct omap_mmc_s *s, int enable);
00779
00780
00781 struct omap_i2c_s;
00782 struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
00783 qemu_irq irq, qemu_irq *dma, omap_clk clk);
00784 struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
00785 qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
00786 void omap_i2c_reset(struct omap_i2c_s *s);
00787 i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
00788
00789 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
00790 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
00791 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
00792 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
00793 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
00794 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
00795 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
00796 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
00797
00798 # define cpu_is_omap15xx(cpu) \
00799 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
00800 # define cpu_is_omap16xx(cpu) \
00801 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
00802 # define cpu_is_omap24xx(cpu) \
00803 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
00804
00805 # define cpu_class_omap1(cpu) \
00806 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
00807 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
00808 # define cpu_class_omap3(cpu) cpu_is_omap3430(cpu)
00809
00810 struct omap_mpu_state_s {
00811 enum omap_mpu_model {
00812 omap310,
00813 omap1510,
00814 omap1610,
00815 omap1710,
00816 omap2410,
00817 omap2420,
00818 omap2422,
00819 omap2423,
00820 omap2430,
00821 omap3430,
00822 } mpu_model;
00823
00824 CPUState *env;
00825
00826 qemu_irq *irq[2];
00827 qemu_irq *drq;
00828
00829 qemu_irq wakeup;
00830
00831 struct omap_dma_port_if_s {
00832 uint32_t (*read[3])(struct omap_mpu_state_s *s,
00833 target_phys_addr_t offset);
00834 void (*write[3])(struct omap_mpu_state_s *s,
00835 target_phys_addr_t offset, uint32_t value);
00836 int (*addr_valid)(struct omap_mpu_state_s *s,
00837 target_phys_addr_t addr);
00838 } port[__omap_dma_port_last];
00839
00840 unsigned long sdram_size;
00841 unsigned long sram_size;
00842
00843
00844 struct omap_uart_s *uart[3];
00845
00846 struct omap_gpio_s *gpio;
00847
00848 struct omap_mcbsp_s *mcbsp1;
00849 struct omap_mcbsp_s *mcbsp3;
00850
00851
00852 struct omap_32khz_timer_s *os_timer;
00853
00854 struct omap_mmc_s *mmc;
00855
00856 struct omap_mpuio_s *mpuio;
00857
00858 struct omap_uwire_s *microwire;
00859
00860 struct {
00861 uint8_t output;
00862 uint8_t level;
00863 uint8_t enable;
00864 int clk;
00865 } pwl;
00866
00867 struct {
00868 uint8_t frc;
00869 uint8_t vrc;
00870 uint8_t gcr;
00871 omap_clk clk;
00872 } pwt;
00873
00874 struct omap_i2c_s *i2c[2];
00875
00876 struct omap_rtc_s *rtc;
00877
00878 struct omap_mcbsp_s *mcbsp2;
00879
00880 struct omap_lpg_s *led[2];
00881
00882
00883 struct omap_intr_handler_s *ih[2];
00884
00885 struct soc_dma_s *dma;
00886
00887 struct omap_mpu_timer_s *timer[3];
00888 struct omap_watchdog_timer_s *wdt;
00889
00890 struct omap_lcd_panel_s *lcd;
00891
00892 uint32_t ulpd_pm_regs[21];
00893 int64_t ulpd_gauge_start;
00894
00895 uint32_t func_mux_ctrl[14];
00896 uint32_t comp_mode_ctrl[1];
00897 uint32_t pull_dwn_ctrl[4];
00898 uint32_t gate_inh_ctrl[1];
00899 uint32_t voltage_ctrl[1];
00900 uint32_t test_dbg_ctrl[1];
00901 uint32_t mod_conf_ctrl[1];
00902 int compat1509;
00903
00904 uint32_t mpui_ctrl;
00905
00906 struct omap_tipb_bridge_s *private_tipb;
00907 struct omap_tipb_bridge_s *public_tipb;
00908
00909 uint32_t tcmi_regs[17];
00910
00911 struct dpll_ctl_s {
00912 uint16_t mode;
00913 omap_clk dpll;
00914 } dpll[3];
00915
00916 omap_clk clks;
00917 struct {
00918 int cold_start;
00919 int clocking_scheme;
00920 uint16_t arm_ckctl;
00921 uint16_t arm_idlect1;
00922 uint16_t arm_idlect2;
00923 uint16_t arm_ewupct;
00924 uint16_t arm_rstct1;
00925 uint16_t arm_rstct2;
00926 uint16_t arm_ckout1;
00927 int dpll1_mode;
00928 uint16_t dsp_idlect1;
00929 uint16_t dsp_idlect2;
00930 uint16_t dsp_rstct2;
00931 } clkm;
00932
00933
00934 struct omap_l4_s *l4;
00935
00936 struct omap_gp_timer_s *gptimer[12];
00937
00938 struct omap_synctimer_s {
00939 uint32_t val;
00940 uint16_t readh;
00941 } synctimer;
00942
00943 struct omap_prcm_s *prcm;
00944 struct omap_sdrc_s *sdrc;
00945 struct omap_gpmc_s *gpmc;
00946 struct omap_sysctl_s *sysc;
00947
00948 struct omap_gpif_s *gpif;
00949
00950 struct omap_mcspi_s *mcspi[2];
00951
00952 struct omap_dss_s *dss;
00953
00954 struct omap_eac_s *eac;
00955 };
00956
00957
00958 struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
00959 const char *core);
00960
00961
00962 struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
00963 const char *core);
00964
00965 # if TARGET_PHYS_ADDR_BITS == 32
00966 # define OMAP_FMT_plx "%#08x"
00967 # elif TARGET_PHYS_ADDR_BITS == 64
00968 # define OMAP_FMT_plx "%#08" PRIx64
00969 # else
00970 # error TARGET_PHYS_ADDR_BITS undefined
00971 # endif
00972
00973 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
00974 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
00975 uint32_t value);
00976 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
00977 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
00978 uint32_t value);
00979 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
00980 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
00981 uint32_t value);
00982
00983 void omap_mpu_wakeup(void *opaque, int irq, int req);
00984
00985 # define OMAP_BAD_REG(paddr) \
00986 fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \
00987 __FUNCTION__, paddr)
00988 # define OMAP_RO_REG(paddr) \
00989 fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
00990 __FUNCTION__, paddr)
00991
00992
00993
00994 #define OMAP_TAG_CLOCK 0x4f01
00995 #define OMAP_TAG_MMC 0x4f02
00996 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
00997 #define OMAP_TAG_USB 0x4f04
00998 #define OMAP_TAG_LCD 0x4f05
00999 #define OMAP_TAG_GPIO_SWITCH 0x4f06
01000 #define OMAP_TAG_UART 0x4f07
01001 #define OMAP_TAG_FBMEM 0x4f08
01002 #define OMAP_TAG_STI_CONSOLE 0x4f09
01003 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a
01004 #define OMAP_TAG_PARTITION 0x4f0b
01005 #define OMAP_TAG_TEA5761 0x4f10
01006 #define OMAP_TAG_TMP105 0x4f11
01007 #define OMAP_TAG_BOOT_REASON 0x4f80
01008 #define OMAP_TAG_FLASH_PART_STR 0x4f81
01009 #define OMAP_TAG_VERSION_STR 0x4f82
01010
01011 enum {
01012 OMAP_GPIOSW_TYPE_COVER = 0 << 4,
01013 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
01014 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4,
01015 };
01016
01017 #define OMAP_GPIOSW_INVERTED 0x0001
01018 #define OMAP_GPIOSW_OUTPUT 0x0002
01019
01020 # define TCMI_VERBOSE 1
01021
01022
01023 # ifdef TCMI_VERBOSE
01024 # define OMAP_8B_REG(paddr) \
01025 fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
01026 __FUNCTION__, paddr)
01027 # define OMAP_16B_REG(paddr) \
01028 fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
01029 __FUNCTION__, paddr)
01030 # define OMAP_32B_REG(paddr) \
01031 fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
01032 __FUNCTION__, paddr)
01033 # else
01034 # define OMAP_8B_REG(paddr)
01035 # define OMAP_16B_REG(paddr)
01036 # define OMAP_32B_REG(paddr)
01037 # endif
01038
01039 # define OMAP_MPUI_REG_MASK 0x000007ff
01040
01041 # ifdef MEM_VERBOSE
01042 struct io_fn {
01043 CPUReadMemoryFunc **mem_read;
01044 CPUWriteMemoryFunc **mem_write;
01045 void *opaque;
01046 int in;
01047 };
01048
01049 static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
01050 {
01051 struct io_fn *s = opaque;
01052 uint32_t ret;
01053
01054 s->in ++;
01055 ret = s->mem_read[0](s->opaque, addr);
01056 s->in --;
01057 if (!s->in)
01058 fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
01059 return ret;
01060 }
01061 static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
01062 {
01063 struct io_fn *s = opaque;
01064 uint32_t ret;
01065
01066 s->in ++;
01067 ret = s->mem_read[1](s->opaque, addr);
01068 s->in --;
01069 if (!s->in)
01070 fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
01071 return ret;
01072 }
01073 static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
01074 {
01075 struct io_fn *s = opaque;
01076 uint32_t ret;
01077
01078 s->in ++;
01079 ret = s->mem_read[2](s->opaque, addr);
01080 s->in --;
01081 if (!s->in)
01082 fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
01083 return ret;
01084 }
01085 static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
01086 {
01087 struct io_fn *s = opaque;
01088
01089 if (!s->in)
01090 fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
01091 s->in ++;
01092 s->mem_write[0](s->opaque, addr, value);
01093 s->in --;
01094 }
01095 static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
01096 {
01097 struct io_fn *s = opaque;
01098
01099 if (!s->in)
01100 fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
01101 s->in ++;
01102 s->mem_write[1](s->opaque, addr, value);
01103 s->in --;
01104 }
01105 static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
01106 {
01107 struct io_fn *s = opaque;
01108
01109 if (!s->in)
01110 fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
01111 s->in ++;
01112 s->mem_write[2](s->opaque, addr, value);
01113 s->in --;
01114 }
01115
01116 static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
01117 static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
01118
01119 inline static int debug_register_io_memory(int io_index,
01120 CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write,
01121 void *opaque)
01122 {
01123 struct io_fn *s = qemu_malloc(sizeof(struct io_fn));
01124
01125 s->mem_read = mem_read;
01126 s->mem_write = mem_write;
01127 s->opaque = opaque;
01128 s->in = 0;
01129 return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);
01130 }
01131 # define cpu_register_io_memory debug_register_io_memory
01132 # endif
01133
01134
01135
01136
01137 # ifdef L4_MUX_HACK
01138 # undef l4_register_io_memory
01139 int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read,
01140 CPUWriteMemoryFunc **mem_write, void *opaque);
01141 # endif
01142
01143 #endif