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00025 #if !defined(PPC_4XX_H)
00026 #define PPC_4XX_H
00027
00028 #include "pci.h"
00029
00030
00031 CPUState *ppc4xx_init (const char *cpu_model,
00032 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
00033 uint32_t sysclk);
00034
00035 typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
00036 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
00037 target_phys_addr_t offset, uint32_t len,
00038 CPUReadMemoryFunc **mem_read,
00039 CPUWriteMemoryFunc **mem_write, void *opaque);
00040 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base);
00041
00042
00043 enum {
00044 PPCUIC_OUTPUT_INT = 0,
00045 PPCUIC_OUTPUT_CINT = 1,
00046 PPCUIC_OUTPUT_NB,
00047 };
00048 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
00049 uint32_t dcr_base, int has_ssr, int has_vr);
00050
00051 ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
00052 target_phys_addr_t ram_bases[],
00053 target_phys_addr_t ram_sizes[],
00054 const unsigned int sdram_bank_sizes[]);
00055
00056 void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
00057 target_phys_addr_t *ram_bases,
00058 target_phys_addr_t *ram_sizes,
00059 int do_init);
00060
00061 PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
00062 target_phys_addr_t config_space,
00063 target_phys_addr_t int_ack,
00064 target_phys_addr_t special_cycle,
00065 target_phys_addr_t registers);
00066
00067 #endif