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00024 #define TCG_TARGET_X86_64 1
00025
00026 #define TCG_TARGET_REG_BITS 64
00027
00028
00029 #define TCG_TARGET_NB_REGS 16
00030
00031 enum {
00032 TCG_REG_RAX = 0,
00033 TCG_REG_RCX,
00034 TCG_REG_RDX,
00035 TCG_REG_RBX,
00036 TCG_REG_RSP,
00037 TCG_REG_RBP,
00038 TCG_REG_RSI,
00039 TCG_REG_RDI,
00040 TCG_REG_R8,
00041 TCG_REG_R9,
00042 TCG_REG_R10,
00043 TCG_REG_R11,
00044 TCG_REG_R12,
00045 TCG_REG_R13,
00046 TCG_REG_R14,
00047 TCG_REG_R15,
00048 };
00049
00050 #define TCG_CT_CONST_S32 0x100
00051 #define TCG_CT_CONST_U32 0x200
00052
00053
00054 #define TCG_REG_CALL_STACK TCG_REG_RSP
00055 #define TCG_TARGET_STACK_ALIGN 16
00056 #define TCG_TARGET_CALL_STACK_OFFSET 0
00057
00058
00059 #define TCG_TARGET_HAS_bswap_i32
00060 #define TCG_TARGET_HAS_bswap_i64
00061 #define TCG_TARGET_HAS_neg_i32
00062 #define TCG_TARGET_HAS_neg_i64
00063 #define TCG_TARGET_HAS_ext8s_i32
00064 #define TCG_TARGET_HAS_ext16s_i32
00065 #define TCG_TARGET_HAS_ext8s_i64
00066 #define TCG_TARGET_HAS_ext16s_i64
00067 #define TCG_TARGET_HAS_ext32s_i64
00068
00069
00070 #define TCG_AREG0 TCG_REG_R14
00071 #define TCG_AREG1 TCG_REG_R15
00072 #define TCG_AREG2 TCG_REG_R12
00073 #define TCG_AREG3 TCG_REG_R13
00074
00075 static inline void flush_icache_range(unsigned long start, unsigned long stop)
00076 {
00077 }