00001
00002 typedef struct pflash_t pflash_t;
00003
00004
00005 pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
00006 BlockDriverState *bs,
00007 uint32_t sector_len, int nb_blocs, int width,
00008 uint16_t id0, uint16_t id1,
00009 uint16_t id2, uint16_t id3);
00010
00011
00012 pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
00013 BlockDriverState *bs, uint32_t sector_len,
00014 int nb_blocs, int nb_mappings, int width,
00015 uint16_t id0, uint16_t id1,
00016 uint16_t id2, uint16_t id3,
00017 uint16_t unlock_addr0, uint16_t unlock_addr1);
00018
00019
00020 struct nand_flash_s;
00021 struct nand_flash_s *nand_init(int manf_id, int chip_id);
00022 void nand_done(struct nand_flash_s *s);
00023 void nand_setpins(struct nand_flash_s *s,
00024 int cle, int ale, int ce, int wp, int gnd);
00025 void nand_getpins(struct nand_flash_s *s, int *rb);
00026 void nand_setio(struct nand_flash_s *s, uint8_t value);
00027 uint8_t nand_getio(struct nand_flash_s *s);
00028
00029 #define NAND_MFR_TOSHIBA 0x98
00030 #define NAND_MFR_SAMSUNG 0xec
00031 #define NAND_MFR_FUJITSU 0x04
00032 #define NAND_MFR_NATIONAL 0x8f
00033 #define NAND_MFR_RENESAS 0x07
00034 #define NAND_MFR_STMICRO 0x20
00035 #define NAND_MFR_HYNIX 0xad
00036 #define NAND_MFR_MICRON 0x2c
00037
00038
00039 void onenand_base_update(void *opaque, target_phys_addr_t new);
00040 void onenand_base_unmap(void *opaque);
00041 void *onenand_init(uint32_t id, int regshift, qemu_irq irq);
00042 void *onenand_raw_otp(void *opaque);
00043
00044
00045 struct ecc_state_s {
00046 uint8_t cp;
00047 uint16_t lp[2];
00048 uint16_t count;
00049 };
00050
00051 uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
00052 void ecc_reset(struct ecc_state_s *s);
00053 void ecc_put(QEMUFile *f, struct ecc_state_s *s);
00054 void ecc_get(QEMUFile *f, struct ecc_state_s *s);