00001 #ifndef HW_PC_H
00002 #define HW_PC_H
00003
00004
00005
00006
00007 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
00008 CharDriverState *chr);
00009 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
00010 qemu_irq irq, int baudbase,
00011 CharDriverState *chr, int ioregister);
00012 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
00013 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
00014 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
00015 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
00016 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
00017 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
00018
00019
00020
00021 typedef struct ParallelState ParallelState;
00022 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
00023 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
00024
00025
00026
00027 typedef struct PicState2 PicState2;
00028 extern PicState2 *isa_pic;
00029 void pic_set_irq(int irq, int level);
00030 void pic_set_irq_new(void *opaque, int irq, int level);
00031 qemu_irq *i8259_init(qemu_irq parent_irq);
00032 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
00033 void *alt_irq_opaque);
00034 int pic_read_irq(PicState2 *s);
00035 void pic_update_irq(PicState2 *s);
00036 uint32_t pic_intack_read(PicState2 *s);
00037 void pic_info(void);
00038 void irq_info(void);
00039
00040
00041 typedef struct IOAPICState IOAPICState;
00042
00043 int apic_init(CPUState *env);
00044 int apic_accept_pic_intr(CPUState *env);
00045 void apic_deliver_pic_intr(CPUState *env, int level);
00046 int apic_get_interrupt(CPUState *env);
00047 IOAPICState *ioapic_init(void);
00048 void ioapic_set_irq(void *opaque, int vector, int level);
00049 void apic_reset_irq_delivered(void);
00050 int apic_get_irq_delivered(void);
00051
00052
00053
00054 #define PIT_FREQ 1193182
00055
00056 typedef struct PITState PITState;
00057
00058 PITState *pit_init(int base, qemu_irq irq);
00059 void pit_set_gate(PITState *pit, int channel, int val);
00060 int pit_get_gate(PITState *pit, int channel);
00061 int pit_get_initial_count(PITState *pit, int channel);
00062 int pit_get_mode(PITState *pit, int channel);
00063 int pit_get_out(PITState *pit, int channel, int64_t current_time);
00064
00065 void hpet_pit_disable(void);
00066 void hpet_pit_enable(void);
00067
00068
00069 void vmport_init(void);
00070 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
00071
00072
00073 void *vmmouse_init(void *m);
00074
00075
00076
00077 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
00078 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
00079 target_phys_addr_t base, ram_addr_t size,
00080 target_phys_addr_t mask);
00081
00082
00083
00084 typedef struct RTCState RTCState;
00085
00086 RTCState *rtc_init(int base, qemu_irq irq, int base_year);
00087 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
00088 int base_year);
00089 void rtc_set_memory(RTCState *s, int addr, int val);
00090 void rtc_set_date(RTCState *s, const struct tm *tm);
00091 void cmos_set_s3_resume(void);
00092
00093
00094 extern int fd_bootchk;
00095
00096 void ioport_set_a20(int enable);
00097 int ioport_get_a20(void);
00098
00099
00100 extern int acpi_enabled;
00101 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
00102 qemu_irq sci_irq);
00103 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
00104 void acpi_bios_init(void);
00105 int acpi_table_add(const char *table_desc);
00106
00107
00108 extern int no_hpet;
00109
00110
00111 void pcspk_init(PITState *);
00112 int pcspk_audio_init(AudioState *, qemu_irq *pic);
00113
00114
00115 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
00116 void i440fx_set_smm(PCIDevice *d, int val);
00117 int piix3_init(PCIBus *bus, int devfn);
00118 void i440fx_init_memory_mappings(PCIDevice *d);
00119
00120 extern PCIDevice *piix4_dev;
00121 int piix4_init(PCIBus *bus, int devfn);
00122
00123
00124 enum vga_retrace_method {
00125 VGA_RETRACE_DUMB,
00126 VGA_RETRACE_PRECISE
00127 };
00128
00129 extern enum vga_retrace_method vga_retrace_method;
00130
00131 #if !defined(TARGET_SPARC) || defined(TARGET_SPARC64)
00132 #define VGA_RAM_SIZE (8192 * 1024)
00133 #else
00134 #define VGA_RAM_SIZE (9 * 1024 * 1024)
00135 #endif
00136
00137 int isa_vga_init(uint8_t *vga_ram_base,
00138 unsigned long vga_ram_offset, int vga_ram_size);
00139 int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
00140 unsigned long vga_ram_offset, int vga_ram_size,
00141 unsigned long vga_bios_offset, int vga_bios_size);
00142 int isa_vga_mm_init(uint8_t *vga_ram_base,
00143 unsigned long vga_ram_offset, int vga_ram_size,
00144 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
00145 int it_shift);
00146
00147
00148 void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
00149 ram_addr_t vga_ram_offset, int vga_ram_size);
00150 void isa_cirrus_vga_init(uint8_t *vga_ram_base,
00151 ram_addr_t vga_ram_offset, int vga_ram_size);
00152
00153
00154 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
00155 BlockDriverState *hd0, BlockDriverState *hd1);
00156 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
00157 int secondary_ide_enabled);
00158 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
00159 qemu_irq *pic);
00160 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
00161 qemu_irq *pic);
00162
00163
00164
00165 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
00166
00167 #endif