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00020 #if !defined (__CPU_PPC_H__)
00021 #define __CPU_PPC_H__
00022
00023 #include "config.h"
00024 #include <inttypes.h>
00025
00026
00027
00028 #if defined (TARGET_PPC64)
00029
00030 #define TARGET_LONG_BITS 64
00031 #define TARGET_PAGE_BITS 12
00032
00033 #else
00034
00035 #define TARGET_LONG_BITS 32
00036
00037 #if defined(TARGET_PPCEMB)
00038
00039
00040 #define TARGET_PHYS_ADDR_BITS 64
00041 #if defined(CONFIG_USER_ONLY)
00042
00043
00044
00045 #define TARGET_PAGE_BITS 12
00046 #else
00047
00048 #define TARGET_PAGE_BITS 10
00049 #endif
00050 #else
00051
00052 #define TARGET_PAGE_BITS 12
00053 #endif
00054
00055 #endif
00056
00057 #include "cpu-defs.h"
00058
00059 #define REGX "%016" PRIx64
00060 #define ADDRX TARGET_FMT_lx
00061 #define PADDRX TARGET_FMT_plx
00062
00063 #include <setjmp.h>
00064
00065 #include "softfloat.h"
00066
00067 #define TARGET_HAS_ICE 1
00068
00069
00070 #if defined (TARGET_PPC64) && defined(CONFIG_USER_ONLY)
00071 #define ELF_MACHINE EM_PPC64
00072 #else
00073 #define ELF_MACHINE EM_PPC
00074 #endif
00075
00076
00077
00078 typedef enum powerpc_mmu_t powerpc_mmu_t;
00079 enum powerpc_mmu_t {
00080 POWERPC_MMU_UNKNOWN = 0x00000000,
00081
00082 POWERPC_MMU_32B = 0x00000001,
00083
00084 POWERPC_MMU_SOFT_6xx = 0x00000002,
00085
00086 POWERPC_MMU_SOFT_74xx = 0x00000003,
00087
00088 POWERPC_MMU_SOFT_4xx = 0x00000004,
00089
00090 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
00091
00092 POWERPC_MMU_REAL = 0x00000006,
00093
00094 POWERPC_MMU_MPC8xx = 0x00000007,
00095
00096 POWERPC_MMU_BOOKE = 0x00000008,
00097
00098 POWERPC_MMU_BOOKE_FSL = 0x00000009,
00099
00100 POWERPC_MMU_601 = 0x0000000A,
00101 #if defined(TARGET_PPC64)
00102 #define POWERPC_MMU_64 0x00010000
00103
00104 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
00105
00106 POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
00107 #endif
00108 };
00109
00110
00111
00112 typedef enum powerpc_excp_t powerpc_excp_t;
00113 enum powerpc_excp_t {
00114 POWERPC_EXCP_UNKNOWN = 0,
00115
00116 POWERPC_EXCP_STD,
00117
00118 POWERPC_EXCP_40x,
00119
00120 POWERPC_EXCP_601,
00121
00122 POWERPC_EXCP_602,
00123
00124 POWERPC_EXCP_603,
00125
00126 POWERPC_EXCP_603E,
00127
00128 POWERPC_EXCP_G2,
00129
00130 POWERPC_EXCP_604,
00131
00132 POWERPC_EXCP_7x0,
00133
00134 POWERPC_EXCP_7x5,
00135
00136 POWERPC_EXCP_74xx,
00137
00138 POWERPC_EXCP_BOOKE,
00139 #if defined(TARGET_PPC64)
00140
00141 POWERPC_EXCP_970,
00142 #endif
00143 };
00144
00145
00146
00147 enum {
00148 POWERPC_EXCP_NONE = -1,
00149
00150 POWERPC_EXCP_CRITICAL = 0,
00151 POWERPC_EXCP_MCHECK = 1,
00152 POWERPC_EXCP_DSI = 2,
00153 POWERPC_EXCP_ISI = 3,
00154 POWERPC_EXCP_EXTERNAL = 4,
00155 POWERPC_EXCP_ALIGN = 5,
00156 POWERPC_EXCP_PROGRAM = 6,
00157 POWERPC_EXCP_FPU = 7,
00158 POWERPC_EXCP_SYSCALL = 8,
00159 POWERPC_EXCP_APU = 9,
00160 POWERPC_EXCP_DECR = 10,
00161 POWERPC_EXCP_FIT = 11,
00162 POWERPC_EXCP_WDT = 12,
00163 POWERPC_EXCP_DTLB = 13,
00164 POWERPC_EXCP_ITLB = 14,
00165 POWERPC_EXCP_DEBUG = 15,
00166
00167 POWERPC_EXCP_SPEU = 32,
00168 POWERPC_EXCP_EFPDI = 33,
00169 POWERPC_EXCP_EFPRI = 34,
00170 POWERPC_EXCP_EPERFM = 35,
00171 POWERPC_EXCP_DOORI = 36,
00172 POWERPC_EXCP_DOORCI = 37,
00173
00174
00175 POWERPC_EXCP_RESET = 64,
00176 POWERPC_EXCP_DSEG = 65,
00177 POWERPC_EXCP_ISEG = 66,
00178 POWERPC_EXCP_HDECR = 67,
00179 POWERPC_EXCP_TRACE = 68,
00180 POWERPC_EXCP_HDSI = 69,
00181 POWERPC_EXCP_HISI = 70,
00182 POWERPC_EXCP_HDSEG = 71,
00183 POWERPC_EXCP_HISEG = 72,
00184 POWERPC_EXCP_VPU = 73,
00185
00186 POWERPC_EXCP_PIT = 74,
00187
00188 POWERPC_EXCP_IO = 75,
00189 POWERPC_EXCP_RUNM = 76,
00190
00191 POWERPC_EXCP_EMUL = 77,
00192
00193 POWERPC_EXCP_IFTLB = 78,
00194 POWERPC_EXCP_DLTLB = 79,
00195 POWERPC_EXCP_DSTLB = 80,
00196
00197 POWERPC_EXCP_FPA = 81,
00198 POWERPC_EXCP_DABR = 82,
00199 POWERPC_EXCP_IABR = 83,
00200 POWERPC_EXCP_SMI = 84,
00201 POWERPC_EXCP_PERFM = 85,
00202
00203 POWERPC_EXCP_THERM = 86,
00204
00205 POWERPC_EXCP_VPUA = 87,
00206
00207 POWERPC_EXCP_SOFTP = 88,
00208 POWERPC_EXCP_MAINT = 89,
00209
00210 POWERPC_EXCP_MEXTBR = 90,
00211 POWERPC_EXCP_NMEXTBR = 91,
00212 POWERPC_EXCP_ITLBE = 92,
00213 POWERPC_EXCP_DTLBE = 93,
00214
00215 POWERPC_EXCP_NB = 96,
00216
00217 POWERPC_EXCP_STOP = 0x200,
00218 POWERPC_EXCP_BRANCH = 0x201,
00219
00220 POWERPC_EXCP_SYNC = 0x202,
00221 POWERPC_EXCP_SYSCALL_USER = 0x203,
00222 };
00223
00224
00225 enum {
00226
00227 POWERPC_EXCP_ALIGN_FP = 0x01,
00228 POWERPC_EXCP_ALIGN_LST = 0x02,
00229 POWERPC_EXCP_ALIGN_LE = 0x03,
00230 POWERPC_EXCP_ALIGN_PROT = 0x04,
00231 POWERPC_EXCP_ALIGN_BAT = 0x05,
00232 POWERPC_EXCP_ALIGN_CACHE = 0x06,
00233
00234
00235 POWERPC_EXCP_FP = 0x10,
00236 POWERPC_EXCP_FP_OX = 0x01,
00237 POWERPC_EXCP_FP_UX = 0x02,
00238 POWERPC_EXCP_FP_ZX = 0x03,
00239 POWERPC_EXCP_FP_XX = 0x04,
00240 POWERPC_EXCP_FP_VXSNAN = 0x05,
00241 POWERPC_EXCP_FP_VXISI = 0x06,
00242 POWERPC_EXCP_FP_VXIDI = 0x07,
00243 POWERPC_EXCP_FP_VXZDZ = 0x08,
00244 POWERPC_EXCP_FP_VXIMZ = 0x09,
00245 POWERPC_EXCP_FP_VXVC = 0x0A,
00246 POWERPC_EXCP_FP_VXSOFT = 0x0B,
00247 POWERPC_EXCP_FP_VXSQRT = 0x0C,
00248 POWERPC_EXCP_FP_VXCVI = 0x0D,
00249
00250 POWERPC_EXCP_INVAL = 0x20,
00251 POWERPC_EXCP_INVAL_INVAL = 0x01,
00252 POWERPC_EXCP_INVAL_LSWX = 0x02,
00253 POWERPC_EXCP_INVAL_SPR = 0x03,
00254 POWERPC_EXCP_INVAL_FP = 0x04,
00255
00256 POWERPC_EXCP_PRIV = 0x30,
00257 POWERPC_EXCP_PRIV_OPC = 0x01,
00258 POWERPC_EXCP_PRIV_REG = 0x02,
00259
00260 POWERPC_EXCP_TRAP = 0x40,
00261 };
00262
00263
00264
00265 typedef enum powerpc_input_t powerpc_input_t;
00266 enum powerpc_input_t {
00267 PPC_FLAGS_INPUT_UNKNOWN = 0,
00268
00269 PPC_FLAGS_INPUT_6xx,
00270
00271 PPC_FLAGS_INPUT_BookE,
00272
00273 PPC_FLAGS_INPUT_405,
00274
00275 PPC_FLAGS_INPUT_970,
00276
00277 PPC_FLAGS_INPUT_401,
00278
00279 PPC_FLAGS_INPUT_RCPU,
00280 };
00281
00282 #define PPC_INPUT(env) (env->bus_model)
00283
00284
00285 typedef struct ppc_def_t ppc_def_t;
00286 typedef struct opc_handler_t opc_handler_t;
00287
00288
00289
00290 typedef struct CPUPPCState CPUPPCState;
00291 typedef struct ppc_tb_t ppc_tb_t;
00292 typedef struct ppc_spr_t ppc_spr_t;
00293 typedef struct ppc_dcr_t ppc_dcr_t;
00294 typedef union ppc_avr_t ppc_avr_t;
00295 typedef union ppc_tlb_t ppc_tlb_t;
00296
00297
00298 struct ppc_spr_t {
00299 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
00300 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
00301 #if !defined(CONFIG_USER_ONLY)
00302 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
00303 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
00304 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
00305 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
00306 #endif
00307 const char *name;
00308 };
00309
00310
00311 union ppc_avr_t {
00312 float32 f[4];
00313 uint8_t u8[16];
00314 uint16_t u16[8];
00315 uint32_t u32[4];
00316 int8_t s8[16];
00317 int16_t s16[8];
00318 int32_t s32[4];
00319 uint64_t u64[2];
00320 };
00321
00322
00323 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
00324 struct ppc6xx_tlb_t {
00325 target_ulong pte0;
00326 target_ulong pte1;
00327 target_ulong EPN;
00328 };
00329
00330 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
00331 struct ppcemb_tlb_t {
00332 target_phys_addr_t RPN;
00333 target_ulong EPN;
00334 target_ulong PID;
00335 target_ulong size;
00336 uint32_t prot;
00337 uint32_t attr;
00338 };
00339
00340 union ppc_tlb_t {
00341 ppc6xx_tlb_t tlb6;
00342 ppcemb_tlb_t tlbe;
00343 };
00344
00345
00346
00347 #define MSR_SF 63
00348 #define MSR_TAG 62
00349 #define MSR_ISF 61
00350 #define MSR_SHV 60
00351 #define MSR_CM 31
00352 #define MSR_ICM 30
00353 #define MSR_THV 29
00354 #define MSR_UCLE 26
00355 #define MSR_VR 25
00356 #define MSR_SPE 25
00357 #define MSR_AP 23
00358 #define MSR_SA 22
00359 #define MSR_KEY 19
00360 #define MSR_POW 18
00361 #define MSR_TGPR 17
00362 #define MSR_CE 17
00363 #define MSR_ILE 16
00364 #define MSR_EE 15
00365 #define MSR_PR 14
00366 #define MSR_FP 13
00367 #define MSR_ME 12
00368 #define MSR_FE0 11
00369 #define MSR_SE 10
00370 #define MSR_DWE 10
00371 #define MSR_UBLE 10
00372 #define MSR_BE 9
00373 #define MSR_DE 9
00374 #define MSR_FE1 8
00375 #define MSR_AL 7
00376 #define MSR_EP 6
00377 #define MSR_IR 5
00378 #define MSR_DR 4
00379 #define MSR_PE 3
00380 #define MSR_PX 2
00381 #define MSR_PMM 2
00382 #define MSR_RI 1
00383 #define MSR_LE 0
00384
00385 #define msr_sf ((env->msr >> MSR_SF) & 1)
00386 #define msr_isf ((env->msr >> MSR_ISF) & 1)
00387 #define msr_shv ((env->msr >> MSR_SHV) & 1)
00388 #define msr_cm ((env->msr >> MSR_CM) & 1)
00389 #define msr_icm ((env->msr >> MSR_ICM) & 1)
00390 #define msr_thv ((env->msr >> MSR_THV) & 1)
00391 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
00392 #define msr_vr ((env->msr >> MSR_VR) & 1)
00393 #define msr_spe ((env->msr >> MSR_SPE) & 1)
00394 #define msr_ap ((env->msr >> MSR_AP) & 1)
00395 #define msr_sa ((env->msr >> MSR_SA) & 1)
00396 #define msr_key ((env->msr >> MSR_KEY) & 1)
00397 #define msr_pow ((env->msr >> MSR_POW) & 1)
00398 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
00399 #define msr_ce ((env->msr >> MSR_CE) & 1)
00400 #define msr_ile ((env->msr >> MSR_ILE) & 1)
00401 #define msr_ee ((env->msr >> MSR_EE) & 1)
00402 #define msr_pr ((env->msr >> MSR_PR) & 1)
00403 #define msr_fp ((env->msr >> MSR_FP) & 1)
00404 #define msr_me ((env->msr >> MSR_ME) & 1)
00405 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
00406 #define msr_se ((env->msr >> MSR_SE) & 1)
00407 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
00408 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
00409 #define msr_be ((env->msr >> MSR_BE) & 1)
00410 #define msr_de ((env->msr >> MSR_DE) & 1)
00411 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
00412 #define msr_al ((env->msr >> MSR_AL) & 1)
00413 #define msr_ep ((env->msr >> MSR_EP) & 1)
00414 #define msr_ir ((env->msr >> MSR_IR) & 1)
00415 #define msr_dr ((env->msr >> MSR_DR) & 1)
00416 #define msr_pe ((env->msr >> MSR_PE) & 1)
00417 #define msr_px ((env->msr >> MSR_PX) & 1)
00418 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
00419 #define msr_ri ((env->msr >> MSR_RI) & 1)
00420 #define msr_le ((env->msr >> MSR_LE) & 1)
00421
00422 #if defined(TARGET_PPC64)
00423 #define MSR_HVB (1ULL << MSR_SHV)
00424 #define msr_hv msr_shv
00425 #else
00426 #if defined(PPC_EMULATE_32BITS_HYPV)
00427 #define MSR_HVB (1ULL << MSR_THV)
00428 #define msr_hv msr_thv
00429 #else
00430 #define MSR_HVB (0ULL)
00431 #define msr_hv (0)
00432 #endif
00433 #endif
00434
00435 enum {
00436 POWERPC_FLAG_NONE = 0x00000000,
00437
00438 POWERPC_FLAG_SPE = 0x00000001,
00439 POWERPC_FLAG_VRE = 0x00000002,
00440
00441 POWERPC_FLAG_TGPR = 0x00000004,
00442 POWERPC_FLAG_CE = 0x00000008,
00443
00444 POWERPC_FLAG_SE = 0x00000010,
00445 POWERPC_FLAG_DWE = 0x00000020,
00446 POWERPC_FLAG_UBLE = 0x00000040,
00447
00448 POWERPC_FLAG_BE = 0x00000080,
00449 POWERPC_FLAG_DE = 0x00000100,
00450
00451 POWERPC_FLAG_PX = 0x00000200,
00452 POWERPC_FLAG_PMM = 0x00000400,
00453
00454
00455 POWERPC_FLAG_RTC_CLK = 0x00010000,
00456 POWERPC_FLAG_BUS_CLK = 0x00020000,
00457 };
00458
00459
00460
00461 #define FPSCR_FX 31
00462 #define FPSCR_FEX 30
00463 #define FPSCR_VX 29
00464 #define FPSCR_OX 28
00465 #define FPSCR_UX 27
00466 #define FPSCR_ZX 26
00467 #define FPSCR_XX 25
00468 #define FPSCR_VXSNAN 24
00469 #define FPSCR_VXISI 23
00470 #define FPSCR_VXIDI 22
00471 #define FPSCR_VXZDZ 21
00472 #define FPSCR_VXIMZ 20
00473 #define FPSCR_VXVC 19
00474 #define FPSCR_FR 18
00475 #define FPSCR_FI 17
00476 #define FPSCR_C 16
00477 #define FPSCR_FL 15
00478 #define FPSCR_FG 14
00479 #define FPSCR_FE 13
00480 #define FPSCR_FU 12
00481 #define FPSCR_FPCC 12
00482 #define FPSCR_FPRF 12
00483 #define FPSCR_VXSOFT 10
00484 #define FPSCR_VXSQRT 9
00485 #define FPSCR_VXCVI 8
00486 #define FPSCR_VE 7
00487 #define FPSCR_OE 6
00488 #define FPSCR_UE 5
00489 #define FPSCR_ZE 4
00490 #define FPSCR_XE 3
00491 #define FPSCR_NI 2
00492 #define FPSCR_RN1 1
00493 #define FPSCR_RN 0
00494 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
00495 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
00496 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
00497 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
00498 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
00499 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
00500 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
00501 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
00502 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
00503 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
00504 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
00505 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
00506 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
00507 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
00508 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
00509 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
00510 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
00511 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
00512 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
00513 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
00514 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
00515 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
00516 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
00517
00518 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
00519 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
00520 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
00521 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
00522 (1 << FPSCR_VXCVI)))
00523
00524 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
00525
00526 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
00527 0x1F)
00528
00529
00530
00531 #define VSCR_NJ 16
00532 #define VSCR_SAT 0
00533 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
00534 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
00535
00536
00537
00538 #define NB_MMU_MODES 3
00539
00540 struct CPUPPCState {
00541
00542
00543
00544
00545 target_ulong gpr[32];
00546 #if !defined(TARGET_PPC64)
00547
00548 target_ulong gprh[32];
00549 #endif
00550
00551 target_ulong lr;
00552
00553 target_ulong ctr;
00554
00555 uint32_t crf[8];
00556
00557 target_ulong xer;
00558
00559 target_ulong reserve;
00560
00561
00562
00563 target_ulong msr;
00564
00565 target_ulong tgpr[4];
00566
00567
00568 float_status fp_status;
00569
00570 float64 fpr[32];
00571
00572 uint32_t fpscr;
00573
00574 CPU_COMMON
00575
00576 int access_type;
00577
00578
00579
00580 #if !defined(CONFIG_USER_ONLY)
00581 #if defined(TARGET_PPC64)
00582
00583 target_ulong asr;
00584
00585 int slb_nr;
00586 #endif
00587
00588 target_ulong sdr1;
00589 target_ulong sr[32];
00590
00591 int nb_BATs;
00592 target_ulong DBAT[2][8];
00593 target_ulong IBAT[2][8];
00594
00595 int nb_tlb;
00596 int tlb_per_way;
00597 int nb_ways;
00598 int last_way;
00599 int id_tlbs;
00600 int nb_pids;
00601 ppc_tlb_t *tlb;
00602
00603 target_ulong pb[4];
00604 #endif
00605
00606
00607
00608 target_ulong spr[1024];
00609 ppc_spr_t spr_cb[1024];
00610
00611 ppc_avr_t avr[32];
00612 uint32_t vscr;
00613
00614 uint64_t spe_acc;
00615 uint32_t spe_fscr;
00616
00617
00618 float_status vec_status;
00619
00620
00621
00622 ppc_tb_t *tb_env;
00623
00624 ppc_dcr_t *dcr_env;
00625
00626 int dcache_line_size;
00627 int icache_line_size;
00628
00629
00630
00631 target_ulong msr_mask;
00632 powerpc_mmu_t mmu_model;
00633 powerpc_excp_t excp_model;
00634 powerpc_input_t bus_model;
00635 int bfd_mach;
00636 uint32_t flags;
00637
00638 int error_code;
00639 uint32_t pending_interrupts;
00640 #if !defined(CONFIG_USER_ONLY)
00641
00642
00643
00644 uint32_t irq_input_state;
00645 void **irq_inputs;
00646
00647 target_ulong excp_vectors[POWERPC_EXCP_NB];
00648 target_ulong excp_prefix;
00649 target_ulong ivor_mask;
00650 target_ulong ivpr_mask;
00651 target_ulong hreset_vector;
00652 #endif
00653
00654
00655
00656 target_ulong nip;
00657
00658
00659 opc_handler_t *opcodes[0x40];
00660
00661
00662 target_ulong hflags;
00663 target_ulong hflags_nmsr;
00664 int mmu_idx;
00665
00666
00667 int power_mode;
00668 int (*check_pow)(CPUPPCState *env);
00669
00670
00671 int (*osi_call)(struct CPUPPCState *env);
00672 };
00673
00674
00675 typedef struct mmu_ctx_t mmu_ctx_t;
00676 struct mmu_ctx_t {
00677 target_phys_addr_t raddr;
00678 int prot;
00679 target_phys_addr_t pg_addr[2];
00680 target_ulong ptem;
00681 int key;
00682 int nx;
00683 };
00684
00685
00686 CPUPPCState *cpu_ppc_init (const char *cpu_model);
00687 void ppc_translate_init(void);
00688 int cpu_ppc_exec (CPUPPCState *s);
00689 void cpu_ppc_close (CPUPPCState *s);
00690
00691
00692
00693 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
00694 void *puc);
00695 int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
00696 int mmu_idx, int is_softmmu);
00697 int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
00698 int rw, int access_type);
00699 void do_interrupt (CPUPPCState *env);
00700 void ppc_hw_interrupt (CPUPPCState *env);
00701
00702 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
00703
00704 #if !defined(CONFIG_USER_ONLY)
00705 void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
00706 target_ulong pte0, target_ulong pte1);
00707 void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
00708 void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
00709 void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
00710 void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
00711 void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
00712 void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
00713 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
00714 #if defined(TARGET_PPC64)
00715 void ppc_store_asr (CPUPPCState *env, target_ulong value);
00716 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
00717 void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);
00718 #endif
00719 void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
00720 #endif
00721 void ppc_store_msr (CPUPPCState *env, target_ulong value);
00722
00723 void cpu_ppc_reset (void *opaque);
00724
00725 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
00726
00727 const ppc_def_t *cpu_ppc_find_by_name (const char *name);
00728 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
00729
00730
00731 #ifndef NO_CPU_IO_DEFS
00732 uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
00733 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
00734 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
00735 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
00736 uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
00737 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
00738 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
00739 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
00740 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
00741 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
00742 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
00743 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
00744 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
00745 void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
00746 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
00747 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
00748 #if !defined(CONFIG_USER_ONLY)
00749 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
00750 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
00751 target_ulong load_40x_pit (CPUPPCState *env);
00752 void store_40x_pit (CPUPPCState *env, target_ulong val);
00753 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
00754 void store_40x_sler (CPUPPCState *env, uint32_t val);
00755 void store_booke_tcr (CPUPPCState *env, target_ulong val);
00756 void store_booke_tsr (CPUPPCState *env, target_ulong val);
00757 void ppc_tlb_invalidate_all (CPUPPCState *env);
00758 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
00759 #if defined(TARGET_PPC64)
00760 void ppc_slb_invalidate_all (CPUPPCState *env);
00761 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
00762 #endif
00763 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
00764 #endif
00765 #endif
00766
00767 static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn)
00768 {
00769 uint64_t gprv;
00770
00771 gprv = env->gpr[gprn];
00772 #if !defined(TARGET_PPC64)
00773 if (env->flags & POWERPC_FLAG_SPE) {
00774
00775
00776
00777 gprv &= 0xFFFFFFFFULL;
00778 gprv |= (uint64_t)env->gprh[gprn] << 32;
00779 }
00780 #endif
00781
00782 return gprv;
00783 }
00784
00785
00786 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
00787 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
00788
00789 #define CPUState CPUPPCState
00790 #define cpu_init cpu_ppc_init
00791 #define cpu_exec cpu_ppc_exec
00792 #define cpu_gen_code cpu_ppc_gen_code
00793 #define cpu_signal_handler cpu_ppc_signal_handler
00794 #define cpu_list ppc_cpu_list
00795
00796 #define CPU_SAVE_VERSION 3
00797
00798
00799 #define MMU_MODE0_SUFFIX _user
00800 #define MMU_MODE1_SUFFIX _kernel
00801 #define MMU_MODE2_SUFFIX _hypv
00802 #define MMU_USER_IDX 0
00803 static inline int cpu_mmu_index (CPUState *env)
00804 {
00805 return env->mmu_idx;
00806 }
00807
00808 #if defined(CONFIG_USER_ONLY)
00809 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
00810 {
00811 int i;
00812 if (newsp)
00813 env->gpr[1] = newsp;
00814 for (i = 7; i < 32; i++)
00815 env->gpr[i] = 0;
00816 }
00817 #endif
00818
00819 #include "cpu-all.h"
00820 #include "exec-all.h"
00821
00822
00823
00824 #define CRF_LT 3
00825 #define CRF_GT 2
00826 #define CRF_EQ 1
00827 #define CRF_SO 0
00828 #define CRF_CH (1 << 4)
00829 #define CRF_CL (1 << 3)
00830 #define CRF_CH_OR_CL (1 << 2)
00831 #define CRF_CH_AND_CL (1 << 1)
00832
00833
00834 #define XER_SO 31
00835 #define XER_OV 30
00836 #define XER_CA 29
00837 #define XER_CMP 8
00838 #define XER_BC 0
00839 #define xer_so ((env->xer >> XER_SO) & 1)
00840 #define xer_ov ((env->xer >> XER_OV) & 1)
00841 #define xer_ca ((env->xer >> XER_CA) & 1)
00842 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
00843 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
00844
00845
00846 #define SPR_MQ (0x000)
00847 #define SPR_XER (0x001)
00848 #define SPR_601_VRTCU (0x004)
00849 #define SPR_601_VRTCL (0x005)
00850 #define SPR_601_UDECR (0x006)
00851 #define SPR_LR (0x008)
00852 #define SPR_CTR (0x009)
00853 #define SPR_DSISR (0x012)
00854 #define SPR_DAR (0x013)
00855 #define SPR_601_RTCU (0x014)
00856 #define SPR_601_RTCL (0x015)
00857 #define SPR_DECR (0x016)
00858 #define SPR_SDR1 (0x019)
00859 #define SPR_SRR0 (0x01A)
00860 #define SPR_SRR1 (0x01B)
00861 #define SPR_AMR (0x01D)
00862 #define SPR_BOOKE_PID (0x030)
00863 #define SPR_BOOKE_DECAR (0x036)
00864 #define SPR_BOOKE_CSRR0 (0x03A)
00865 #define SPR_BOOKE_CSRR1 (0x03B)
00866 #define SPR_BOOKE_DEAR (0x03D)
00867 #define SPR_BOOKE_ESR (0x03E)
00868 #define SPR_BOOKE_IVPR (0x03F)
00869 #define SPR_MPC_EIE (0x050)
00870 #define SPR_MPC_EID (0x051)
00871 #define SPR_MPC_NRI (0x052)
00872 #define SPR_CTRL (0x088)
00873 #define SPR_MPC_CMPA (0x090)
00874 #define SPR_MPC_CMPB (0x091)
00875 #define SPR_MPC_CMPC (0x092)
00876 #define SPR_MPC_CMPD (0x093)
00877 #define SPR_MPC_ECR (0x094)
00878 #define SPR_MPC_DER (0x095)
00879 #define SPR_MPC_COUNTA (0x096)
00880 #define SPR_MPC_COUNTB (0x097)
00881 #define SPR_UCTRL (0x098)
00882 #define SPR_MPC_CMPE (0x098)
00883 #define SPR_MPC_CMPF (0x099)
00884 #define SPR_MPC_CMPG (0x09A)
00885 #define SPR_MPC_CMPH (0x09B)
00886 #define SPR_MPC_LCTRL1 (0x09C)
00887 #define SPR_MPC_LCTRL2 (0x09D)
00888 #define SPR_MPC_ICTRL (0x09E)
00889 #define SPR_MPC_BAR (0x09F)
00890 #define SPR_VRSAVE (0x100)
00891 #define SPR_USPRG0 (0x100)
00892 #define SPR_USPRG1 (0x101)
00893 #define SPR_USPRG2 (0x102)
00894 #define SPR_USPRG3 (0x103)
00895 #define SPR_USPRG4 (0x104)
00896 #define SPR_USPRG5 (0x105)
00897 #define SPR_USPRG6 (0x106)
00898 #define SPR_USPRG7 (0x107)
00899 #define SPR_VTBL (0x10C)
00900 #define SPR_VTBU (0x10D)
00901 #define SPR_SPRG0 (0x110)
00902 #define SPR_SPRG1 (0x111)
00903 #define SPR_SPRG2 (0x112)
00904 #define SPR_SPRG3 (0x113)
00905 #define SPR_SPRG4 (0x114)
00906 #define SPR_SCOMC (0x114)
00907 #define SPR_SPRG5 (0x115)
00908 #define SPR_SCOMD (0x115)
00909 #define SPR_SPRG6 (0x116)
00910 #define SPR_SPRG7 (0x117)
00911 #define SPR_ASR (0x118)
00912 #define SPR_EAR (0x11A)
00913 #define SPR_TBL (0x11C)
00914 #define SPR_TBU (0x11D)
00915 #define SPR_TBU40 (0x11E)
00916 #define SPR_SVR (0x11E)
00917 #define SPR_BOOKE_PIR (0x11E)
00918 #define SPR_PVR (0x11F)
00919 #define SPR_HSPRG0 (0x130)
00920 #define SPR_BOOKE_DBSR (0x130)
00921 #define SPR_HSPRG1 (0x131)
00922 #define SPR_HDSISR (0x132)
00923 #define SPR_HDAR (0x133)
00924 #define SPR_BOOKE_DBCR0 (0x134)
00925 #define SPR_IBCR (0x135)
00926 #define SPR_PURR (0x135)
00927 #define SPR_BOOKE_DBCR1 (0x135)
00928 #define SPR_DBCR (0x136)
00929 #define SPR_HDEC (0x136)
00930 #define SPR_BOOKE_DBCR2 (0x136)
00931 #define SPR_HIOR (0x137)
00932 #define SPR_MBAR (0x137)
00933 #define SPR_RMOR (0x138)
00934 #define SPR_BOOKE_IAC1 (0x138)
00935 #define SPR_HRMOR (0x139)
00936 #define SPR_BOOKE_IAC2 (0x139)
00937 #define SPR_HSRR0 (0x13A)
00938 #define SPR_BOOKE_IAC3 (0x13A)
00939 #define SPR_HSRR1 (0x13B)
00940 #define SPR_BOOKE_IAC4 (0x13B)
00941 #define SPR_LPCR (0x13C)
00942 #define SPR_BOOKE_DAC1 (0x13C)
00943 #define SPR_LPIDR (0x13D)
00944 #define SPR_DABR2 (0x13D)
00945 #define SPR_BOOKE_DAC2 (0x13D)
00946 #define SPR_BOOKE_DVC1 (0x13E)
00947 #define SPR_BOOKE_DVC2 (0x13F)
00948 #define SPR_BOOKE_TSR (0x150)
00949 #define SPR_BOOKE_TCR (0x154)
00950 #define SPR_BOOKE_IVOR0 (0x190)
00951 #define SPR_BOOKE_IVOR1 (0x191)
00952 #define SPR_BOOKE_IVOR2 (0x192)
00953 #define SPR_BOOKE_IVOR3 (0x193)
00954 #define SPR_BOOKE_IVOR4 (0x194)
00955 #define SPR_BOOKE_IVOR5 (0x195)
00956 #define SPR_BOOKE_IVOR6 (0x196)
00957 #define SPR_BOOKE_IVOR7 (0x197)
00958 #define SPR_BOOKE_IVOR8 (0x198)
00959 #define SPR_BOOKE_IVOR9 (0x199)
00960 #define SPR_BOOKE_IVOR10 (0x19A)
00961 #define SPR_BOOKE_IVOR11 (0x19B)
00962 #define SPR_BOOKE_IVOR12 (0x19C)
00963 #define SPR_BOOKE_IVOR13 (0x19D)
00964 #define SPR_BOOKE_IVOR14 (0x19E)
00965 #define SPR_BOOKE_IVOR15 (0x19F)
00966 #define SPR_BOOKE_SPEFSCR (0x200)
00967 #define SPR_Exxx_BBEAR (0x201)
00968 #define SPR_Exxx_BBTAR (0x202)
00969 #define SPR_Exxx_L1CFG0 (0x203)
00970 #define SPR_Exxx_NPIDR (0x205)
00971 #define SPR_ATBL (0x20E)
00972 #define SPR_ATBU (0x20F)
00973 #define SPR_IBAT0U (0x210)
00974 #define SPR_BOOKE_IVOR32 (0x210)
00975 #define SPR_RCPU_MI_GRA (0x210)
00976 #define SPR_IBAT0L (0x211)
00977 #define SPR_BOOKE_IVOR33 (0x211)
00978 #define SPR_IBAT1U (0x212)
00979 #define SPR_BOOKE_IVOR34 (0x212)
00980 #define SPR_IBAT1L (0x213)
00981 #define SPR_BOOKE_IVOR35 (0x213)
00982 #define SPR_IBAT2U (0x214)
00983 #define SPR_BOOKE_IVOR36 (0x214)
00984 #define SPR_IBAT2L (0x215)
00985 #define SPR_BOOKE_IVOR37 (0x215)
00986 #define SPR_IBAT3U (0x216)
00987 #define SPR_IBAT3L (0x217)
00988 #define SPR_DBAT0U (0x218)
00989 #define SPR_RCPU_L2U_GRA (0x218)
00990 #define SPR_DBAT0L (0x219)
00991 #define SPR_DBAT1U (0x21A)
00992 #define SPR_DBAT1L (0x21B)
00993 #define SPR_DBAT2U (0x21C)
00994 #define SPR_DBAT2L (0x21D)
00995 #define SPR_DBAT3U (0x21E)
00996 #define SPR_DBAT3L (0x21F)
00997 #define SPR_IBAT4U (0x230)
00998 #define SPR_RPCU_BBCMCR (0x230)
00999 #define SPR_MPC_IC_CST (0x230)
01000 #define SPR_Exxx_CTXCR (0x230)
01001 #define SPR_IBAT4L (0x231)
01002 #define SPR_MPC_IC_ADR (0x231)
01003 #define SPR_Exxx_DBCR3 (0x231)
01004 #define SPR_IBAT5U (0x232)
01005 #define SPR_MPC_IC_DAT (0x232)
01006 #define SPR_Exxx_DBCNT (0x232)
01007 #define SPR_IBAT5L (0x233)
01008 #define SPR_IBAT6U (0x234)
01009 #define SPR_IBAT6L (0x235)
01010 #define SPR_IBAT7U (0x236)
01011 #define SPR_IBAT7L (0x237)
01012 #define SPR_DBAT4U (0x238)
01013 #define SPR_RCPU_L2U_MCR (0x238)
01014 #define SPR_MPC_DC_CST (0x238)
01015 #define SPR_Exxx_ALTCTXCR (0x238)
01016 #define SPR_DBAT4L (0x239)
01017 #define SPR_MPC_DC_ADR (0x239)
01018 #define SPR_DBAT5U (0x23A)
01019 #define SPR_BOOKE_MCSRR0 (0x23A)
01020 #define SPR_MPC_DC_DAT (0x23A)
01021 #define SPR_DBAT5L (0x23B)
01022 #define SPR_BOOKE_MCSRR1 (0x23B)
01023 #define SPR_DBAT6U (0x23C)
01024 #define SPR_BOOKE_MCSR (0x23C)
01025 #define SPR_DBAT6L (0x23D)
01026 #define SPR_Exxx_MCAR (0x23D)
01027 #define SPR_DBAT7U (0x23E)
01028 #define SPR_BOOKE_DSRR0 (0x23E)
01029 #define SPR_DBAT7L (0x23F)
01030 #define SPR_BOOKE_DSRR1 (0x23F)
01031 #define SPR_BOOKE_SPRG8 (0x25C)
01032 #define SPR_BOOKE_SPRG9 (0x25D)
01033 #define SPR_BOOKE_MAS0 (0x270)
01034 #define SPR_BOOKE_MAS1 (0x271)
01035 #define SPR_BOOKE_MAS2 (0x272)
01036 #define SPR_BOOKE_MAS3 (0x273)
01037 #define SPR_BOOKE_MAS4 (0x274)
01038 #define SPR_BOOKE_MAS5 (0x275)
01039 #define SPR_BOOKE_MAS6 (0x276)
01040 #define SPR_BOOKE_PID1 (0x279)
01041 #define SPR_BOOKE_PID2 (0x27A)
01042 #define SPR_MPC_DPDR (0x280)
01043 #define SPR_MPC_IMMR (0x288)
01044 #define SPR_BOOKE_TLB0CFG (0x2B0)
01045 #define SPR_BOOKE_TLB1CFG (0x2B1)
01046 #define SPR_BOOKE_TLB2CFG (0x2B2)
01047 #define SPR_BOOKE_TLB3CFG (0x2B3)
01048 #define SPR_BOOKE_EPR (0x2BE)
01049 #define SPR_PERF0 (0x300)
01050 #define SPR_RCPU_MI_RBA0 (0x300)
01051 #define SPR_MPC_MI_CTR (0x300)
01052 #define SPR_PERF1 (0x301)
01053 #define SPR_RCPU_MI_RBA1 (0x301)
01054 #define SPR_PERF2 (0x302)
01055 #define SPR_RCPU_MI_RBA2 (0x302)
01056 #define SPR_MPC_MI_AP (0x302)
01057 #define SPR_PERF3 (0x303)
01058 #define SPR_620_PMC1R (0x303)
01059 #define SPR_RCPU_MI_RBA3 (0x303)
01060 #define SPR_MPC_MI_EPN (0x303)
01061 #define SPR_PERF4 (0x304)
01062 #define SPR_620_PMC2R (0x304)
01063 #define SPR_PERF5 (0x305)
01064 #define SPR_MPC_MI_TWC (0x305)
01065 #define SPR_PERF6 (0x306)
01066 #define SPR_MPC_MI_RPN (0x306)
01067 #define SPR_PERF7 (0x307)
01068 #define SPR_PERF8 (0x308)
01069 #define SPR_RCPU_L2U_RBA0 (0x308)
01070 #define SPR_MPC_MD_CTR (0x308)
01071 #define SPR_PERF9 (0x309)
01072 #define SPR_RCPU_L2U_RBA1 (0x309)
01073 #define SPR_MPC_MD_CASID (0x309)
01074 #define SPR_PERFA (0x30A)
01075 #define SPR_RCPU_L2U_RBA2 (0x30A)
01076 #define SPR_MPC_MD_AP (0x30A)
01077 #define SPR_PERFB (0x30B)
01078 #define SPR_620_MMCR0R (0x30B)
01079 #define SPR_RCPU_L2U_RBA3 (0x30B)
01080 #define SPR_MPC_MD_EPN (0x30B)
01081 #define SPR_PERFC (0x30C)
01082 #define SPR_MPC_MD_TWB (0x30C)
01083 #define SPR_PERFD (0x30D)
01084 #define SPR_MPC_MD_TWC (0x30D)
01085 #define SPR_PERFE (0x30E)
01086 #define SPR_MPC_MD_RPN (0x30E)
01087 #define SPR_PERFF (0x30F)
01088 #define SPR_MPC_MD_TW (0x30F)
01089 #define SPR_UPERF0 (0x310)
01090 #define SPR_UPERF1 (0x311)
01091 #define SPR_UPERF2 (0x312)
01092 #define SPR_UPERF3 (0x313)
01093 #define SPR_620_PMC1W (0x313)
01094 #define SPR_UPERF4 (0x314)
01095 #define SPR_620_PMC2W (0x314)
01096 #define SPR_UPERF5 (0x315)
01097 #define SPR_UPERF6 (0x316)
01098 #define SPR_UPERF7 (0x317)
01099 #define SPR_UPERF8 (0x318)
01100 #define SPR_UPERF9 (0x319)
01101 #define SPR_UPERFA (0x31A)
01102 #define SPR_UPERFB (0x31B)
01103 #define SPR_620_MMCR0W (0x31B)
01104 #define SPR_UPERFC (0x31C)
01105 #define SPR_UPERFD (0x31D)
01106 #define SPR_UPERFE (0x31E)
01107 #define SPR_UPERFF (0x31F)
01108 #define SPR_RCPU_MI_RA0 (0x320)
01109 #define SPR_MPC_MI_DBCAM (0x320)
01110 #define SPR_RCPU_MI_RA1 (0x321)
01111 #define SPR_MPC_MI_DBRAM0 (0x321)
01112 #define SPR_RCPU_MI_RA2 (0x322)
01113 #define SPR_MPC_MI_DBRAM1 (0x322)
01114 #define SPR_RCPU_MI_RA3 (0x323)
01115 #define SPR_RCPU_L2U_RA0 (0x328)
01116 #define SPR_MPC_MD_DBCAM (0x328)
01117 #define SPR_RCPU_L2U_RA1 (0x329)
01118 #define SPR_MPC_MD_DBRAM0 (0x329)
01119 #define SPR_RCPU_L2U_RA2 (0x32A)
01120 #define SPR_MPC_MD_DBRAM1 (0x32A)
01121 #define SPR_RCPU_L2U_RA3 (0x32B)
01122 #define SPR_440_INV0 (0x370)
01123 #define SPR_440_INV1 (0x371)
01124 #define SPR_440_INV2 (0x372)
01125 #define SPR_440_INV3 (0x373)
01126 #define SPR_440_ITV0 (0x374)
01127 #define SPR_440_ITV1 (0x375)
01128 #define SPR_440_ITV2 (0x376)
01129 #define SPR_440_ITV3 (0x377)
01130 #define SPR_440_CCR1 (0x378)
01131 #define SPR_DCRIPR (0x37B)
01132 #define SPR_PPR (0x380)
01133 #define SPR_750_GQR0 (0x390)
01134 #define SPR_440_DNV0 (0x390)
01135 #define SPR_750_GQR1 (0x391)
01136 #define SPR_440_DNV1 (0x391)
01137 #define SPR_750_GQR2 (0x392)
01138 #define SPR_440_DNV2 (0x392)
01139 #define SPR_750_GQR3 (0x393)
01140 #define SPR_440_DNV3 (0x393)
01141 #define SPR_750_GQR4 (0x394)
01142 #define SPR_440_DTV0 (0x394)
01143 #define SPR_750_GQR5 (0x395)
01144 #define SPR_440_DTV1 (0x395)
01145 #define SPR_750_GQR6 (0x396)
01146 #define SPR_440_DTV2 (0x396)
01147 #define SPR_750_GQR7 (0x397)
01148 #define SPR_440_DTV3 (0x397)
01149 #define SPR_750_THRM4 (0x398)
01150 #define SPR_750CL_HID2 (0x398)
01151 #define SPR_440_DVLIM (0x398)
01152 #define SPR_750_WPAR (0x399)
01153 #define SPR_440_IVLIM (0x399)
01154 #define SPR_750_DMAU (0x39A)
01155 #define SPR_750_DMAL (0x39B)
01156 #define SPR_440_RSTCFG (0x39B)
01157 #define SPR_BOOKE_DCDBTRL (0x39C)
01158 #define SPR_BOOKE_DCDBTRH (0x39D)
01159 #define SPR_BOOKE_ICDBTRL (0x39E)
01160 #define SPR_BOOKE_ICDBTRH (0x39F)
01161 #define SPR_UMMCR2 (0x3A0)
01162 #define SPR_UPMC5 (0x3A1)
01163 #define SPR_UPMC6 (0x3A2)
01164 #define SPR_UBAMR (0x3A7)
01165 #define SPR_UMMCR0 (0x3A8)
01166 #define SPR_UPMC1 (0x3A9)
01167 #define SPR_UPMC2 (0x3AA)
01168 #define SPR_USIAR (0x3AB)
01169 #define SPR_UMMCR1 (0x3AC)
01170 #define SPR_UPMC3 (0x3AD)
01171 #define SPR_UPMC4 (0x3AE)
01172 #define SPR_USDA (0x3AF)
01173 #define SPR_40x_ZPR (0x3B0)
01174 #define SPR_BOOKE_MAS7 (0x3B0)
01175 #define SPR_620_PMR0 (0x3B0)
01176 #define SPR_MMCR2 (0x3B0)
01177 #define SPR_PMC5 (0x3B1)
01178 #define SPR_40x_PID (0x3B1)
01179 #define SPR_620_PMR1 (0x3B1)
01180 #define SPR_PMC6 (0x3B2)
01181 #define SPR_440_MMUCR (0x3B2)
01182 #define SPR_620_PMR2 (0x3B2)
01183 #define SPR_4xx_CCR0 (0x3B3)
01184 #define SPR_BOOKE_EPLC (0x3B3)
01185 #define SPR_620_PMR3 (0x3B3)
01186 #define SPR_405_IAC3 (0x3B4)
01187 #define SPR_BOOKE_EPSC (0x3B4)
01188 #define SPR_620_PMR4 (0x3B4)
01189 #define SPR_405_IAC4 (0x3B5)
01190 #define SPR_620_PMR5 (0x3B5)
01191 #define SPR_405_DVC1 (0x3B6)
01192 #define SPR_620_PMR6 (0x3B6)
01193 #define SPR_405_DVC2 (0x3B7)
01194 #define SPR_620_PMR7 (0x3B7)
01195 #define SPR_BAMR (0x3B7)
01196 #define SPR_MMCR0 (0x3B8)
01197 #define SPR_620_PMR8 (0x3B8)
01198 #define SPR_PMC1 (0x3B9)
01199 #define SPR_40x_SGR (0x3B9)
01200 #define SPR_620_PMR9 (0x3B9)
01201 #define SPR_PMC2 (0x3BA)
01202 #define SPR_40x_DCWR (0x3BA)
01203 #define SPR_620_PMRA (0x3BA)
01204 #define SPR_SIAR (0x3BB)
01205 #define SPR_405_SLER (0x3BB)
01206 #define SPR_620_PMRB (0x3BB)
01207 #define SPR_MMCR1 (0x3BC)
01208 #define SPR_405_SU0R (0x3BC)
01209 #define SPR_620_PMRC (0x3BC)
01210 #define SPR_401_SKR (0x3BC)
01211 #define SPR_PMC3 (0x3BD)
01212 #define SPR_405_DBCR1 (0x3BD)
01213 #define SPR_620_PMRD (0x3BD)
01214 #define SPR_PMC4 (0x3BE)
01215 #define SPR_620_PMRE (0x3BE)
01216 #define SPR_SDA (0x3BF)
01217 #define SPR_620_PMRF (0x3BF)
01218 #define SPR_403_VTBL (0x3CC)
01219 #define SPR_403_VTBU (0x3CD)
01220 #define SPR_DMISS (0x3D0)
01221 #define SPR_DCMP (0x3D1)
01222 #define SPR_HASH1 (0x3D2)
01223 #define SPR_HASH2 (0x3D3)
01224 #define SPR_BOOKE_ICDBDR (0x3D3)
01225 #define SPR_TLBMISS (0x3D4)
01226 #define SPR_IMISS (0x3D4)
01227 #define SPR_40x_ESR (0x3D4)
01228 #define SPR_PTEHI (0x3D5)
01229 #define SPR_ICMP (0x3D5)
01230 #define SPR_40x_DEAR (0x3D5)
01231 #define SPR_PTELO (0x3D6)
01232 #define SPR_RPA (0x3D6)
01233 #define SPR_40x_EVPR (0x3D6)
01234 #define SPR_L3PM (0x3D7)
01235 #define SPR_403_CDBCR (0x3D7)
01236 #define SPR_L3ITCR0 (0x3D8)
01237 #define SPR_TCR (0x3D8)
01238 #define SPR_40x_TSR (0x3D8)
01239 #define SPR_IBR (0x3DA)
01240 #define SPR_40x_TCR (0x3DA)
01241 #define SPR_ESASRR (0x3DB)
01242 #define SPR_40x_PIT (0x3DB)
01243 #define SPR_403_TBL (0x3DC)
01244 #define SPR_403_TBU (0x3DD)
01245 #define SPR_SEBR (0x3DE)
01246 #define SPR_40x_SRR2 (0x3DE)
01247 #define SPR_SER (0x3DF)
01248 #define SPR_40x_SRR3 (0x3DF)
01249 #define SPR_L3OHCR (0x3E8)
01250 #define SPR_L3ITCR1 (0x3E9)
01251 #define SPR_L3ITCR2 (0x3EA)
01252 #define SPR_L3ITCR3 (0x3EB)
01253 #define SPR_HID0 (0x3F0)
01254 #define SPR_40x_DBSR (0x3F0)
01255 #define SPR_HID1 (0x3F1)
01256 #define SPR_IABR (0x3F2)
01257 #define SPR_40x_DBCR0 (0x3F2)
01258 #define SPR_601_HID2 (0x3F2)
01259 #define SPR_Exxx_L1CSR0 (0x3F2)
01260 #define SPR_ICTRL (0x3F3)
01261 #define SPR_HID2 (0x3F3)
01262 #define SPR_750CL_HID4 (0x3F3)
01263 #define SPR_Exxx_L1CSR1 (0x3F3)
01264 #define SPR_440_DBDR (0x3F3)
01265 #define SPR_LDSTDB (0x3F4)
01266 #define SPR_750_TDCL (0x3F4)
01267 #define SPR_40x_IAC1 (0x3F4)
01268 #define SPR_MMUCSR0 (0x3F4)
01269 #define SPR_DABR (0x3F5)
01270 #define DABR_MASK (~(target_ulong)0x7)
01271 #define SPR_Exxx_BUCSR (0x3F5)
01272 #define SPR_40x_IAC2 (0x3F5)
01273 #define SPR_601_HID5 (0x3F5)
01274 #define SPR_40x_DAC1 (0x3F6)
01275 #define SPR_MSSCR0 (0x3F6)
01276 #define SPR_970_HID5 (0x3F6)
01277 #define SPR_MSSSR0 (0x3F7)
01278 #define SPR_MSSCR1 (0x3F7)
01279 #define SPR_DABRX (0x3F7)
01280 #define SPR_40x_DAC2 (0x3F7)
01281 #define SPR_MMUCFG (0x3F7)
01282 #define SPR_LDSTCR (0x3F8)
01283 #define SPR_L2PMCR (0x3F8)
01284 #define SPR_750FX_HID2 (0x3F8)
01285 #define SPR_620_BUSCSR (0x3F8)
01286 #define SPR_Exxx_L1FINV0 (0x3F8)
01287 #define SPR_L2CR (0x3F9)
01288 #define SPR_620_L2CR (0x3F9)
01289 #define SPR_L3CR (0x3FA)
01290 #define SPR_750_TDCH (0x3FA)
01291 #define SPR_IABR2 (0x3FA)
01292 #define SPR_40x_DCCR (0x3FA)
01293 #define SPR_620_L2SR (0x3FA)
01294 #define SPR_ICTC (0x3FB)
01295 #define SPR_40x_ICCR (0x3FB)
01296 #define SPR_THRM1 (0x3FC)
01297 #define SPR_403_PBL1 (0x3FC)
01298 #define SPR_SP (0x3FD)
01299 #define SPR_THRM2 (0x3FD)
01300 #define SPR_403_PBU1 (0x3FD)
01301 #define SPR_604_HID13 (0x3FD)
01302 #define SPR_LT (0x3FE)
01303 #define SPR_THRM3 (0x3FE)
01304 #define SPR_RCPU_FPECR (0x3FE)
01305 #define SPR_403_PBL2 (0x3FE)
01306 #define SPR_PIR (0x3FF)
01307 #define SPR_403_PBU2 (0x3FF)
01308 #define SPR_601_HID15 (0x3FF)
01309 #define SPR_604_HID15 (0x3FF)
01310 #define SPR_E500_SVR (0x3FF)
01311
01312
01313
01314
01315
01316 enum {
01317
01318 ACCESS_USER = 0x00,
01319 ACCESS_SUPER = 0x01,
01320
01321 ACCESS_CODE = 0x10,
01322 ACCESS_INT = 0x20,
01323 ACCESS_FLOAT = 0x30,
01324 ACCESS_RES = 0x40,
01325 ACCESS_EXT = 0x50,
01326 ACCESS_CACHE = 0x60,
01327 };
01328
01329
01330
01331
01332
01333 enum {
01334
01335 PPC6xx_INPUT_HRESET = 0,
01336 PPC6xx_INPUT_SRESET = 1,
01337 PPC6xx_INPUT_CKSTP_IN = 2,
01338 PPC6xx_INPUT_MCP = 3,
01339 PPC6xx_INPUT_SMI = 4,
01340 PPC6xx_INPUT_INT = 5,
01341 PPC6xx_INPUT_TBEN = 6,
01342 PPC6xx_INPUT_WAKEUP = 7,
01343 PPC6xx_INPUT_NB,
01344 };
01345
01346 enum {
01347
01348 PPCBookE_INPUT_HRESET = 0,
01349 PPCBookE_INPUT_SRESET = 1,
01350 PPCBookE_INPUT_CKSTP_IN = 2,
01351 PPCBookE_INPUT_MCP = 3,
01352 PPCBookE_INPUT_SMI = 4,
01353 PPCBookE_INPUT_INT = 5,
01354 PPCBookE_INPUT_CINT = 6,
01355 PPCBookE_INPUT_NB,
01356 };
01357
01358 enum {
01359
01360 PPCE500_INPUT_RESET_CORE = 0,
01361 PPCE500_INPUT_MCK = 1,
01362 PPCE500_INPUT_CINT = 3,
01363 PPCE500_INPUT_INT = 4,
01364 PPCE500_INPUT_DEBUG = 6,
01365 PPCE500_INPUT_NB,
01366 };
01367
01368 enum {
01369
01370 PPC40x_INPUT_RESET_CORE = 0,
01371 PPC40x_INPUT_RESET_CHIP = 1,
01372 PPC40x_INPUT_RESET_SYS = 2,
01373 PPC40x_INPUT_CINT = 3,
01374 PPC40x_INPUT_INT = 4,
01375 PPC40x_INPUT_HALT = 5,
01376 PPC40x_INPUT_DEBUG = 6,
01377 PPC40x_INPUT_NB,
01378 };
01379
01380 enum {
01381
01382 PPCRCPU_INPUT_PORESET = 0,
01383 PPCRCPU_INPUT_HRESET = 1,
01384 PPCRCPU_INPUT_SRESET = 2,
01385 PPCRCPU_INPUT_IRQ0 = 3,
01386 PPCRCPU_INPUT_IRQ1 = 4,
01387 PPCRCPU_INPUT_IRQ2 = 5,
01388 PPCRCPU_INPUT_IRQ3 = 6,
01389 PPCRCPU_INPUT_IRQ4 = 7,
01390 PPCRCPU_INPUT_IRQ5 = 8,
01391 PPCRCPU_INPUT_IRQ6 = 9,
01392 PPCRCPU_INPUT_IRQ7 = 10,
01393 PPCRCPU_INPUT_NB,
01394 };
01395
01396 #if defined(TARGET_PPC64)
01397 enum {
01398
01399 PPC970_INPUT_HRESET = 0,
01400 PPC970_INPUT_SRESET = 1,
01401 PPC970_INPUT_CKSTP = 2,
01402 PPC970_INPUT_TBEN = 3,
01403 PPC970_INPUT_MCP = 4,
01404 PPC970_INPUT_INT = 5,
01405 PPC970_INPUT_THINT = 6,
01406 PPC970_INPUT_NB,
01407 };
01408 #endif
01409
01410
01411 enum {
01412
01413 PPC_INTERRUPT_RESET = 0,
01414 PPC_INTERRUPT_WAKEUP,
01415 PPC_INTERRUPT_MCK,
01416 PPC_INTERRUPT_EXT,
01417 PPC_INTERRUPT_SMI,
01418 PPC_INTERRUPT_CEXT,
01419 PPC_INTERRUPT_DEBUG,
01420 PPC_INTERRUPT_THERM,
01421
01422 PPC_INTERRUPT_DECR,
01423 PPC_INTERRUPT_HDECR,
01424 PPC_INTERRUPT_PIT,
01425 PPC_INTERRUPT_FIT,
01426 PPC_INTERRUPT_WDT,
01427 PPC_INTERRUPT_CDOORBELL,
01428 PPC_INTERRUPT_DOORBELL,
01429 PPC_INTERRUPT_PERFM,
01430 };
01431
01432
01433
01434 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
01435 {
01436 env->nip = tb->pc;
01437 }
01438
01439 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
01440 target_ulong *cs_base, int *flags)
01441 {
01442 *pc = env->nip;
01443 *cs_base = 0;
01444 *flags = env->hflags;
01445 }
01446
01447 #endif