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convProc Class Reference

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#include <ssb_sim-outorder.h>

Inheritance diagram for convProc:
prefetchProc mainProc

Public Member Functions

unsigned long long TimeStamp () const
virtual bool checkCache (const simAddress addr)
virtual void insertCache (const simAddress mem)
void wakeUpMM (map< instruction *, RUU_station * >::iterator &mi)
void wakeUpPrefetched (instruction *inst)
virtual void sendToMem (instruction *i)
 convProc (string configFile, processor *p, int maxMMOut, int coreNum, map< string, string > prefetchInit)
bool pipeClear ()
virtual void handleMemEvent (instruction *inst)

Data Fields

unsigned long long iMix [LASTINST]

Protected Types

enum  { spec_ID, spec_WB, spec_CT }
typedef map< instruction *, int > latencyMap

Protected Member Functions

virtual unsigned getFEBDelay ()
void mmSendParcel (instruction *inst)
void mainMemAccess (instruction *)
unsigned int mem_access_latency (int blk_sz)
virtual unsigned int cplx_mem_access_latency (const enum mem_cmd cmd, const md_addr_t baddr, const int bsize, bool &)
virtual void noteWrite (const simAddress a)=0
virtual void handleCoher (const simAddress, const enum mem_cmd cmd)=0
uint dl1_access_fn (enum mem_cmd cmd, md_addr_t baddr, int bsize, struct cache_blk_t *blk, tick_t now, bool &)
uint dl2_access_fn (enum mem_cmd cmd, md_addr_t baddr, int bsize, cache_blk_t *blk, tick_t now, bool &)
uint il1_access_fn (enum mem_cmd cmd, md_addr_t baddr, int bsize, struct cache_blk_t *blk, tick_t now, bool &)
uint il2_access_fn (enum mem_cmd cmd, md_addr_t baddr, int bsize, struct cache_blk_t *blk, tick_t now, bool &)
uint itlb_access_fn (enum mem_cmd cmd, md_addr_t baddr, int bsize, struct cache_blk_t *blk, tick_t now, bool &)
uint dtlb_access_fn (enum mem_cmd cmd, md_addr_t baddr, int bsize, struct cache_blk_t *blk, tick_t now, bool &)
void sim_print_stats (FILE *fd)
int ss_main (const char *)
void sim_reg_options (struct opt_odb_t *odb)
void sim_check_options (struct opt_odb_t *odb)
void sim_reg_stats (struct stat_sdb_t *sdb)
void sim_init (void)
void sim_load_prog (const string fuConfStr)
void ruu_init (void)
void lsq_init (void)
void fetch_init (void)
void ruu_dump (FILE *stream)
void lsq_dump (FILE *stream)
void rspec_dump (FILE *stream)
void mspec_dump (FILE *stream)
void fetch_dump (FILE *stream)
void eventq_dump (FILE *stream)
void readyq_dump (FILE *stream)
struct RUU_station * eventq_next_event (void)
void eventq_queue_event (struct RUU_station *rs, tick_t when)
void eventq_init (void)
void readyq_init (void)
void readyq_enqueue (struct RUU_station *rs)
void tracer_recover (void)
void tracer_init (void)
void ruu_recover (int branch_index)
void ruu_link_idep (struct RUU_station *const rs, const int idep_num, const int idep_name)
void ruu_install_odep (struct RUU_station *rs, int odep_num, int odep_name)
void fast_sim_loop ()
void sim_loop (bool)
void ruu_release_fu (void)
void ruu_commit (void)
void ruu_writeback (void)
void lsq_refresh (void)
void ruu_issue (void)
void ruu_dispatch (void)
void ruu_fetch (void)
bool pipeDispatchClear ()
virtual void setup ()=0
virtual void finish ()
virtual void postTic ()=0
void handleReturningStore (instruction *inst)
frameID requestFrame (int size)
simRegister * getFrame (frameID)
void returnFrame (frameID)
virtual bool insertThread (thread *)
void dataCacheInvalidate (simAddress addr)

Static Protected Member Functions

static void ruu_dumpent (struct RUU_station *rs, int index, FILE *stream, int header)
static char * simoo_reg_obj (struct regs_t *regs, int is_write, enum md_reg_type rt, int reg, struct eval_value_t *val)
static char * simoo_mem_obj (struct mem_t *mem, int is_write, md_addr_t addr, char *p, int nbytes)
static char * simoo_mstate_obj (FILE *stream, char *cmd, struct regs_t *regs, struct mem_t *mem)

Protected Attributes

bool simpleFetch
int maxMMStores
int portLimitedCommit
int regPortAvail
int waciLoadExtra
unsigned long long lsqCompares
bool clearPipe
bool isSyncing
int clockRatio
map< frameID, simRegister * > allocatedFrames
set< instruction * > mainMemStores
deque< instruction * > retireList
set< instruction * > OOOStores
set< instruction * > condemnedRemotes
map< instruction *, RUU_station * > mainMemLoads
instruction * iFetchBlocker
prefetcher * pref
thread * thr
int instructionSize
int simpleMemory
RS_link_list rs_free_list
struct RS_link last_op
md_addr_t pred_PC
md_addr_t recover_PC
md_addr_t fetch_regs_PC
md_addr_t fetch_pred_PC
struct fetch_rec * fetch_data
int fetch_num
int fetch_tail
int fetch_head
int last_inst_missed
int last_inst_tmissed
struct RUU_station * RUU
int RUU_head
int RUU_tail
int RUU_num
struct RUU_station * LSQ
int LSQ_head
int LSQ_tail
int LSQ_num
struct RS_link * event_queue
struct RS_link * ready_queue
unsigned int use_spec_cv [CV_BMAP_SZ]
struct CV_link create_vector [MD_TOTAL_REGS+2]
struct CV_link spec_create_vector [MD_TOTAL_REGS+2]
tick_t create_vector_rt [MD_TOTAL_REGS+2]
tick_t spec_create_vector_rt [MD_TOTAL_REGS+2]
unsigned int max_insts
int fastfwd_count
word_t stop_PC
int ptrace_nelt
char * ptrace_opts [2]
int ruu_ifq_size
int ruu_branch_penalty
int fetch_speed
char * pred_type
int bimod_nelt
int bimod_config [1]
int twolev_nelt
int twolev_config [4]
int comb_nelt
int comb_config [1]
int ras_size
int btb_nelt
int btb_config [2]
int ruu_decode_width
int ruu_issue_width
int ruu_inorder_issue
int ruu_include_spec
int ruu_commit_width
int RUU_size
int LSQ_size
char * cache_dl1_opt
int cache_dl1_lat
char * cache_dl2_opt
int cache_dl2_lat
char * cache_il1_opt
int cache_il1_lat
char * cache_il2_opt
int cache_il2_lat
int flush_on_syscalls
int compress_icache_addrs
int mem_nelt
int mem_lat [2]
int mem_bus_width
char * itlb_opt
char * dtlb_opt
int tlb_miss_lat
int res_ialu
int res_imult
int res_memport
int res_fpalu
int res_fpmult
int pcstat_nelt
char * pcstat_vars [MAX_PCSTAT_VARS]
struct opt_odb_t * sim_odb
struct stat_sdb_t * sim_sdb
counter_t sim_num_insn
counter_t sim_total_insn
counter_t sim_num_refs
counter_t sim_total_refs
counter_t sim_num_loads
counter_t sim_total_loads
counter_t sim_num_branches
counter_t sim_total_branches
counter_t IFQ_count
counter_t IFQ_fcount
counter_t RUU_count
counter_t RUU_fcount
counter_t LSQ_count
map< int, counter_t > LSQ_hist
counter_t LSQ_fcount
counter_t sim_invalid_addrs
time_t sim_start_time
time_t sim_end_time
int sim_elapsed_time
unsigned int inst_seq
unsigned int ptrace_seq
bool spec_mode
int lsq_mult
unsigned ruu_fetch_issue_delay
unsigned ruu_dispatch_delay
int pred_perfect
char * bpred_spec_opt
enum convProc:: { ... }  bpred_spec_update
struct cache_t * cache_il1
struct cache_t * cache_il2
struct cache_t * cache_dl1
struct cache_t * cache_dl2
struct cache_t * itlb
struct cache_t * dtlb
struct bpred_t * pred
struct res_pool * fu_pool
struct stat_stat_t * pcstat_stats [MAX_PCSTAT_VARS]
counter_t pcstat_lastvals [MAX_PCSTAT_VARS]
struct stat_stat_t * pcstat_sdists [MAX_PCSTAT_VARS]
latencyMap extraInstLat
instruction * committingInst

Friends

struct CV_link

Detailed Description

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The documentation for this class was generated from the following files:
Generated on Fri Oct 22 2010 11:02:36 for SST by  doxygen 1.7.1